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ESP32-S2FH2
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Espressif Systems RF and Wireless, 56-VFQFN Exposed Pad. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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ESP32-S2FH2
Espressif Systems · RF and Wireless · 56-VFQFN Exposed Pad
ESP32-S2FH2 from Espressif Systems, in a 56-VFQFN Exposed Pad. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDDA | power_in | Analog power domain supply input for the chip's analog circuitry. |
| 2 | LNA_IN | bidirectional | RF low-noise amplifier input/output signal for the 2.4 GHz receive path. |
| 3 | VDD3P3 | power_in | Analog power domain supply input. |
| 4 | VDD3P3 | power_in | Analog power domain supply input. |
| 5 | GPIO0 | bidirectional | Strapping pin for chip boot mode with internal weak pull-up at reset; also RTC_GPIO0 and sar_i2c_scl_0 function, powered by VDD3P3_RTC_IO. |
| 6 | GPIO1 | bidirectional | General-purpose IO with RTC_GPIO1, TOUCH1 and ADC1_CH0 functions, powered by VDD3P3_RTC_IO. |
| 7 | GPIO2 | bidirectional | General-purpose IO with RTC_GPIO2, TOUCH2 and ADC1_CH1 functions, powered by VDD3P3_RTC_IO. |
| 8 | GPIO3 | bidirectional | General-purpose IO with RTC_GPIO3, TOUCH3 and ADC1_CH2 functions, powered by VDD3P3_RTC_IO. |
| 9 | GPIO4 | bidirectional | General-purpose IO with RTC_GPIO4, TOUCH4 and ADC1_CH3 functions, powered by VDD3P3_RTC_IO. |
| 10 | GPIO5 | bidirectional | General-purpose IO with RTC_GPIO5, TOUCH5 and ADC1_CH4 functions, powered by VDD3P3_RTC_IO. |
| 11 | GPIO6 | bidirectional | General-purpose IO with RTC_GPIO6, TOUCH6 and ADC1_CH5 functions, powered by VDD3P3_RTC_IO. |
| 12 | GPIO7 | bidirectional | General-purpose IO with RTC_GPIO7, TOUCH7 and ADC1_CH6 functions, powered by VDD3P3_RTC_IO. |
| 13 | GPIO8 | bidirectional | General-purpose IO with RTC_GPIO8, TOUCH8, ADC1_CH7 and SUBSPICS1 functions, powered by VDD3P3_RTC_IO. |
| 14 | GPIO9 | bidirectional | General-purpose IO with RTC_GPIO9, TOUCH9, ADC1_CH8 and input enabled at reset, powered by VDD3P3_RTC_IO. |
| 15 | GPIO10 | bidirectional | General-purpose IO with RTC_GPIO10, TOUCH10, ADC1_CH9 and input enabled at reset, powered by VDD3P3_RTC_IO. |
| 16 | GPIO11 | bidirectional | General-purpose IO with RTC_GPIO11, TOUCH11, ADC2_CH0 and input enabled at reset, powered by VDD3P3_RTC_IO. |
| 17 | GPIO12 | bidirectional | General-purpose IO with RTC_GPIO12, TOUCH12, ADC2_CH1 and input enabled at reset, powered by VDD3P3_RTC_IO. |
| 18 | GPIO13 | bidirectional | General-purpose IO with RTC_GPIO13, TOUCH13, ADC2_CH2 and input enabled at reset, powered by VDD3P3_RTC_IO. |
| 19 | GPIO14 | bidirectional | General-purpose IO with RTC_GPIO14, TOUCH14, ADC2_CH3 and input enabled at reset, powered by VDD3P3_RTC_IO. |
| 20 | VDD3P3_RTC | power_in | RTC domain supply input. |
| 21 | XTAL_32K_P | bidirectional | Positive 32 kHz clock signal connected to the chip's crystal or oscillator; also RTC_GPIO15 and ADC2_CH4, powered by VDD3P3_RTC_IO. |
| 22 | XTAL_32K_N | bidirectional | Negative 32 kHz clock signal for the external crystal or clock input/output; also RTC_GPIO16 and ADC2_CH5, powered by VDD3P3_RTC_IO. |
| 23 | DAC_1 | bidirectional | DAC channel 1 analog output (8-bit DAC) with RTC_GPIO17 and ADC2_CH6 functions, powered by VDD3P3_RTC_IO. |
| 24 | DAC_2 | bidirectional | DAC channel 2 analog output (8-bit DAC) with RTC_GPIO18 and ADC2_CH7 functions, powered by VDD3P3_RTC_IO. |
| 25 | GPIO19 | bidirectional | General-purpose IO with RTC_GPIO19, USB_D- and ADC2_CH8 functions; USB_D- is the default USB OTG function. |
| 26 | GPIO20 | bidirectional | General-purpose IO with RTC_GPIO20, USB_D+ and ADC2_CH9 functions; USB_D+ is the default USB OTG function. |
| 27 | VDD3P3_RTC_IO | power_in | RTC and part of digital power domain supply input for RTC IO pins. |
| 28 | GPIO21 | bidirectional | General-purpose IO with RTC_GPIO21 function, powered by VDD3P3_RTC_IO. |
| 29 | SPICS1 | bidirectional | SPI chip select 1 connected to in-package PSRAM; internal weak pull-up enabled at reset, powered by VDD_SPI. |
| 30 | VDD_SPI | power_out | Output of the internal regulator for in-package and off-package flash/PSRAM SPI IO; can also be an input backup power line. |
| 31 | SPIHD | bidirectional | SPI hold signal for in-package flash/PSRAM; internal weak pull-up enabled at reset, powered by VDD_SPI. |
| 32 | SPIWP | bidirectional | SPI write-protect signal for in-package flash/PSRAM; internal weak pull-up enabled at reset, powered by VDD_SPI. |
| 33 | SPICS0 | bidirectional | SPI chip select 0 for in-package flash; internal weak pull-up enabled at reset, powered by VDD_SPI. |
| 34 | SPICLK | bidirectional | SPI clock for in-package flash/PSRAM; internal weak pull-up enabled at reset, powered by VDD_SPI. |
| 35 | SPIQ | bidirectional | SPI data line (MISO/SIO1) for in-package flash/PSRAM; internal weak pull-up enabled at reset, powered by VDD_SPI. |
| 36 | SPID | bidirectional | SPI data line (MOSI/SIO0) for in-package flash/PSRAM; internal weak pull-up enabled at reset, powered by VDD_SPI. |
| 37 | GPIO33 | bidirectional | General-purpose IO and 8-line SPI data line IO4 for in-package flash/PSRAM, powered by VDD_SPI or VDD3P3_CPU. |
| 38 | GPIO34 | bidirectional | General-purpose IO and 8-line SPI data line IO5 for in-package flash/PSRAM, powered by VDD_SPI or VDD3P3_CPU. |
| 39 | GPIO35 | bidirectional | General-purpose IO and 8-line SPI data line IO6 for in-package flash/PSRAM, powered by VDD_SPI or VDD3P3_CPU. |
| 40 | GPIO36 | bidirectional | General-purpose IO and 8-line SPI data line IO7 for in-package flash/PSRAM, powered by VDD_SPI or VDD3P3_CPU. |
| 41 | GPIO37 | bidirectional | General-purpose IO and 8-line SPI DQS for in-package flash/PSRAM, powered by VDD_SPI or VDD3P3_CPU. |
| 42 | GPIO38 | bidirectional | General-purpose IO with FSPIWP and SUBSPIWP functions, powered by VDD3P3_CPU. |
| 43 | MTCK | bidirectional | JTAG test clock (MTCK) with input enabled at reset, also GPIO39, powered by VDD3P3_CPU. |
| 44 | MTDO | bidirectional | JTAG test data output (MTDO) with input enabled at reset, also GPIO40, powered by VDD3P3_CPU. |
| 45 | VDD3P3_CPU | power_in | Digital power domain supply input for digital IO pins. |
| 46 | MTDI | bidirectional | JTAG test data input (MTDI) with input enabled at reset, also GPIO41, powered by VDD3P3_CPU. |
| 47 | MTMS | bidirectional | JTAG test mode select (MTMS) with input enabled at reset, also GPIO42, powered by VDD3P3_CPU. |
| 48 | U0TXD | bidirectional | UART0 transmit data with internal weak pull-up at reset, also GPIO43, powered by VDD3P3_CPU. |
| 49 | U0RXD | bidirectional | UART0 receive data with internal weak pull-up at reset, also GPIO44, powered by VDD3P3_CPU. |
| 50 | GPIO45 | bidirectional | Strapping pin for VDD_SPI voltage with internal weak pull-down at reset, powered by VDD3P3_CPU. |
| 51 | VDDA | power_in | Analog power domain supply input. |
| 52 | XTAL_N | passive | Negative external clock input/output connected to the chip's oscillator. |
| 53 | XTAL_P | passive | Positive external clock input/output connected to the chip's oscillator. |
| 54 | VDDA | power_in | Analog power domain supply input. |
| 55 | GPIO46 | input | Input-only GPIO46 strapping pin with fixed internal weak pull-down, powered by VDD3P3_CPU. |
| 56 | CHIP_PU | input | Chip power-up/reset pin: high enables the chip, low shuts it down; must not be left floating. |
| 57 | GND | power_in | External ground connection (exposed pad). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Espressif Systems |
| Package | 56-VFQFN Exposed Pad |
| Category | RF and Wireless |
| Pins | 57 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input power pins allowed input voltage | -0.3 | 3.6 | V | 48 | |||
| Cumulative IO output current | Ioutput | 1800 | mA | 48 | |||
| Storage temperature | TSTORE | -40 | 150 | °C | 48 | ||
| VDDA, VDD3P3, VDD3P3_RTC recommended input voltage | 2.8 | 3.3 | 3.6 | V | 48 | ||
| VDD3P3_RTC_IO recommended input voltage | 3 | 3.3 | 3.6 | V | 48 | ||
| VDD_SPI (as input) | 1.8 | 3.3 | 3.6 | V | as input | 48 | |
| VDD3P3_CPU recommended input voltage | 2.8 | 3.3 | 3.6 | V | 48 | ||
| Cumulative input current | IVDD | 0.5 | A | 48 | |||
| Junction temperature | TJ | -40 | 125 | °C | 48 | ||
| High-level input current | IIH | 50 | nA | 49 | |||
| Low-level input current | IIL | 50 | nA | 49 | |||
| Low-level input voltage | VIL | -0.3 | V | 49 | |||
| Chip reset voltage | VIL_nRST | -0.3 | V | CHIP_PU voltage is within the specified range | 49 | ||
| Differential nonlinearity (DNL) | DNL | -7 | 7 | LSB | ADC connected to an external 100 nF capacitor; DC signal input; Ambient temperature at 25 °C; Wi-Fi off | 50 | |
| Integral nonlinearity (INL) | INL | -12 | 12 | LSB | ADC connected to an external 100 nF capacitor; DC signal input; Ambient temperature at 25 °C; Wi-Fi off | 50 | |
| Sampling rate | 100 | kSPS | 50 | ||||
| Total error ATTEN0 | -10 | 10 | mV | effective measurement range of 0 ~ 700 | 50 | ||
| Total error ATTEN1 | -11 | 11 | mV | effective measurement range of 0 ~ 950 | 50 | ||
| Total error ATTEN2 | -13 | 13 | mV | effective measurement range of 0 ~ 1200 | 50 | ||
| Total error ATTEN3 | -17 | 17 | mV | effective measurement range of 0 ~ 2300 | 50 | ||
| Time reserved for power rails to stabilize before CHIP_PU is pulled high | tST BL | 50 | µs | 27 | |||
| Time reserved for CHIP_PU to stay below VIL_nRST to reset the chip | tRST | 50 | µs | 27 | |||
| Center frequency of operating channel | 2412 | 2484 | MHz | 54 |
CAD (KiCad official)
- Symbol:
ESP32-S2FH2 - Footprint:
Package_DFN_QFN:QFN-56-1EP_7x7mm_P0.4mm_EP5.6x5.6mm - 3D model: 56-VFQFN Exposed Pad (KiCad packages3D, STEP)
- 3D model files:
esp32-s2fh2-etched.step/esp32-s2fh2-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);esp32-s2fh2.step/esp32-s2fh2.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Espressif Systems datasheet (65 pp, sha256
7c0c54f11e79cc77, retrieved 2026-10-27, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# ESP32-S2FH2
**Espressif Systems** · RF and Wireless · 56-VFQFN Exposed Pad
ESP32-S2FH2 from Espressif Systems, in a 56-VFQFN Exposed Pad. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDDA | power_in | Analog power domain supply input for the chip's analog circuitry. |
| 2 | LNA_IN | bidirectional | RF low-noise amplifier input/output signal for the 2.4 GHz receive path. |
| 3 | VDD3P3 | power_in | Analog power domain supply input. |
| 4 | VDD3P3 | power_in | Analog power domain supply input. |
| 5 | GPIO0 | bidirectional | Strapping pin for chip boot mode with internal weak pull-up at reset; also RTC_GPIO0 and sar_i2c_scl_0 function, powered by VDD3P3_RTC_IO. |
| 6 | GPIO1 | bidirectional | General-purpose IO with RTC_GPIO1, TOUCH1 and ADC1_CH0 functions, powered by VDD3P3_RTC_IO. |
| 7 | GPIO2 | bidirectional | General-purpose IO with RTC_GPIO2, TOUCH2 and ADC1_CH1 functions, powered by VDD3P3_RTC_IO. |
| 8 | GPIO3 | bidirectional | General-purpose IO with RTC_GPIO3, TOUCH3 and ADC1_CH2 functions, powered by VDD3P3_RTC_IO. |
| 9 | GPIO4 | bidirectional | General-purpose IO with RTC_GPIO4, TOUCH4 and ADC1_CH3 functions, powered by VDD3P3_RTC_IO. |
| 10 | GPIO5 | bidirectional | General-purpose IO with RTC_GPIO5, TOUCH5 and ADC1_CH4 functions, powered by VDD3P3_RTC_IO. |
| 11 | GPIO6 | bidirectional | General-purpose IO with RTC_GPIO6, TOUCH6 and ADC1_CH5 functions, powered by VDD3P3_RTC_IO. |
| 12 | GPIO7 | bidirectional | General-purpose IO with RTC_GPIO7, TOUCH7 and ADC1_CH6 functions, powered by VDD3P3_RTC_IO. |
| 13 | GPIO8 | bidirectional | General-purpose IO with RTC_GPIO8, TOUCH8, ADC1_CH7 and SUBSPICS1 functions, powered by VDD3P3_RTC_IO. |
| 14 | GPIO9 | bidirectional | General-purpose IO with RTC_GPIO9, TOUCH9, ADC1_CH8 and input enabled at reset, powered by VDD3P3_RTC_IO. |
| 15 | GPIO10 | bidirectional | General-purpose IO with RTC_GPIO10, TOUCH10, ADC1_CH9 and input enabled at reset, powered by VDD3P3_RTC_IO. |
| 16 | GPIO11 | bidirectional | General-purpose IO with RTC_GPIO11, TOUCH11, ADC2_CH0 and input enabled at reset, powered by VDD3P3_RTC_IO. |
| 17 | GPIO12 | bidirectional | General-purpose IO with RTC_GPIO12, TOUCH12, ADC2_CH1 and input enabled at reset, powered by VDD3P3_RTC_IO. |
| 18 | GPIO13 | bidirectional | General-purpose IO with RTC_GPIO13, TOUCH13, ADC2_CH2 and input enabled at reset, powered by VDD3P3_RTC_IO. |
| 19 | GPIO14 | bidirectional | General-purpose IO with RTC_GPIO14, TOUCH14, ADC2_CH3 and input enabled at reset, powered by VDD3P3_RTC_IO. |
| 20 | VDD3P3_RTC | power_in | RTC domain supply input. |
| 21 | XTAL_32K_P | bidirectional | Positive 32 kHz clock signal connected to the chip's crystal or oscillator; also RTC_GPIO15 and ADC2_CH4, powered by VDD3P3_RTC_IO. |
| 22 | XTAL_32K_N | bidirectional | Negative 32 kHz clock signal for the external crystal or clock input/output; also RTC_GPIO16 and ADC2_CH5, powered by VDD3P3_RTC_IO. |
| 23 | DAC_1 | bidirectional | DAC channel 1 analog output (8-bit DAC) with RTC_GPIO17 and ADC2_CH6 functions, powered by VDD3P3_RTC_IO. |
| 24 | DAC_2 | bidirectional | DAC channel 2 analog output (8-bit DAC) with RTC_GPIO18 and ADC2_CH7 functions, powered by VDD3P3_RTC_IO. |
| 25 | GPIO19 | bidirectional | General-purpose IO with RTC_GPIO19, USB_D- and ADC2_CH8 functions; USB_D- is the default USB OTG function. |
| 26 | GPIO20 | bidirectional | General-purpose IO with RTC_GPIO20, USB_D+ and ADC2_CH9 functions; USB_D+ is the default USB OTG function. |
| 27 | VDD3P3_RTC_IO | power_in | RTC and part of digital power domain supply input for RTC IO pins. |
| 28 | GPIO21 | bidirectional | General-purpose IO with RTC_GPIO21 function, powered by VDD3P3_RTC_IO. |
| 29 | SPICS1 | bidirectional | SPI chip select 1 connected to in-package PSRAM; internal weak pull-up enabled at reset, powered by VDD_SPI. |
| 30 | VDD_SPI | power_out | Output of the internal regulator for in-package and off-package flash/PSRAM SPI IO; can also be an input backup power line. |
| 31 | SPIHD | bidirectional | SPI hold signal for in-package flash/PSRAM; internal weak pull-up enabled at reset, powered by VDD_SPI. |
| 32 | SPIWP | bidirectional | SPI write-protect signal for in-package flash/PSRAM; internal weak pull-up enabled at reset, powered by VDD_SPI. |
| 33 | SPICS0 | bidirectional | SPI chip select 0 for in-package flash; internal weak pull-up enabled at reset, powered by VDD_SPI. |
| 34 | SPICLK | bidirectional | SPI clock for in-package flash/PSRAM; internal weak pull-up enabled at reset, powered by VDD_SPI. |
| 35 | SPIQ | bidirectional | SPI data line (MISO/SIO1) for in-package flash/PSRAM; internal weak pull-up enabled at reset, powered by VDD_SPI. |
| 36 | SPID | bidirectional | SPI data line (MOSI/SIO0) for in-package flash/PSRAM; internal weak pull-up enabled at reset, powered by VDD_SPI. |
| 37 | GPIO33 | bidirectional | General-purpose IO and 8-line SPI data line IO4 for in-package flash/PSRAM, powered by VDD_SPI or VDD3P3_CPU. |
| 38 | GPIO34 | bidirectional | General-purpose IO and 8-line SPI data line IO5 for in-package flash/PSRAM, powered by VDD_SPI or VDD3P3_CPU. |
| 39 | GPIO35 | bidirectional | General-purpose IO and 8-line SPI data line IO6 for in-package flash/PSRAM, powered by VDD_SPI or VDD3P3_CPU. |
| 40 | GPIO36 | bidirectional | General-purpose IO and 8-line SPI data line IO7 for in-package flash/PSRAM, powered by VDD_SPI or VDD3P3_CPU. |
| 41 | GPIO37 | bidirectional | General-purpose IO and 8-line SPI DQS for in-package flash/PSRAM, powered by VDD_SPI or VDD3P3_CPU. |
| 42 | GPIO38 | bidirectional | General-purpose IO with FSPIWP and SUBSPIWP functions, powered by VDD3P3_CPU. |
| 43 | MTCK | bidirectional | JTAG test clock (MTCK) with input enabled at reset, also GPIO39, powered by VDD3P3_CPU. |
| 44 | MTDO | bidirectional | JTAG test data output (MTDO) with input enabled at reset, also GPIO40, powered by VDD3P3_CPU. |
| 45 | VDD3P3_CPU | power_in | Digital power domain supply input for digital IO pins. |
| 46 | MTDI | bidirectional | JTAG test data input (MTDI) with input enabled at reset, also GPIO41, powered by VDD3P3_CPU. |
| 47 | MTMS | bidirectional | JTAG test mode select (MTMS) with input enabled at reset, also GPIO42, powered by VDD3P3_CPU. |
| 48 | U0TXD | bidirectional | UART0 transmit data with internal weak pull-up at reset, also GPIO43, powered by VDD3P3_CPU. |
| 49 | U0RXD | bidirectional | UART0 receive data with internal weak pull-up at reset, also GPIO44, powered by VDD3P3_CPU. |
| 50 | GPIO45 | bidirectional | Strapping pin for VDD_SPI voltage with internal weak pull-down at reset, powered by VDD3P3_CPU. |
| 51 | VDDA | power_in | Analog power domain supply input. |
| 52 | XTAL_N | passive | Negative external clock input/output connected to the chip's oscillator. |
| 53 | XTAL_P | passive | Positive external clock input/output connected to the chip's oscillator. |
| 54 | VDDA | power_in | Analog power domain supply input. |
| 55 | GPIO46 | input | Input-only GPIO46 strapping pin with fixed internal weak pull-down, powered by VDD3P3_CPU. |
| 56 | CHIP_PU | input | Chip power-up/reset pin: high enables the chip, low shuts it down; must not be left floating. |
| 57 | GND | power_in | External ground connection (exposed pad). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Espressif Systems |
| Package | 56-VFQFN Exposed Pad |
| Category | RF and Wireless |
| Pins | 57 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input power pins allowed input voltage | | -0.3 | | 3.6 | V | | 48 |
| Cumulative IO output current | Ioutput | | | 1800 | mA | | 48 |
| Storage temperature | TSTORE | -40 | | 150 | °C | | 48 |
| VDDA, VDD3P3, VDD3P3_RTC recommended input voltage | | 2.8 | 3.3 | 3.6 | V | | 48 |
| VDD3P3_RTC_IO recommended input voltage | | 3 | 3.3 | 3.6 | V | | 48 |
| VDD_SPI (as input) | | 1.8 | 3.3 | 3.6 | V | as input | 48 |
| VDD3P3_CPU recommended input voltage | | 2.8 | 3.3 | 3.6 | V | | 48 |
| Cumulative input current | IVDD | 0.5 | | | A | | 48 |
| Junction temperature | TJ | -40 | | 125 | °C | | 48 |
| High-level input current | IIH | | | 50 | nA | | 49 |
| Low-level input current | IIL | | | 50 | nA | | 49 |
| Low-level input voltage | VIL | -0.3 | | | V | | 49 |
| Chip reset voltage | VIL_nRST | -0.3 | | | V | CHIP_PU voltage is within the specified range | 49 |
| Differential nonlinearity (DNL) | DNL | -7 | | 7 | LSB | ADC connected to an external 100 nF capacitor; DC signal input; Ambient temperature at 25 °C; Wi-Fi off | 50 |
| Integral nonlinearity (INL) | INL | -12 | | 12 | LSB | ADC connected to an external 100 nF capacitor; DC signal input; Ambient temperature at 25 °C; Wi-Fi off | 50 |
| Sampling rate | | | | 100 | kSPS | | 50 |
| Total error ATTEN0 | | -10 | | 10 | mV | effective measurement range of 0 ~ 700 | 50 |
| Total error ATTEN1 | | -11 | | 11 | mV | effective measurement range of 0 ~ 950 | 50 |
| Total error ATTEN2 | | -13 | | 13 | mV | effective measurement range of 0 ~ 1200 | 50 |
| Total error ATTEN3 | | -17 | | 17 | mV | effective measurement range of 0 ~ 2300 | 50 |
| Time reserved for power rails to stabilize before CHIP_PU is pulled high | tST BL | 50 | | | µs | | 27 |
| Time reserved for CHIP_PU to stay below VIL_nRST to reset the chip | tRST | 50 | | | µs | | 27 |
| Center frequency of operating channel | | 2412 | | 2484 | MHz | | 54 |
## CAD (KiCad official)
- Symbol: `ESP32-S2FH2`
- Footprint: `Package_DFN_QFN:QFN-56-1EP_7x7mm_P0.4mm_EP5.6x5.6mm`
- 3D model: 56-VFQFN Exposed Pad (KiCad packages3D, STEP)
- 3D model files: `esp32-s2fh2-etched.step` / `esp32-s2fh2-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `esp32-s2fh2.step` / `esp32-s2fh2.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Espressif Systems datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-s2_datasheet_en.pdf) (65 pp, sha256 `7c0c54f11e79cc77`, retrieved 2026-10-27, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/esp32-s2fh2-datasheet.pdf)