component
ESP32-S2
Public Made by Adomby adom
Espressif Systems RF Transceiver ICs, QFN-56-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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ESP32-S2
Espressif Systems · RF Transceiver ICs · QFN-56-EP(7x7)
ESP32-S2 from Espressif Systems, in a QFN-56-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDDA | power_in | Analog power supply; VDDA, VDD3P3 and VDD3P3_RTC are specified at 2.8 V to 3.6 V (3.3 V typical). |
| 2 | LNA_IN | bidirectional | RF input and output pin of the 2.4 GHz front end. |
| 3 | VDD3P3 | power_in | Analog power supply, 2.8 V to 3.6 V (3.3 V typical). |
| 4 | VDD3P3 | power_in | Analog power supply, 2.8 V to 3.6 V (3.3 V typical). |
| 5 | GPIO0 | bidirectional | RTC_GPIO0 / GPIO0 in the VDD3P3_RTC_IO domain; strapping pin with weak pull-up by default, sampled at reset. |
| 6 | GPIO1 | bidirectional | RTC_GPIO1 / GPIO1 with TOUCH1 and ADC1_CH0 functions, powered from VDD3P3_RTC_IO. |
| 7 | GPIO2 | bidirectional | RTC_GPIO2 / GPIO2 with TOUCH2 and ADC1_CH1 functions, powered from VDD3P3_RTC_IO. |
| 8 | GPIO3 | bidirectional | RTC_GPIO3 / GPIO3 with TOUCH3 and ADC1_CH2 functions, powered from VDD3P3_RTC_IO. |
| 9 | GPIO4 | bidirectional | RTC_GPIO4 / GPIO4 with TOUCH4 and ADC1_CH3 functions, powered from VDD3P3_RTC_IO. |
| 10 | GPIO5 | bidirectional | RTC_GPIO5 / GPIO5 with TOUCH5 and ADC1_CH4 functions, powered from VDD3P3_RTC_IO. |
| 11 | GPIO6 | bidirectional | RTC_GPIO6 / GPIO6 with TOUCH6 and ADC1_CH5 functions, powered from VDD3P3_RTC_IO. |
| 12 | GPIO7 | bidirectional | RTC_GPIO7 / GPIO7 with TOUCH7 and ADC1_CH6 functions, powered from VDD3P3_RTC_IO. |
| 13 | GPIO8 | bidirectional | RTC_GPIO8 / GPIO8 with TOUCH8 and ADC1_CH7 functions, powered from VDD3P3_RTC_IO. |
| 14 | GPIO9 | bidirectional | RTC_GPIO9 / GPIO9 with TOUCH9, ADC1_CH8 and FSPIHD functions, powered from VDD3P3_RTC_IO. |
| 15 | GPIO10 | bidirectional | RTC_GPIO10 / GPIO10 with TOUCH10, ADC1_CH9, FSPICS0 and FSPIIO4 functions, powered from VDD3P3_RTC_IO. |
| 16 | GPIO11 | bidirectional | RTC_GPIO11 / GPIO11 with TOUCH11, ADC2_CH0, FSPID and FSPIIO5 functions, powered from VDD3P3_RTC_IO. |
| 17 | GPIO12 | bidirectional | RTC_GPIO12 / GPIO12 with TOUCH12, ADC2_CH1, FSPICLK and FSPIIO6 functions, powered from VDD3P3_RTC_IO. |
| 18 | GPIO13 | bidirectional | RTC_GPIO13 / GPIO13 with TOUCH13, ADC2_CH2, FSPIQ and FSPIIO7 functions, powered from VDD3P3_RTC_IO. |
| 19 | GPIO14 | bidirectional | RTC_GPIO14 / GPIO14 with TOUCH14, ADC2_CH3, FSPIWP and FSPIDQS functions, powered from VDD3P3_RTC_IO. |
| 20 | VDD3P3_RTC | power_in | Analog power supply for the RTC, 2.8 V to 3.6 V (3.3 V typical). |
| 21 | XTAL_32K_P | bidirectional | External 32 kHz crystal input, also RTC_GPIO15 / GPIO15 with ADC2_CH4, U0RTS and powered from VDD3P3_RTC_IO. |
| 22 | XTAL_32K_N | bidirectional | External 32 kHz crystal output, also RTC_GPIO16 / GPIO16 with ADC2_CH5, U0CTS and powered from VDD3P3_RTC_IO. |
| 23 | DAC_1 | bidirectional | 8-bit DAC channel 1 analog output, also RTC_GPIO17 / GPIO17 with ADC2_CH6 and U1TXD; DAC reference is VDD3P3_RTC_IO. |
| 24 | DAC_2 | bidirectional | 8-bit DAC channel 2 analog output, also RTC_GPIO18 / GPIO18 with ADC2_CH7, U1RXD and CLK_OUT3; DAC reference is VDD3P3_RTC_IO. |
| 25 | GPIO19 | bidirectional | RTC_GPIO19 / GPIO19 with ADC2_CH8, U1RTS, CLK_OUT2 and USB D- (full-speed USB OTG). |
| 26 | GPIO20 | bidirectional | RTC_GPIO20 / GPIO20 with ADC2_CH9, U1CTS, CLK_OUT1 and USB D+ (full-speed USB OTG). |
| 27 | VDD3P3_RTC_IO | power_in | RTC IO power input; this supply also feeds the CPU and RTC, rated 3.0 V to 3.6 V (3.3 V typical). |
| 28 | GPIO21 | bidirectional | RTC_GPIO21 / GPIO21 in the VDD3P3_RTC_IO domain. |
| 29 | SPICS1 | bidirectional | SPI chip select 1 (SPICS1 / GPIO26) in the VDD_SPI domain; on ESP32-S2FN4R2 and ESP32-S2R2 it connects to the in-package PSRAM CE#, and it is not recommended for other uses there. |
| 30 | VDD_SPI | power_out | Output of the internal 1.8 V LDO (fed from VDD3P3_RTC_IO) or a power input from VDD3P3_RTC_IO through R_SPI; the internal LDO supplies up to 40 mA at 1.8 V. |
| 31 | SPIHD | bidirectional | SPI HOLD signal (SPIHD / GPIO27) in the VDD_SPI domain; on flash-integrated variants it is connected to the in-package flash and not recommended for other uses. |
| 32 | SPIWP | bidirectional | SPI write-protect signal (SPIWP / GPIO28) in the VDD_SPI domain; on flash-integrated variants it is connected to the in-package flash and not recommended for other uses. |
| 33 | SPICS0 | bidirectional | SPI chip select 0 (SPICS0 / GPIO29) in the VDD_SPI domain; on flash-integrated variants it is connected to the in-package flash and not recommended for other uses. |
| 34 | SPICLK | bidirectional | SPI clock (SPICLK / GPIO30) in the VDD_SPI domain; on flash-integrated variants it is connected to the in-package flash and not recommended for other uses. |
| 35 | SPIQ | bidirectional | SPI data MISO/IO1 (SPIQ / GPIO31) in the VDD_SPI domain; on flash-integrated variants it is connected to the in-package flash and not recommended for other uses. |
| 36 | SPID | bidirectional | SPI data MOSI/IO0 (SPID / GPIO32) in the VDD_SPI domain; on flash-integrated variants it is connected to the in-package flash and not recommended for other uses. |
| 37 | GPIO33 | bidirectional | GPIO33 (SPIIO4, FSPIHD) in the VDD3P3_CPU domain by default, selectable to VDD_SPI by software. |
| 38 | GPIO34 | bidirectional | GPIO34 (SPIIO5, FSPICS0) in the VDD3P3_CPU domain by default, selectable to VDD_SPI by software. |
| 39 | GPIO35 | bidirectional | GPIO35 (SPIIO6, FSPID) in the VDD3P3_CPU domain by default, selectable to VDD_SPI by software. |
| 40 | GPIO36 | bidirectional | GPIO36 (SPIIO7, FSPICLK) in the VDD3P3_CPU domain by default, selectable to VDD_SPI by software. |
| 41 | GPIO37 | bidirectional | GPIO37 (SPIDQS, FSPIQ) in the VDD3P3_CPU domain by default, selectable to VDD_SPI by software. |
| 42 | GPIO38 | bidirectional | General-purpose I/O GPIO38 (FSPIWP) in the VDD3P3_CPU domain. |
| 43 | MTCK | bidirectional | JTAG debug clock MTCK, also GPIO39 and CLK_OUT3, in the VDD3P3_CPU domain. |
| 44 | MTDO | bidirectional | JTAG debug data output MTDO, also GPIO40 and CLK_OUT2, in the VDD3P3_CPU domain. |
| 45 | VDD3P3_CPU | power_in | CPU IO power input, 2.8 V to 3.6 V (3.3 V typical); must not exceed 3.3 V when writing eFuse. |
| 46 | MTDI | bidirectional | JTAG debug data input MTDI, also GPIO41 and CLK_OUT1, in the VDD3P3_CPU domain. |
| 47 | MTMS | bidirectional | JTAG debug mode select MTMS, also GPIO42, in the VDD3P3_CPU domain. |
| 48 | U0TXD | bidirectional | UART0 transmit U0TXD, also GPIO43 and CLK_OUT1; ROM boot log is printed here by default. |
| 49 | U0RXD | bidirectional | UART0 receive U0RXD, also GPIO44 and CLK_OUT2, in the VDD3P3_CPU domain. |
| 50 | GPIO45 | bidirectional | GPIO45 in the VDD3P3_CPU domain; strapping pin that selects the VDD_SPI voltage, with weak pull-down by default. |
| 51 | VDDA | power_in | Analog power supply, 2.8 V to 3.6 V (3.3 V typical). |
| 52 | XTAL_N | passive | External main crystal output; a 40 MHz main crystal is required for the chip to run. |
| 53 | XTAL_P | passive | External main crystal input; a 40 MHz main crystal is required for the chip to run. |
| 54 | VDDA | power_in | Analog power supply, 2.8 V to 3.6 V (3.3 V typical). |
| 55 | GPIO46 | input | Input-only GPIO46 with fixed pull-down and no output capability; strapping pin that controls ROM boot-log printing. |
| 56 | CHIP_PU | input | Chip enable: high enables the chip, low shuts it down; must not be left floating and is powered from VDD3P3_RTC_IO. |
| 57 | GND | power_in | Ground; this is the exposed thermal/ground pad of the QFN-56 package. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Espressif Systems |
| Package | QFN-56-EP(7x7) |
| Category | RF And Wireless |
| Pins | 57 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Power pin voltage (absolute maximum) | VDDA, VDD3P3, VDD3P3_RTC, VDD3P3_CPU, VDD_SPI, VDD3P3_RTC_IO | -0.3 | 3.6 | V | 35 | ||
| IO output total current (absolute maximum) | Ioutput | 1800 | mA | 35 | |||
| Storage temperature | TSTORE | -40 | 150 | °C | 35 | ||
| Power pin voltage VDDA, VDD3P3, VDD3P3_RTC (recommended) | VDDA, VDD3P3, VDD3P3_RTC | 2.8 | 3.3 | 3.6 | V | 电源管脚电压 | 35 |
| Power pin voltage VDD3P3_CPU (recommended) | VDD3P3_CPU | 2.8 | 3.3 | 3.6 | V | 电源管脚电压 | 35 |
| External power supply current | IVDD | 0.5 | A | 单电源供电时 (note 4) | 35 | ||
| Junction temperature | TJ | -40 | 125 | °C | 35 | ||
| Input leakage current, high | IIH | 50 | nA | 36 | |||
| Input leakage current, low | IIL | 50 | nA | 36 | |||
| ADC differential nonlinearity (DNL) | DNL | -7 | 7 | LSB | RTC 控制器；ADC 外接 100 nF 电容；输入为 DC 信号；常温 25 °C；Wi-Fi 关闭 | 36 | |
| ADC integral nonlinearity (INL) | INL | -12 | 12 | LSB | RTC 控制器；ADC 外接 100 nF 电容；输入为 DC 信号；常温 25 °C；Wi-Fi 关闭 | 36 | |
| ESD HBM sensitivity | -2000 | 2000 | V | HBM, JS-001 | 38 | ||
| ESD CDM sensitivity | -500 | 500 | V | CDM, JS-002 | 38 | ||
| Latch-up current | -200 | 200 | mA | JESD78, 过电流 | 38 | ||
| Wi-Fi operating channel center frequency | 2412 | 2484 | MHz | 工作信道中心频率 | 39 | ||
| TX EVM limit | EVM | -25 | -10 | dB | 802.11b, 1 Mbps, @19.5 dBm | 39 | |
| TX EVM limit | EVM | -28 | -5 | dB | 802.11g, 6 Mbps, @18 dBm | 39 | |
| TX EVM limit | EVM | -28 | -25 | dB | 802.11g, 54 Mbps, @18 dBm | 39 | |
| TX EVM limit | EVM | -26 | -5 | dB | 802.11n, HT20, MCS0, @18 dBm | 39 | |
| TX EVM limit | EVM | -30 | -27 | dB | 802.11n, HT20, MCS7, @17 dBm | 39 | |
| CHIP_PU delay after supply power-up | t0 | 50 | µs | CHIP_PU 上电晚于 VDDA、VDD3P3、VDD3P3_RTC、VDD3P3_RTC_IO、VDD3P3_CPU 上电的延时 | 17 | ||
| CHIP_PU low time below VIL_nRST | t1 | 50 | µs | CHIP_PU 电平低于 VIL_nRST 的时间 | 17 | ||
| Strapping pin setup time | tSU | 0 | ms | 拉高 CHIP_PU 激活芯片前电源轨稳定所需时间 | 18 | ||
| Strapping pin hold time | tH | 3 | ms | CHIP_PU 已拉高后 strapping 管脚可读取的时间 | 18 |
CAD (KiCad official)
- Symbol:
ESP32-S2 - Footprint:
Package_DFN_QFN:QFN-56-1EP_7x7mm_P0.4mm_EP4x4mm - 3D model: QFN-56-EP(7x7) (KiCad packages3D, STEP)
- 3D model files:
esp32-s2-etched.step/esp32-s2-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);esp32-s2.step/esp32-s2.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Espressif Systems datasheet (52 pp, sha256
4a9a84db4a708c85, retrieved 2026-10-19, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# ESP32-S2
**Espressif Systems** · RF Transceiver ICs · QFN-56-EP(7x7)
ESP32-S2 from Espressif Systems, in a QFN-56-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDDA | power_in | Analog power supply; VDDA, VDD3P3 and VDD3P3_RTC are specified at 2.8 V to 3.6 V (3.3 V typical). |
| 2 | LNA_IN | bidirectional | RF input and output pin of the 2.4 GHz front end. |
| 3 | VDD3P3 | power_in | Analog power supply, 2.8 V to 3.6 V (3.3 V typical). |
| 4 | VDD3P3 | power_in | Analog power supply, 2.8 V to 3.6 V (3.3 V typical). |
| 5 | GPIO0 | bidirectional | RTC_GPIO0 / GPIO0 in the VDD3P3_RTC_IO domain; strapping pin with weak pull-up by default, sampled at reset. |
| 6 | GPIO1 | bidirectional | RTC_GPIO1 / GPIO1 with TOUCH1 and ADC1_CH0 functions, powered from VDD3P3_RTC_IO. |
| 7 | GPIO2 | bidirectional | RTC_GPIO2 / GPIO2 with TOUCH2 and ADC1_CH1 functions, powered from VDD3P3_RTC_IO. |
| 8 | GPIO3 | bidirectional | RTC_GPIO3 / GPIO3 with TOUCH3 and ADC1_CH2 functions, powered from VDD3P3_RTC_IO. |
| 9 | GPIO4 | bidirectional | RTC_GPIO4 / GPIO4 with TOUCH4 and ADC1_CH3 functions, powered from VDD3P3_RTC_IO. |
| 10 | GPIO5 | bidirectional | RTC_GPIO5 / GPIO5 with TOUCH5 and ADC1_CH4 functions, powered from VDD3P3_RTC_IO. |
| 11 | GPIO6 | bidirectional | RTC_GPIO6 / GPIO6 with TOUCH6 and ADC1_CH5 functions, powered from VDD3P3_RTC_IO. |
| 12 | GPIO7 | bidirectional | RTC_GPIO7 / GPIO7 with TOUCH7 and ADC1_CH6 functions, powered from VDD3P3_RTC_IO. |
| 13 | GPIO8 | bidirectional | RTC_GPIO8 / GPIO8 with TOUCH8 and ADC1_CH7 functions, powered from VDD3P3_RTC_IO. |
| 14 | GPIO9 | bidirectional | RTC_GPIO9 / GPIO9 with TOUCH9, ADC1_CH8 and FSPIHD functions, powered from VDD3P3_RTC_IO. |
| 15 | GPIO10 | bidirectional | RTC_GPIO10 / GPIO10 with TOUCH10, ADC1_CH9, FSPICS0 and FSPIIO4 functions, powered from VDD3P3_RTC_IO. |
| 16 | GPIO11 | bidirectional | RTC_GPIO11 / GPIO11 with TOUCH11, ADC2_CH0, FSPID and FSPIIO5 functions, powered from VDD3P3_RTC_IO. |
| 17 | GPIO12 | bidirectional | RTC_GPIO12 / GPIO12 with TOUCH12, ADC2_CH1, FSPICLK and FSPIIO6 functions, powered from VDD3P3_RTC_IO. |
| 18 | GPIO13 | bidirectional | RTC_GPIO13 / GPIO13 with TOUCH13, ADC2_CH2, FSPIQ and FSPIIO7 functions, powered from VDD3P3_RTC_IO. |
| 19 | GPIO14 | bidirectional | RTC_GPIO14 / GPIO14 with TOUCH14, ADC2_CH3, FSPIWP and FSPIDQS functions, powered from VDD3P3_RTC_IO. |
| 20 | VDD3P3_RTC | power_in | Analog power supply for the RTC, 2.8 V to 3.6 V (3.3 V typical). |
| 21 | XTAL_32K_P | bidirectional | External 32 kHz crystal input, also RTC_GPIO15 / GPIO15 with ADC2_CH4, U0RTS and powered from VDD3P3_RTC_IO. |
| 22 | XTAL_32K_N | bidirectional | External 32 kHz crystal output, also RTC_GPIO16 / GPIO16 with ADC2_CH5, U0CTS and powered from VDD3P3_RTC_IO. |
| 23 | DAC_1 | bidirectional | 8-bit DAC channel 1 analog output, also RTC_GPIO17 / GPIO17 with ADC2_CH6 and U1TXD; DAC reference is VDD3P3_RTC_IO. |
| 24 | DAC_2 | bidirectional | 8-bit DAC channel 2 analog output, also RTC_GPIO18 / GPIO18 with ADC2_CH7, U1RXD and CLK_OUT3; DAC reference is VDD3P3_RTC_IO. |
| 25 | GPIO19 | bidirectional | RTC_GPIO19 / GPIO19 with ADC2_CH8, U1RTS, CLK_OUT2 and USB D- (full-speed USB OTG). |
| 26 | GPIO20 | bidirectional | RTC_GPIO20 / GPIO20 with ADC2_CH9, U1CTS, CLK_OUT1 and USB D+ (full-speed USB OTG). |
| 27 | VDD3P3_RTC_IO | power_in | RTC IO power input; this supply also feeds the CPU and RTC, rated 3.0 V to 3.6 V (3.3 V typical). |
| 28 | GPIO21 | bidirectional | RTC_GPIO21 / GPIO21 in the VDD3P3_RTC_IO domain. |
| 29 | SPICS1 | bidirectional | SPI chip select 1 (SPICS1 / GPIO26) in the VDD_SPI domain; on ESP32-S2FN4R2 and ESP32-S2R2 it connects to the in-package PSRAM CE#, and it is not recommended for other uses there. |
| 30 | VDD_SPI | power_out | Output of the internal 1.8 V LDO (fed from VDD3P3_RTC_IO) or a power input from VDD3P3_RTC_IO through R_SPI; the internal LDO supplies up to 40 mA at 1.8 V. |
| 31 | SPIHD | bidirectional | SPI HOLD signal (SPIHD / GPIO27) in the VDD_SPI domain; on flash-integrated variants it is connected to the in-package flash and not recommended for other uses. |
| 32 | SPIWP | bidirectional | SPI write-protect signal (SPIWP / GPIO28) in the VDD_SPI domain; on flash-integrated variants it is connected to the in-package flash and not recommended for other uses. |
| 33 | SPICS0 | bidirectional | SPI chip select 0 (SPICS0 / GPIO29) in the VDD_SPI domain; on flash-integrated variants it is connected to the in-package flash and not recommended for other uses. |
| 34 | SPICLK | bidirectional | SPI clock (SPICLK / GPIO30) in the VDD_SPI domain; on flash-integrated variants it is connected to the in-package flash and not recommended for other uses. |
| 35 | SPIQ | bidirectional | SPI data MISO/IO1 (SPIQ / GPIO31) in the VDD_SPI domain; on flash-integrated variants it is connected to the in-package flash and not recommended for other uses. |
| 36 | SPID | bidirectional | SPI data MOSI/IO0 (SPID / GPIO32) in the VDD_SPI domain; on flash-integrated variants it is connected to the in-package flash and not recommended for other uses. |
| 37 | GPIO33 | bidirectional | GPIO33 (SPIIO4, FSPIHD) in the VDD3P3_CPU domain by default, selectable to VDD_SPI by software. |
| 38 | GPIO34 | bidirectional | GPIO34 (SPIIO5, FSPICS0) in the VDD3P3_CPU domain by default, selectable to VDD_SPI by software. |
| 39 | GPIO35 | bidirectional | GPIO35 (SPIIO6, FSPID) in the VDD3P3_CPU domain by default, selectable to VDD_SPI by software. |
| 40 | GPIO36 | bidirectional | GPIO36 (SPIIO7, FSPICLK) in the VDD3P3_CPU domain by default, selectable to VDD_SPI by software. |
| 41 | GPIO37 | bidirectional | GPIO37 (SPIDQS, FSPIQ) in the VDD3P3_CPU domain by default, selectable to VDD_SPI by software. |
| 42 | GPIO38 | bidirectional | General-purpose I/O GPIO38 (FSPIWP) in the VDD3P3_CPU domain. |
| 43 | MTCK | bidirectional | JTAG debug clock MTCK, also GPIO39 and CLK_OUT3, in the VDD3P3_CPU domain. |
| 44 | MTDO | bidirectional | JTAG debug data output MTDO, also GPIO40 and CLK_OUT2, in the VDD3P3_CPU domain. |
| 45 | VDD3P3_CPU | power_in | CPU IO power input, 2.8 V to 3.6 V (3.3 V typical); must not exceed 3.3 V when writing eFuse. |
| 46 | MTDI | bidirectional | JTAG debug data input MTDI, also GPIO41 and CLK_OUT1, in the VDD3P3_CPU domain. |
| 47 | MTMS | bidirectional | JTAG debug mode select MTMS, also GPIO42, in the VDD3P3_CPU domain. |
| 48 | U0TXD | bidirectional | UART0 transmit U0TXD, also GPIO43 and CLK_OUT1; ROM boot log is printed here by default. |
| 49 | U0RXD | bidirectional | UART0 receive U0RXD, also GPIO44 and CLK_OUT2, in the VDD3P3_CPU domain. |
| 50 | GPIO45 | bidirectional | GPIO45 in the VDD3P3_CPU domain; strapping pin that selects the VDD_SPI voltage, with weak pull-down by default. |
| 51 | VDDA | power_in | Analog power supply, 2.8 V to 3.6 V (3.3 V typical). |
| 52 | XTAL_N | passive | External main crystal output; a 40 MHz main crystal is required for the chip to run. |
| 53 | XTAL_P | passive | External main crystal input; a 40 MHz main crystal is required for the chip to run. |
| 54 | VDDA | power_in | Analog power supply, 2.8 V to 3.6 V (3.3 V typical). |
| 55 | GPIO46 | input | Input-only GPIO46 with fixed pull-down and no output capability; strapping pin that controls ROM boot-log printing. |
| 56 | CHIP_PU | input | Chip enable: high enables the chip, low shuts it down; must not be left floating and is powered from VDD3P3_RTC_IO. |
| 57 | GND | power_in | Ground; this is the exposed thermal/ground pad of the QFN-56 package. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Espressif Systems |
| Package | QFN-56-EP(7x7) |
| Category | RF And Wireless |
| Pins | 57 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Power pin voltage (absolute maximum) | VDDA, VDD3P3, VDD3P3_RTC, VDD3P3_CPU, VDD_SPI, VDD3P3_RTC_IO | -0.3 | | 3.6 | V | | 35 |
| IO output total current (absolute maximum) | Ioutput | | | 1800 | mA | | 35 |
| Storage temperature | TSTORE | -40 | | 150 | °C | | 35 |
| Power pin voltage VDDA, VDD3P3, VDD3P3_RTC (recommended) | VDDA, VDD3P3, VDD3P3_RTC | 2.8 | 3.3 | 3.6 | V | 电源管脚电压 | 35 |
| Power pin voltage VDD3P3_CPU (recommended) | VDD3P3_CPU | 2.8 | 3.3 | 3.6 | V | 电源管脚电压 | 35 |
| External power supply current | IVDD | 0.5 | | | A | 单电源供电时 (note 4) | 35 |
| Junction temperature | TJ | -40 | | 125 | °C | | 35 |
| Input leakage current, high | IIH | | | 50 | nA | | 36 |
| Input leakage current, low | IIL | | | 50 | nA | | 36 |
| ADC differential nonlinearity (DNL) | DNL | -7 | | 7 | LSB | RTC 控制器；ADC 外接 100 nF 电容；输入为 DC 信号；常温 25 °C；Wi-Fi 关闭 | 36 |
| ADC integral nonlinearity (INL) | INL | -12 | | 12 | LSB | RTC 控制器；ADC 外接 100 nF 电容；输入为 DC 信号；常温 25 °C；Wi-Fi 关闭 | 36 |
| ESD HBM sensitivity | | -2000 | | 2000 | V | HBM, JS-001 | 38 |
| ESD CDM sensitivity | | -500 | | 500 | V | CDM, JS-002 | 38 |
| Latch-up current | | -200 | | 200 | mA | JESD78, 过电流 | 38 |
| Wi-Fi operating channel center frequency | | 2412 | | 2484 | MHz | 工作信道中心频率 | 39 |
| TX EVM limit | EVM | | -25 | -10 | dB | 802.11b, 1 Mbps, @19.5 dBm | 39 |
| TX EVM limit | EVM | | -28 | -5 | dB | 802.11g, 6 Mbps, @18 dBm | 39 |
| TX EVM limit | EVM | | -28 | -25 | dB | 802.11g, 54 Mbps, @18 dBm | 39 |
| TX EVM limit | EVM | | -26 | -5 | dB | 802.11n, HT20, MCS0, @18 dBm | 39 |
| TX EVM limit | EVM | | -30 | -27 | dB | 802.11n, HT20, MCS7, @17 dBm | 39 |
| CHIP_PU delay after supply power-up | t0 | 50 | | | µs | CHIP_PU 上电晚于 VDDA、VDD3P3、VDD3P3_RTC、VDD3P3_RTC_IO、VDD3P3_CPU 上电的延时 | 17 |
| CHIP_PU low time below VIL_nRST | t1 | 50 | | | µs | CHIP_PU 电平低于 VIL_nRST 的时间 | 17 |
| Strapping pin setup time | tSU | 0 | | | ms | 拉高 CHIP_PU 激活芯片前电源轨稳定所需时间 | 18 |
| Strapping pin hold time | tH | 3 | | | ms | CHIP_PU 已拉高后 strapping 管脚可读取的时间 | 18 |
## CAD (KiCad official)
- Symbol: `ESP32-S2`
- Footprint: `Package_DFN_QFN:QFN-56-1EP_7x7mm_P0.4mm_EP4x4mm`
- 3D model: QFN-56-EP(7x7) (KiCad packages3D, STEP)
- 3D model files: `esp32-s2-etched.step` / `esp32-s2-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `esp32-s2.step` / `esp32-s2.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Espressif Systems datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588893190203695104) (52 pp, sha256 `4a9a84db4a708c85`, retrieved 2026-10-19, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/esp32-s2-datasheet.pdf)