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ESP32-P4NRW32X
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Espressif Systems Integrated Circuits (ICs), 104-VFQFN Exposed Pad. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D. Chip revision v3.x, the newer revision of ESP32-P4NRW32 (v1.x).
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ESP32-P4NRW32X
Espressif Systems · Integrated Circuits (ICs) · 104-VFQFN Exposed Pad
ESP32-P4NRW32X from Espressif Systems, in a 104-VFQFN Exposed Pad. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Silicon revision
ESP32-P4NRW32X is chip revision v3.x, the newer revision. ESP32-P4NRW32 is the older revision, v1.x, in the same 104-pin 10 x 10 mm QFN. Espressif documents them separately: v3.x in the ESP32-P4 Series datasheet (v0.7 covers v3.x only), v1.x in the ESP32-P4 chip revision v1.3 datasheet. Two differences matter for a board, both from Espressif's own KiCad symbols (ESP32-P4 and ESP32-P4X): pin 54 is NC on v1.x but VDD_HP_1 (a supply pin) on v3.x, so a board drawn for v1.x needs pin 54 wired to the supply before it takes a v3.x part; and the ADC pins move. On v1.x GPIO0 to GPIO23 and GPIO49 to GPIO54 are marked ADC; on v3.x only GPIO16 to GPIO23 (ADC1 channels 0 to 7) and GPIO49 to GPIO54 (ADC2 channels 0 to 5) are, so a v1.x design reading an analog input on GPIO0 to GPIO15 needs it moved. Check both against the datasheets before swapping one for the other.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GPIO1 | bidirectional | IO pin powered by VDD_LP/VDD_BAT with IO MUX, LP IO MUX and analog (XTAL_32K_P) functions; default drive strength 20 mA. |
| 2 | GPIO2 | bidirectional | IO pin powered by VDD_LP/VDD_BAT with input enabled and weak pull-up at reset; F0 is JTAG MTCK and it also serves as TOUCH_CHANNEL1; default drive strength 20 mA. |
| 3 | GPIO3 | bidirectional | IO pin powered by VDD_LP/VDD_BAT with input enabled at reset; F0 is JTAG MTDI and it also serves as TOUCH_CHANNEL2; default drive strength 20 mA. |
| 4 | GPIO4 | bidirectional | IO pin powered by VDD_LP with input enabled at reset; F0 is JTAG MTMS and it also serves as TOUCH_CHANNEL3; default drive strength 20 mA. |
| 5 | GPIO5 | bidirectional | IO pin powered by VDD_LP; F0 is JTAG MTDO and it also serves as TOUCH_CHANNEL4; default drive strength 20 mA. |
| 6 | GPIO6 | bidirectional | IO pin powered by VDD_LP; F2 is SPI2_HOLD_PAD and it also serves as TOUCH_CHANNEL5; default drive strength 20 mA. |
| 7 | GPIO7 | bidirectional | IO pin powered by VDD_LP; F2 is SPI2_CS_PAD and it also serves as TOUCH_CHANNEL6; default drive strength 20 mA. |
| 8 | GPIO8 | bidirectional | IO pin powered by VDD_LP; F1 is UART0_RTS, F2 is SPI2_D_PAD, and it also serves as TOUCH_CHANNEL7; default drive strength 20 mA. |
| 9 | VDD_LP | power_in | Power input for the LP power domain that supplies LP IO pins; recommended input voltage 3.0-3.6 V (typ. 3.3 V). |
| 10 | GPIO9 | bidirectional | IO pin powered by VDD_LP; F1 is UART0_CTS, F2 is SPI2_CK_PAD, and it also serves as TOUCH_CHANNEL8; default drive strength 20 mA. |
| 11 | GPIO10 | bidirectional | IO pin powered by VDD_LP; F1 is UART1_TXD, F2 is SPI2_Q_PAD, and it also serves as TOUCH_CHANNEL9; default drive strength 20 mA. |
| 12 | GPIO11 | bidirectional | IO pin powered by VDD_LP; F1 is UART1_RXD, F2 is SPI2_WP_PAD, and it also serves as TOUCH_CHANNEL10; default drive strength 20 mA. |
| 13 | GPIO12 | bidirectional | IO pin powered by VDD_LP; F1 is UART1_RTS and it also serves as TOUCH_CHANNEL11; default drive strength 20 mA. |
| 14 | GPIO13 | bidirectional | IO pin powered by VDD_LP; F1 is UART1_CTS and it also serves as TOUCH_CHANNEL12; default drive strength 20 mA. |
| 15 | GPIO14 | bidirectional | IO pin powered by VDD_LP; LP IO MUX function LP_UART_TXD and it also serves as TOUCH_CHANNEL13; default drive strength 20 mA. |
| 16 | GPIO15 | bidirectional | IO pin powered by VDD_LP; LP IO MUX function LP_UART_RXD and it also serves as TOUCH_CHANNEL14; default drive strength 20 mA. |
| 17 | GPIO16 | bidirectional | IO pin powered by VDD_IO_0 with analog function ADC1_CHANNEL0; default drive strength 20 mA. |
| 18 | GPIO17 | bidirectional | IO pin powered by VDD_IO_0 with analog function ADC1_CHANNEL1; default drive strength 20 mA. |
| 19 | GPIO18 | bidirectional | IO pin powered by VDD_IO_0 with analog function ADC1_CHANNEL2; default drive strength 20 mA. |
| 20 | GPIO19 | bidirectional | IO pin powered by VDD_IO_0 with analog function ADC1_CHANNEL3; default drive strength 20 mA. |
| 21 | VDD_IO_0 | power_in | Digital power domain input for HP IO pins GPIO16-GPIO23; recommended input voltage 1.65-3.6 V (typ. 1.8 V). |
| 22 | GPIO20 | bidirectional | IO pin powered by VDD_IO_0 with analog function ADC1_CHANNEL4; default drive strength 20 mA. |
| 23 | GPIO21 | bidirectional | IO pin powered by VDD_IO_0 with analog function ADC1_CHANNEL5; default drive strength 20 mA. |
| 24 | GPIO22 | bidirectional | IO pin powered by VDD_IO_0 with analog function ADC1_CHANNEL6; default drive strength 20 mA. |
| 25 | GPIO23 | bidirectional | IO pin powered by VDD_IO_0 with analog function ADC1_CHANNEL7; F2 is REF_50M_CLK_PAD output; default drive strength 20 mA. |
| 26 | VDD_HP_0 | power_in | Digital power domain input for the HP core, with absolute maximum allowed input voltage of 0-1.3 V. |
| 27 | FLASH_CS | output | Dedicated off-package flash chip-select output (CS#), powered by VDD_FLASHIO. |
| 28 | FLASH_Q | bidirectional | Dedicated off-package flash data output (DO) pin, powered by VDD_FLASHIO. |
| 29 | FLASH_WP | bidirectional | Dedicated off-package flash write-protect (WP#) pin, powered by VDD_FLASHIO. |
| 30 | VDD_FLASHIO | power_in | Power input for flash IO, to be adjusted to the flash model (examples in the datasheet use 3.3 V flash); recommended range 1.65-3.6 V. |
| 31 | FLASH_HOLD | bidirectional | Dedicated off-package flash hold (HOLD#) pin, powered by VDD_FLASHIO. |
| 32 | FLASH_CK | output | Dedicated off-package flash clock output (CLK), powered by VDD_FLASHIO. |
| 33 | FLASH_D | bidirectional | Dedicated off-package flash data input (DI) pin, powered by VDD_FLASHIO. |
| 34 | DSI_REXT | bidirectional | MIPI DSI PHY connection for the 4.02 kΩ external reference resistor, powered by VDD_MIPI_DPHY. |
| 35 | DSI_DATAP1 | bidirectional | MIPI DSI PHY positive data channel 1 (2-lane, 1.5 Gbps per lane), powered by VDD_MIPI_DPHY. |
| 36 | DSI_DATAN1 | bidirectional | MIPI DSI PHY negative data channel 1, powered by VDD_MIPI_DPHY. |
| 37 | DSI_CLKN | bidirectional | MIPI DSI PHY negative clock channel, powered by VDD_MIPI_DPHY. |
| 38 | DSI_CLKP | bidirectional | MIPI DSI PHY positive clock channel, powered by VDD_MIPI_DPHY. |
| 39 | DSI_DATAP0 | bidirectional | MIPI DSI PHY positive data channel 0, powered by VDD_MIPI_DPHY. |
| 40 | DSI_DATAN0 | bidirectional | MIPI DSI PHY negative data channel 0, powered by VDD_MIPI_DPHY. |
| 41 | VDD_MIPI_DPHY | power_in | Power input for the MIPI PHY domain, with absolute maximum allowed input voltage of 0-2.75 V. |
| 42 | CSI_DATAN0 | bidirectional | MIPI CSI PHY negative data channel 0, powered by VDD_MIPI_DPHY. |
| 43 | CSI_DATAP0 | bidirectional | MIPI CSI PHY positive data channel 0, powered by VDD_MIPI_DPHY. |
| 44 | CSI_CLKP | bidirectional | MIPI CSI PHY positive clock channel, powered by VDD_MIPI_DPHY. |
| 45 | CSI_CLKN | bidirectional | MIPI CSI PHY negative clock channel, powered by VDD_MIPI_DPHY. |
| 46 | CSI_DATAN1 | bidirectional | MIPI CSI PHY negative data channel 1, powered by VDD_MIPI_DPHY. |
| 47 | CSI_DATAP1 | bidirectional | MIPI CSI PHY positive data channel 1, powered by VDD_MIPI_DPHY. |
| 48 | CSI_REXT | bidirectional | MIPI CSI PHY connection for the 4.02 kΩ external reference resistor, powered by VDD_MIPI_DPHY. |
| 49 | USB_DM | bidirectional | USB 2.0 High-Speed OTG PHY D- (USB_D-) dedicated pin. |
| 50 | USB_DP | bidirectional | USB 2.0 High-Speed OTG PHY D+ (USB_D+) dedicated pin. |
| 51 | VDD_USBPHY | power_in | Power input for the USB PHY, with absolute maximum allowed input voltage of -0.66-3.96 V. |
| 52 | GPIO24 | bidirectional | IO pin powered by VDD_IO_4; by default it is the USB1P1_N0 USB Serial/JTAG D- signal, and its default drive strength is 40 mA. |
| 53 | GPIO25 | bidirectional | IO pin powered by VDD_IO_4; by default it is the USB1P1_P0 USB Serial/JTAG D+ signal with USB pull-up enabled at reset, and its default drive strength is 40 mA. |
| 54 | VDD_HP_1 | power_in | Digital power domain input for the HP core, with absolute maximum allowed input voltage of 0-1.3 V. |
| 55 | GPIO26 | bidirectional | IO pin powered by VDD_IO_4 with USB1P1_N1 (USB 2.0 Full-Speed OTG D-) analog function; default drive strength 20 mA. |
| 56 | GPIO27 | bidirectional | IO pin powered by VDD_IO_4 with USB1P1_P1 (USB 2.0 Full-Speed OTG D+) analog function; default drive strength 20 mA. |
| 57 | GPIO28 | bidirectional | IO pin powered by VDD_IO_4; F2 is SPI2_CS_PAD and F3 is GMAC_PHY_RXDV_PAD; default drive strength 20 mA. |
| 58 | GPIO29 | bidirectional | IO pin powered by VDD_IO_4; F2 is SPI2_D_PAD and F3 is GMAC_PHY_RXD0_PAD; default drive strength 20 mA. |
| 59 | VDD_PSRAM_0 | power_in | Power input for PSRAM IO; recommended input voltage 1.65-1.95 V (typ. 1.8 V). |
| 60 | GPIO30 | bidirectional | IO pin powered by VDD_IO_4; F2 is SPI2_CK_PAD and F3 is GMAC_PHY_RXD1_PAD; default drive strength 20 mA. |
| 61 | GPIO31 | bidirectional | IO pin powered by VDD_IO_4; F2 is SPI2_Q_PAD and F3 is GMAC_PHY_RXER_PAD; default drive strength 20 mA. |
| 62 | VDD_IO_4 | power_in | Digital power domain input for HP IO pins GPIO24-GPIO38 group; recommended input voltage 1.65-3.6 V (typ. 1.8 V). |
| 63 | GPIO32 | bidirectional | IO pin powered by VDD_IO_4 with input enabled at reset; F2 is SPI2_HOLD_PAD, F3 is GMAC_RMII_CLK_PAD, and it is a dedicated I3C master SCL pin with configurable pull-up. |
| 64 | GPIO33 | bidirectional | IO pin powered by VDD_IO_4 with input enabled at reset; F2 is SPI2_WP_PAD, F3 is GMAC_PHY_TXEN_PAD, and it is a dedicated I3C master SDA pin with configurable pull-up. |
| 65 | GPIO34 | bidirectional | Strapping IO pin powered by VDD_IO_4 with input enabled at reset (JTAG signal source control, floating by default); F2 is SPI2_IO4_PAD and F3 is GMAC_PHY_TXD0_PAD. |
| 66 | GPIO35 | bidirectional | Strapping IO pin powered by VDD_IO_4 with input enabled and weak pull-up at reset (chip boot mode control, default bit value 1); F2 is SPI2_IO5_PAD and F3 is GMAC_PHY_TXD1_PAD. |
| 67 | VDD_PSRAM_1 | power_in | Power input for PSRAM IO; recommended input voltage 1.65-1.95 V (typ. 1.8 V). |
| 68 | GPIO36 | bidirectional | Strapping IO pin powered by VDD_IO_4 with input enabled at reset (ROM message printing control, floating by default); F2 is SPI2_IO6_PAD and F3 is GMAC_PHY_TXER_PAD. |
| 69 | GPIO37 | bidirectional | Strapping IO pin powered by VDD_IO_4 (chip boot mode control, floating by default); F0 is UART0_TXD and F2 is SPI2_IO7_PAD. |
| 70 | GPIO38 | bidirectional | Strapping IO pin powered by VDD_IO_4 with input enabled at reset (chip boot mode control, floating by default); F0 is UART0_RXD and F2 is SPI2_DQS_PAD. |
| 71 | VDDO_FLASH | power_out | Regulated output supplying the off-package flash, rated up to 50 mA at maximum. |
| 72 | VDDO_PSRAM | power_out | Regulated output supplying in-package and off-package PSRAM, rated up to 50 mA at maximum. |
| 73 | VDDO_3 | power_out | Regulated power output rated up to 50 mA at maximum. |
| 74 | VDDO_4 | power_out | Regulated power output rated up to 50 mA at maximum. |
| 75 | VDD_LDO | power_in | Analog power domain input providing power for the LDOs; recommended input voltage 3.0-3.6 V (typ. 3.3 V). |
| 76 | VDD_HP_2 | power_in | Digital power domain input for the HP core, with absolute maximum allowed input voltage of 0-1.3 V. |
| 77 | VDD_DCDCC | power_in | Analog power domain input providing power for DC/DC control; recommended input voltage 3.0-3.6 V (typ. 3.3 V). |
| 78 | FB_DCDC | passive | Feedback pin of the power supply for the external DC/DC; it regulates VDD_HP_0/1/2/3 together with external feedback resistors. |
| 79 | EN_DCDC | output | Enable output for the external DC/DC converter. |
| 80 | GPIO39 | bidirectional | IO pin powered by VDD_IO_5; F0 is SD1_CDATA0 and F2 is REF_50M_CLK_PAD; default drive strength 20 mA. |
| 81 | GPIO40 | bidirectional | IO pin powered by VDD_IO_5; F0 is SD1_CDATA1 and F2 is GMAC_PHY_TXEN_PAD; default drive strength 20 mA. |
| 82 | GPIO41 | bidirectional | IO pin powered by VDD_IO_5; F0 is SD1_CDATA2 and F2 is GMAC_PHY_TXD0_PAD; default drive strength 20 mA. |
| 83 | GPIO42 | bidirectional | IO pin powered by VDD_IO_5; F0 is SD1_CDATA3 and F2 is GMAC_PHY_TXD1_PAD; default drive strength 20 mA. |
| 84 | GPIO43 | bidirectional | IO pin powered by VDD_IO_5; F0 is SD1_CCLK and F2 is GMAC_PHY_TXER_PAD; default drive strength 20 mA. |
| 85 | VDD_IO_5 | power_in | Digital power domain input for HP IO pins GPIO39-GPIO48; recommended input voltage 1.65-3.6 V (typ. 1.8 V). |
| 86 | GPIO44 | bidirectional | IO pin powered by VDD_IO_5; F0 is SD1_CCMD and F2 is GMAC_RMII_CLK_PAD; default drive strength 20 mA. |
| 87 | GPIO45 | bidirectional | IO pin powered by VDD_IO_5; F0 is SD1_CDATA4 and F2 is GMAC_PHY_RXDV_PAD; default drive strength 20 mA. |
| 88 | GPIO46 | bidirectional | IO pin powered by VDD_IO_5; F0 is SD1_CDATA5 and F2 is GMAC_PHY_RXD0_PAD; default drive strength 20 mA. |
| 89 | GPIO47 | bidirectional | IO pin powered by VDD_IO_5; F0 is SD1_CDATA6 and F2 is GMAC_PHY_RXD1_PAD; default drive strength 20 mA. |
| 90 | GPIO48 | bidirectional | IO pin powered by VDD_IO_5; F0 is SD1_CDATA7 and F2 is GMAC_PHY_RXER_PAD; default drive strength 20 mA. |
| 91 | VDD_HP_3 | power_in | Digital power domain input for the HP core, with absolute maximum allowed input voltage of 0-1.3 V. |
| 92 | GPIO49 | bidirectional | IO pin powered by VDD_IO_6 with analog function ADC2_CHANNEL0; F2 is GMAC_PHY_TXEN_PAD; default drive strength 20 mA. |
| 93 | GPIO50 | bidirectional | IO pin powered by VDD_IO_6 with analog function ADC2_CHANNEL1; F2 is GMAC_RMII_CLK_PAD; default drive strength 20 mA. |
| 94 | GPIO51 | bidirectional | IO pin powered by VDD_IO_6 with analog functions ADC2_CHANNEL2 and ANA_COMP0; F2 is GMAC_PHY_RXDV_PAD; default drive strength 20 mA. |
| 95 | GPIO52 | bidirectional | IO pin powered by VDD_IO_6 with analog functions ADC2_CHANNEL3 and ANA_COMP0; F2 is GMAC_PHY_RXD0_PAD; default drive strength 20 mA. |
| 96 | VDD_IO_6 | power_in | Digital power domain input for HP IO pins GPIO49-GPIO54; recommended input voltage 1.65-3.6 V (typ. 1.8 V). |
| 97 | GPIO53 | bidirectional | IO pin powered by VDD_IO_6 with analog functions ADC2_CHANNEL4 and ANA_COMP1; F2 is GMAC_PHY_RXD1_PAD; default drive strength 20 mA. |
| 98 | GPIO54 | bidirectional | IO pin powered by VDD_IO_6 with analog functions ADC2_CHANNEL5 and ANA_COMP1; F2 is GMAC_PHY_RXER_PAD; default drive strength 20 mA. |
| 99 | XTAL_N | passive | Negative external clock input/output connected to the chip's crystal or oscillator. |
| 100 | XTAL_P | passive | Positive external clock input/output connected to the chip's crystal or oscillator (differential clock with XTAL_N). |
| 101 | VDD_ANA | power_in | Analog power domain input; recommended input voltage 3.0-3.6 V (typ. 3.3 V). |
| 102 | VDD_BAT | power_in | Analog power domain input that can optionally connect to an external battery; recommended input voltage 2.5-3.6 V (typ. 3.3 V). |
| 103 | CHIP_PU | input | Chip enable: High enables the chip (powered up), Low disables it (powered down); it must not be left floating. |
| 104 | GPIO0 | bidirectional | IO pin powered by VDD_LP/VDD_BAT with analog function XTAL_32K_N and LP_GPIO0; default drive strength 20 mA. |
| 105 | GND | power_in | External ground connection (exposed pad on the QFN104 package). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Espressif Systems |
| Package | 104-VFQFN Exposed Pad |
| Category | Integrated Circuits (ICs) |
| Pins | 105 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Allowed input voltage (VDD_LDO, VDD_DCDCC, VDD_ANA, VDD_BAT, VDD_LP) | -0.3 | 3.6 | V | 88 | |||
| Allowed input voltage (VDD_IO_0, VDD_FLASHIO, VDD_IO_4, VDD_IO_5, VDD_IO_6) | -0.3 | 3.6 | V | 88 | |||
| Allowed input voltage (VDD_PSRAM_0, VDD_PSRAM_1) | 1.62 | 1.98 | V | 88 | |||
| Allowed input voltage (VDD_HP_0, VDD_HP_1, VDD_HP_2, VDD_HP_3) | 0 | 1.3 | V | 88 | |||
| Allowed input voltage (VDD_MIPI_DPHY) | 0 | 2.75 | V | 88 | |||
| Allowed input voltage (VDD_USBPHY) | -0.66 | 3.96 | V | 88 | |||
| Cumulative IO output current | Ioutput | 1500 | mA | 88 | |||
| Storage temperature | TSTORE | -40 | 150 | °C | 88 | ||
| Recommended input voltage (VDD_LDO, VDD_DCDCC, VDD_ANA, VDD_LP) | 3 | 3.3 | 3.6 | V | 88 | ||
| Recommended input voltage (VDD_BAT) | 2.5 | 3.3 | 3.6 | V | 88 | ||
| Recommended input voltage (VDD_IO_0, VDD_FLASHIO, VDD_IO_4, VDD_IO_5, VDD_IO_6) | 1.65 | 1.8 | 3.6 | V | 88 | ||
| Recommended input voltage (VDD_PSRAM_0, VDD_PSRAM_1) | 1.65 | 1.8 | 1.95 | V | 88 | ||
| Recommended input voltage (VDD_HP_0, VDD_HP_1, VDD_HP_2, VDD_HP_3) | 0.99 | 1.1 | 1.3 | V | 89 | ||
| Recommended input voltage (VDD_MIPI_DPHY) | 2.25 | 2.5 | 2.75 | V | 89 | ||
| Recommended input voltage (VDD_USBPHY) | 2.97 | 3.3 | 3.63 | V | 89 | ||
| Current supplied to core | IVDD | 0.5 | A | 89 | |||
| Ambient temperature | TA | -40 | 85 | °C | 89 | ||
| Low-level input voltage | VIL | -0.3 | V | 89 | |||
| High-level input current | IIH | 50 | nA | 89 | |||
| Low-level input current | IIL | 50 | nA | 89 | |||
| Chip reset voltage | VIL_nRST | -0.3 | V | CHIP_PU voltage is within the specified range | 90 | ||
| Differential nonlinearity (DNL) | DNL | -1 | 3 | LSB | 90 | ||
| Integral nonlinearity (INL) | INL | -5 | 3 | LSB | 90 | ||
| ADC sampling rate | 100 | kSPS | 90 | ||||
| Total error ATTEN0 | -12 | 12 | mV | effective measurement range of 0-1000 | 90 | ||
| Total error ATTEN1 | -12 | 12 | mV | effective measurement range of 0-1300 | 90 | ||
| Total error ATTEN2 | -12 | 12 | mV | effective measurement range of 0-1900 | 90 | ||
| Total error ATTEN3 | -15 | 15 | mV | effective measurement range of 0-3300 | 90 | ||
| Power supply voltage (1.8 V PSRAM) | VCC | 1.62 | 1.8 | 1.98 | V | Power supply voltage (1.8 V) | 92 |
| Power supply voltage (3.3 V PSRAM) | VCC | 2.7 | 3.3 | 3.6 | V | Power supply voltage (3.3 V) | 92 |
| Maximum clock frequency (PSRAM) | FC | 80 | MHz | Maximum clock frequency | 92 |
CAD (KiCad official)
- Symbol:
ESP32-P4NRW32X - Footprint:
PCM_Espressif:ESP32-P4 - 3D model: 104-VFQFN Exposed Pad, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.85 mm nominal QFN height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files:
esp32-p4nrw32x-etched.step/esp32-p4nrw32x-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);esp32-p4nrw32x.step/esp32-p4nrw32x.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Espressif Systems datasheet (102 pp, sha256
fb4f3e91cc2ac519, retrieved 2026-10-28, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# ESP32-P4NRW32X
**Espressif Systems** · Integrated Circuits (ICs) · 104-VFQFN Exposed Pad
ESP32-P4NRW32X from Espressif Systems, in a 104-VFQFN Exposed Pad. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Silicon revision
ESP32-P4NRW32X is chip revision **v3.x**, the **newer** revision. [ESP32-P4NRW32](https://wiki.adom.inc/adom/esp32-p4nrw32) is the older revision, v1.x, in the same 104-pin 10 x 10 mm QFN. Espressif documents them separately: v3.x in the ESP32-P4 Series datasheet (v0.7 covers v3.x only), v1.x in the ESP32-P4 chip revision v1.3 datasheet. Two differences matter for a board, both from Espressif's own KiCad symbols (ESP32-P4 and ESP32-P4X): pin 54 is NC on v1.x but VDD_HP_1 (a supply pin) on v3.x, so a board drawn for v1.x needs pin 54 wired to the supply before it takes a v3.x part; and the ADC pins move. On v1.x GPIO0 to GPIO23 and GPIO49 to GPIO54 are marked ADC; on v3.x only GPIO16 to GPIO23 (ADC1 channels 0 to 7) and GPIO49 to GPIO54 (ADC2 channels 0 to 5) are, so a v1.x design reading an analog input on GPIO0 to GPIO15 needs it moved. Check both against the datasheets before swapping one for the other.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GPIO1 | bidirectional | IO pin powered by VDD_LP/VDD_BAT with IO MUX, LP IO MUX and analog (XTAL_32K_P) functions; default drive strength 20 mA. |
| 2 | GPIO2 | bidirectional | IO pin powered by VDD_LP/VDD_BAT with input enabled and weak pull-up at reset; F0 is JTAG MTCK and it also serves as TOUCH_CHANNEL1; default drive strength 20 mA. |
| 3 | GPIO3 | bidirectional | IO pin powered by VDD_LP/VDD_BAT with input enabled at reset; F0 is JTAG MTDI and it also serves as TOUCH_CHANNEL2; default drive strength 20 mA. |
| 4 | GPIO4 | bidirectional | IO pin powered by VDD_LP with input enabled at reset; F0 is JTAG MTMS and it also serves as TOUCH_CHANNEL3; default drive strength 20 mA. |
| 5 | GPIO5 | bidirectional | IO pin powered by VDD_LP; F0 is JTAG MTDO and it also serves as TOUCH_CHANNEL4; default drive strength 20 mA. |
| 6 | GPIO6 | bidirectional | IO pin powered by VDD_LP; F2 is SPI2_HOLD_PAD and it also serves as TOUCH_CHANNEL5; default drive strength 20 mA. |
| 7 | GPIO7 | bidirectional | IO pin powered by VDD_LP; F2 is SPI2_CS_PAD and it also serves as TOUCH_CHANNEL6; default drive strength 20 mA. |
| 8 | GPIO8 | bidirectional | IO pin powered by VDD_LP; F1 is UART0_RTS, F2 is SPI2_D_PAD, and it also serves as TOUCH_CHANNEL7; default drive strength 20 mA. |
| 9 | VDD_LP | power_in | Power input for the LP power domain that supplies LP IO pins; recommended input voltage 3.0-3.6 V (typ. 3.3 V). |
| 10 | GPIO9 | bidirectional | IO pin powered by VDD_LP; F1 is UART0_CTS, F2 is SPI2_CK_PAD, and it also serves as TOUCH_CHANNEL8; default drive strength 20 mA. |
| 11 | GPIO10 | bidirectional | IO pin powered by VDD_LP; F1 is UART1_TXD, F2 is SPI2_Q_PAD, and it also serves as TOUCH_CHANNEL9; default drive strength 20 mA. |
| 12 | GPIO11 | bidirectional | IO pin powered by VDD_LP; F1 is UART1_RXD, F2 is SPI2_WP_PAD, and it also serves as TOUCH_CHANNEL10; default drive strength 20 mA. |
| 13 | GPIO12 | bidirectional | IO pin powered by VDD_LP; F1 is UART1_RTS and it also serves as TOUCH_CHANNEL11; default drive strength 20 mA. |
| 14 | GPIO13 | bidirectional | IO pin powered by VDD_LP; F1 is UART1_CTS and it also serves as TOUCH_CHANNEL12; default drive strength 20 mA. |
| 15 | GPIO14 | bidirectional | IO pin powered by VDD_LP; LP IO MUX function LP_UART_TXD and it also serves as TOUCH_CHANNEL13; default drive strength 20 mA. |
| 16 | GPIO15 | bidirectional | IO pin powered by VDD_LP; LP IO MUX function LP_UART_RXD and it also serves as TOUCH_CHANNEL14; default drive strength 20 mA. |
| 17 | GPIO16 | bidirectional | IO pin powered by VDD_IO_0 with analog function ADC1_CHANNEL0; default drive strength 20 mA. |
| 18 | GPIO17 | bidirectional | IO pin powered by VDD_IO_0 with analog function ADC1_CHANNEL1; default drive strength 20 mA. |
| 19 | GPIO18 | bidirectional | IO pin powered by VDD_IO_0 with analog function ADC1_CHANNEL2; default drive strength 20 mA. |
| 20 | GPIO19 | bidirectional | IO pin powered by VDD_IO_0 with analog function ADC1_CHANNEL3; default drive strength 20 mA. |
| 21 | VDD_IO_0 | power_in | Digital power domain input for HP IO pins GPIO16-GPIO23; recommended input voltage 1.65-3.6 V (typ. 1.8 V). |
| 22 | GPIO20 | bidirectional | IO pin powered by VDD_IO_0 with analog function ADC1_CHANNEL4; default drive strength 20 mA. |
| 23 | GPIO21 | bidirectional | IO pin powered by VDD_IO_0 with analog function ADC1_CHANNEL5; default drive strength 20 mA. |
| 24 | GPIO22 | bidirectional | IO pin powered by VDD_IO_0 with analog function ADC1_CHANNEL6; default drive strength 20 mA. |
| 25 | GPIO23 | bidirectional | IO pin powered by VDD_IO_0 with analog function ADC1_CHANNEL7; F2 is REF_50M_CLK_PAD output; default drive strength 20 mA. |
| 26 | VDD_HP_0 | power_in | Digital power domain input for the HP core, with absolute maximum allowed input voltage of 0-1.3 V. |
| 27 | FLASH_CS | output | Dedicated off-package flash chip-select output (CS#), powered by VDD_FLASHIO. |
| 28 | FLASH_Q | bidirectional | Dedicated off-package flash data output (DO) pin, powered by VDD_FLASHIO. |
| 29 | FLASH_WP | bidirectional | Dedicated off-package flash write-protect (WP#) pin, powered by VDD_FLASHIO. |
| 30 | VDD_FLASHIO | power_in | Power input for flash IO, to be adjusted to the flash model (examples in the datasheet use 3.3 V flash); recommended range 1.65-3.6 V. |
| 31 | FLASH_HOLD | bidirectional | Dedicated off-package flash hold (HOLD#) pin, powered by VDD_FLASHIO. |
| 32 | FLASH_CK | output | Dedicated off-package flash clock output (CLK), powered by VDD_FLASHIO. |
| 33 | FLASH_D | bidirectional | Dedicated off-package flash data input (DI) pin, powered by VDD_FLASHIO. |
| 34 | DSI_REXT | bidirectional | MIPI DSI PHY connection for the 4.02 kΩ external reference resistor, powered by VDD_MIPI_DPHY. |
| 35 | DSI_DATAP1 | bidirectional | MIPI DSI PHY positive data channel 1 (2-lane, 1.5 Gbps per lane), powered by VDD_MIPI_DPHY. |
| 36 | DSI_DATAN1 | bidirectional | MIPI DSI PHY negative data channel 1, powered by VDD_MIPI_DPHY. |
| 37 | DSI_CLKN | bidirectional | MIPI DSI PHY negative clock channel, powered by VDD_MIPI_DPHY. |
| 38 | DSI_CLKP | bidirectional | MIPI DSI PHY positive clock channel, powered by VDD_MIPI_DPHY. |
| 39 | DSI_DATAP0 | bidirectional | MIPI DSI PHY positive data channel 0, powered by VDD_MIPI_DPHY. |
| 40 | DSI_DATAN0 | bidirectional | MIPI DSI PHY negative data channel 0, powered by VDD_MIPI_DPHY. |
| 41 | VDD_MIPI_DPHY | power_in | Power input for the MIPI PHY domain, with absolute maximum allowed input voltage of 0-2.75 V. |
| 42 | CSI_DATAN0 | bidirectional | MIPI CSI PHY negative data channel 0, powered by VDD_MIPI_DPHY. |
| 43 | CSI_DATAP0 | bidirectional | MIPI CSI PHY positive data channel 0, powered by VDD_MIPI_DPHY. |
| 44 | CSI_CLKP | bidirectional | MIPI CSI PHY positive clock channel, powered by VDD_MIPI_DPHY. |
| 45 | CSI_CLKN | bidirectional | MIPI CSI PHY negative clock channel, powered by VDD_MIPI_DPHY. |
| 46 | CSI_DATAN1 | bidirectional | MIPI CSI PHY negative data channel 1, powered by VDD_MIPI_DPHY. |
| 47 | CSI_DATAP1 | bidirectional | MIPI CSI PHY positive data channel 1, powered by VDD_MIPI_DPHY. |
| 48 | CSI_REXT | bidirectional | MIPI CSI PHY connection for the 4.02 kΩ external reference resistor, powered by VDD_MIPI_DPHY. |
| 49 | USB_DM | bidirectional | USB 2.0 High-Speed OTG PHY D- (USB_D-) dedicated pin. |
| 50 | USB_DP | bidirectional | USB 2.0 High-Speed OTG PHY D+ (USB_D+) dedicated pin. |
| 51 | VDD_USBPHY | power_in | Power input for the USB PHY, with absolute maximum allowed input voltage of -0.66-3.96 V. |
| 52 | GPIO24 | bidirectional | IO pin powered by VDD_IO_4; by default it is the USB1P1_N0 USB Serial/JTAG D- signal, and its default drive strength is 40 mA. |
| 53 | GPIO25 | bidirectional | IO pin powered by VDD_IO_4; by default it is the USB1P1_P0 USB Serial/JTAG D+ signal with USB pull-up enabled at reset, and its default drive strength is 40 mA. |
| 54 | VDD_HP_1 | power_in | Digital power domain input for the HP core, with absolute maximum allowed input voltage of 0-1.3 V. |
| 55 | GPIO26 | bidirectional | IO pin powered by VDD_IO_4 with USB1P1_N1 (USB 2.0 Full-Speed OTG D-) analog function; default drive strength 20 mA. |
| 56 | GPIO27 | bidirectional | IO pin powered by VDD_IO_4 with USB1P1_P1 (USB 2.0 Full-Speed OTG D+) analog function; default drive strength 20 mA. |
| 57 | GPIO28 | bidirectional | IO pin powered by VDD_IO_4; F2 is SPI2_CS_PAD and F3 is GMAC_PHY_RXDV_PAD; default drive strength 20 mA. |
| 58 | GPIO29 | bidirectional | IO pin powered by VDD_IO_4; F2 is SPI2_D_PAD and F3 is GMAC_PHY_RXD0_PAD; default drive strength 20 mA. |
| 59 | VDD_PSRAM_0 | power_in | Power input for PSRAM IO; recommended input voltage 1.65-1.95 V (typ. 1.8 V). |
| 60 | GPIO30 | bidirectional | IO pin powered by VDD_IO_4; F2 is SPI2_CK_PAD and F3 is GMAC_PHY_RXD1_PAD; default drive strength 20 mA. |
| 61 | GPIO31 | bidirectional | IO pin powered by VDD_IO_4; F2 is SPI2_Q_PAD and F3 is GMAC_PHY_RXER_PAD; default drive strength 20 mA. |
| 62 | VDD_IO_4 | power_in | Digital power domain input for HP IO pins GPIO24-GPIO38 group; recommended input voltage 1.65-3.6 V (typ. 1.8 V). |
| 63 | GPIO32 | bidirectional | IO pin powered by VDD_IO_4 with input enabled at reset; F2 is SPI2_HOLD_PAD, F3 is GMAC_RMII_CLK_PAD, and it is a dedicated I3C master SCL pin with configurable pull-up. |
| 64 | GPIO33 | bidirectional | IO pin powered by VDD_IO_4 with input enabled at reset; F2 is SPI2_WP_PAD, F3 is GMAC_PHY_TXEN_PAD, and it is a dedicated I3C master SDA pin with configurable pull-up. |
| 65 | GPIO34 | bidirectional | Strapping IO pin powered by VDD_IO_4 with input enabled at reset (JTAG signal source control, floating by default); F2 is SPI2_IO4_PAD and F3 is GMAC_PHY_TXD0_PAD. |
| 66 | GPIO35 | bidirectional | Strapping IO pin powered by VDD_IO_4 with input enabled and weak pull-up at reset (chip boot mode control, default bit value 1); F2 is SPI2_IO5_PAD and F3 is GMAC_PHY_TXD1_PAD. |
| 67 | VDD_PSRAM_1 | power_in | Power input for PSRAM IO; recommended input voltage 1.65-1.95 V (typ. 1.8 V). |
| 68 | GPIO36 | bidirectional | Strapping IO pin powered by VDD_IO_4 with input enabled at reset (ROM message printing control, floating by default); F2 is SPI2_IO6_PAD and F3 is GMAC_PHY_TXER_PAD. |
| 69 | GPIO37 | bidirectional | Strapping IO pin powered by VDD_IO_4 (chip boot mode control, floating by default); F0 is UART0_TXD and F2 is SPI2_IO7_PAD. |
| 70 | GPIO38 | bidirectional | Strapping IO pin powered by VDD_IO_4 with input enabled at reset (chip boot mode control, floating by default); F0 is UART0_RXD and F2 is SPI2_DQS_PAD. |
| 71 | VDDO_FLASH | power_out | Regulated output supplying the off-package flash, rated up to 50 mA at maximum. |
| 72 | VDDO_PSRAM | power_out | Regulated output supplying in-package and off-package PSRAM, rated up to 50 mA at maximum. |
| 73 | VDDO_3 | power_out | Regulated power output rated up to 50 mA at maximum. |
| 74 | VDDO_4 | power_out | Regulated power output rated up to 50 mA at maximum. |
| 75 | VDD_LDO | power_in | Analog power domain input providing power for the LDOs; recommended input voltage 3.0-3.6 V (typ. 3.3 V). |
| 76 | VDD_HP_2 | power_in | Digital power domain input for the HP core, with absolute maximum allowed input voltage of 0-1.3 V. |
| 77 | VDD_DCDCC | power_in | Analog power domain input providing power for DC/DC control; recommended input voltage 3.0-3.6 V (typ. 3.3 V). |
| 78 | FB_DCDC | passive | Feedback pin of the power supply for the external DC/DC; it regulates VDD_HP_0/1/2/3 together with external feedback resistors. |
| 79 | EN_DCDC | output | Enable output for the external DC/DC converter. |
| 80 | GPIO39 | bidirectional | IO pin powered by VDD_IO_5; F0 is SD1_CDATA0 and F2 is REF_50M_CLK_PAD; default drive strength 20 mA. |
| 81 | GPIO40 | bidirectional | IO pin powered by VDD_IO_5; F0 is SD1_CDATA1 and F2 is GMAC_PHY_TXEN_PAD; default drive strength 20 mA. |
| 82 | GPIO41 | bidirectional | IO pin powered by VDD_IO_5; F0 is SD1_CDATA2 and F2 is GMAC_PHY_TXD0_PAD; default drive strength 20 mA. |
| 83 | GPIO42 | bidirectional | IO pin powered by VDD_IO_5; F0 is SD1_CDATA3 and F2 is GMAC_PHY_TXD1_PAD; default drive strength 20 mA. |
| 84 | GPIO43 | bidirectional | IO pin powered by VDD_IO_5; F0 is SD1_CCLK and F2 is GMAC_PHY_TXER_PAD; default drive strength 20 mA. |
| 85 | VDD_IO_5 | power_in | Digital power domain input for HP IO pins GPIO39-GPIO48; recommended input voltage 1.65-3.6 V (typ. 1.8 V). |
| 86 | GPIO44 | bidirectional | IO pin powered by VDD_IO_5; F0 is SD1_CCMD and F2 is GMAC_RMII_CLK_PAD; default drive strength 20 mA. |
| 87 | GPIO45 | bidirectional | IO pin powered by VDD_IO_5; F0 is SD1_CDATA4 and F2 is GMAC_PHY_RXDV_PAD; default drive strength 20 mA. |
| 88 | GPIO46 | bidirectional | IO pin powered by VDD_IO_5; F0 is SD1_CDATA5 and F2 is GMAC_PHY_RXD0_PAD; default drive strength 20 mA. |
| 89 | GPIO47 | bidirectional | IO pin powered by VDD_IO_5; F0 is SD1_CDATA6 and F2 is GMAC_PHY_RXD1_PAD; default drive strength 20 mA. |
| 90 | GPIO48 | bidirectional | IO pin powered by VDD_IO_5; F0 is SD1_CDATA7 and F2 is GMAC_PHY_RXER_PAD; default drive strength 20 mA. |
| 91 | VDD_HP_3 | power_in | Digital power domain input for the HP core, with absolute maximum allowed input voltage of 0-1.3 V. |
| 92 | GPIO49 | bidirectional | IO pin powered by VDD_IO_6 with analog function ADC2_CHANNEL0; F2 is GMAC_PHY_TXEN_PAD; default drive strength 20 mA. |
| 93 | GPIO50 | bidirectional | IO pin powered by VDD_IO_6 with analog function ADC2_CHANNEL1; F2 is GMAC_RMII_CLK_PAD; default drive strength 20 mA. |
| 94 | GPIO51 | bidirectional | IO pin powered by VDD_IO_6 with analog functions ADC2_CHANNEL2 and ANA_COMP0; F2 is GMAC_PHY_RXDV_PAD; default drive strength 20 mA. |
| 95 | GPIO52 | bidirectional | IO pin powered by VDD_IO_6 with analog functions ADC2_CHANNEL3 and ANA_COMP0; F2 is GMAC_PHY_RXD0_PAD; default drive strength 20 mA. |
| 96 | VDD_IO_6 | power_in | Digital power domain input for HP IO pins GPIO49-GPIO54; recommended input voltage 1.65-3.6 V (typ. 1.8 V). |
| 97 | GPIO53 | bidirectional | IO pin powered by VDD_IO_6 with analog functions ADC2_CHANNEL4 and ANA_COMP1; F2 is GMAC_PHY_RXD1_PAD; default drive strength 20 mA. |
| 98 | GPIO54 | bidirectional | IO pin powered by VDD_IO_6 with analog functions ADC2_CHANNEL5 and ANA_COMP1; F2 is GMAC_PHY_RXER_PAD; default drive strength 20 mA. |
| 99 | XTAL_N | passive | Negative external clock input/output connected to the chip's crystal or oscillator. |
| 100 | XTAL_P | passive | Positive external clock input/output connected to the chip's crystal or oscillator (differential clock with XTAL_N). |
| 101 | VDD_ANA | power_in | Analog power domain input; recommended input voltage 3.0-3.6 V (typ. 3.3 V). |
| 102 | VDD_BAT | power_in | Analog power domain input that can optionally connect to an external battery; recommended input voltage 2.5-3.6 V (typ. 3.3 V). |
| 103 | CHIP_PU | input | Chip enable: High enables the chip (powered up), Low disables it (powered down); it must not be left floating. |
| 104 | GPIO0 | bidirectional | IO pin powered by VDD_LP/VDD_BAT with analog function XTAL_32K_N and LP_GPIO0; default drive strength 20 mA. |
| 105 | GND | power_in | External ground connection (exposed pad on the QFN104 package). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Espressif Systems |
| Package | 104-VFQFN Exposed Pad |
| Category | Integrated Circuits (ICs) |
| Pins | 105 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Allowed input voltage (VDD_LDO, VDD_DCDCC, VDD_ANA, VDD_BAT, VDD_LP) | | -0.3 | | 3.6 | V | | 88 |
| Allowed input voltage (VDD_IO_0, VDD_FLASHIO, VDD_IO_4, VDD_IO_5, VDD_IO_6) | | -0.3 | | 3.6 | V | | 88 |
| Allowed input voltage (VDD_PSRAM_0, VDD_PSRAM_1) | | 1.62 | | 1.98 | V | | 88 |
| Allowed input voltage (VDD_HP_0, VDD_HP_1, VDD_HP_2, VDD_HP_3) | | 0 | | 1.3 | V | | 88 |
| Allowed input voltage (VDD_MIPI_DPHY) | | 0 | | 2.75 | V | | 88 |
| Allowed input voltage (VDD_USBPHY) | | -0.66 | | 3.96 | V | | 88 |
| Cumulative IO output current | Ioutput | | | 1500 | mA | | 88 |
| Storage temperature | TSTORE | -40 | | 150 | °C | | 88 |
| Recommended input voltage (VDD_LDO, VDD_DCDCC, VDD_ANA, VDD_LP) | | 3 | 3.3 | 3.6 | V | | 88 |
| Recommended input voltage (VDD_BAT) | | 2.5 | 3.3 | 3.6 | V | | 88 |
| Recommended input voltage (VDD_IO_0, VDD_FLASHIO, VDD_IO_4, VDD_IO_5, VDD_IO_6) | | 1.65 | 1.8 | 3.6 | V | | 88 |
| Recommended input voltage (VDD_PSRAM_0, VDD_PSRAM_1) | | 1.65 | 1.8 | 1.95 | V | | 88 |
| Recommended input voltage (VDD_HP_0, VDD_HP_1, VDD_HP_2, VDD_HP_3) | | 0.99 | 1.1 | 1.3 | V | | 89 |
| Recommended input voltage (VDD_MIPI_DPHY) | | 2.25 | 2.5 | 2.75 | V | | 89 |
| Recommended input voltage (VDD_USBPHY) | | 2.97 | 3.3 | 3.63 | V | | 89 |
| Current supplied to core | IVDD | 0.5 | | | A | | 89 |
| Ambient temperature | TA | -40 | | 85 | °C | | 89 |
| Low-level input voltage | VIL | -0.3 | | | V | | 89 |
| High-level input current | IIH | | | 50 | nA | | 89 |
| Low-level input current | IIL | | | 50 | nA | | 89 |
| Chip reset voltage | VIL_nRST | -0.3 | | | V | CHIP_PU voltage is within the specified range | 90 |
| Differential nonlinearity (DNL) | DNL | -1 | | 3 | LSB | | 90 |
| Integral nonlinearity (INL) | INL | -5 | | 3 | LSB | | 90 |
| ADC sampling rate | | | | 100 | kSPS | | 90 |
| Total error ATTEN0 | | -12 | | 12 | mV | effective measurement range of 0-1000 | 90 |
| Total error ATTEN1 | | -12 | | 12 | mV | effective measurement range of 0-1300 | 90 |
| Total error ATTEN2 | | -12 | | 12 | mV | effective measurement range of 0-1900 | 90 |
| Total error ATTEN3 | | -15 | | 15 | mV | effective measurement range of 0-3300 | 90 |
| Power supply voltage (1.8 V PSRAM) | VCC | 1.62 | 1.8 | 1.98 | V | Power supply voltage (1.8 V) | 92 |
| Power supply voltage (3.3 V PSRAM) | VCC | 2.7 | 3.3 | 3.6 | V | Power supply voltage (3.3 V) | 92 |
| Maximum clock frequency (PSRAM) | FC | 80 | | | MHz | Maximum clock frequency | 92 |
## CAD (KiCad official)
- Symbol: `ESP32-P4NRW32X`
- Footprint: `PCM_Espressif:ESP32-P4`
- 3D model: 104-VFQFN Exposed Pad, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.85 mm nominal QFN height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files: `esp32-p4nrw32x-etched.step` / `esp32-p4nrw32x-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `esp32-p4nrw32x.step` / `esp32-p4nrw32x.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Espressif Systems datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-p4_datasheet_en.pdf) (102 pp, sha256 `fb4f3e91cc2ac519`, retrieved 2026-10-28, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/esp32-p4nrw32x-datasheet.pdf)