component
ESP32-P4NRW32
Public Made by Adomby adom
ESPRESSIF Functional Modules, QFN-104(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D. Chip revision v1.x; ESP32-P4NRW32X is the newer revision (v3.x).
Made with KiCad 10.0 · needs KiCad 10.0 or later to open · KiCad file format 20251024
ESP32-P4NRW32
ESPRESSIF · Functional Modules · QFN-104(10x10)
ESP32-P4NRW32 from ESPRESSIF, in a QFN-104(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Silicon revision
ESP32-P4NRW32 is chip revision v1.x, the older revision. ESP32-P4NRW32X is the newer revision, v3.x, in the same 104-pin 10 x 10 mm QFN; for a new design, use ESP32-P4NRW32X. Espressif documents them separately: v1.x in the ESP32-P4 chip revision v1.3 datasheet, v3.x in the ESP32-P4 Series datasheet (v0.7 covers v3.x only). Two differences matter for a board, both from Espressif's own KiCad symbols (ESP32-P4 and ESP32-P4X): pin 54 is NC on v1.x but VDD_HP_1 (a supply pin) on v3.x, so a board drawn for v1.x needs pin 54 wired to the supply before it takes a v3.x part; and the ADC pins move. On v1.x GPIO0 to GPIO23 and GPIO49 to GPIO54 are marked ADC; on v3.x only GPIO16 to GPIO23 (ADC1 channels 0 to 7) and GPIO49 to GPIO54 (ADC2 channels 0 to 5) are, so a v1.x design reading an analog input on GPIO0 to GPIO15 needs it moved. Check both against the datasheets before swapping one for the other.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GPIO1 | bidirectional | GPIO1 is powered by VDD_LP/VDD_BAT, has no pin setting at reset, and offers IO MUX GPIO1, LP IO MUX LP_GPIO1 and analog XTAL_32K_P functions. |
| 2 | GPIO2 | bidirectional | GPIO2 is powered by VDD_LP/VDD_BAT with input enabled and weak pull-up enabled at reset, and its IO MUX F0 function is MTCK (JTAG test clock) with touch channel TOUCH_CHANNEL1. |
| 3 | GPIO3 | bidirectional | GPIO3 is powered by VDD_LP/VDD_BAT with input enabled at reset, and its IO MUX F0 function is MTDI (JTAG test data in) with touch channel TOUCH_CHANNEL2. |
| 4 | GPIO4 | bidirectional | GPIO4 is powered by VDD_LP with input enabled at reset, and its IO MUX F0 function is MTMS (JTAG test mode select) with touch channel TOUCH_CHANNEL3. |
| 5 | GPIO5 | bidirectional | GPIO5 is powered by VDD_LP, and its IO MUX F0 function is MTDO (JTAG test data out) with touch channel TOUCH_CHANNEL4. |
| 6 | GPIO6 | bidirectional | GPIO6 is powered by VDD_LP and its IO MUX F2 function is SPI2_HOLD_PAD, with touch channel TOUCH_CHANNEL5 and LP_GPIO6 available. |
| 7 | GPIO7 | bidirectional | GPIO7 is powered by VDD_LP and its IO MUX F2 function is SPI2_CS_PAD, with touch channel TOUCH_CHANNEL6 and LP_GPIO7 available. |
| 8 | GPIO8 | bidirectional | GPIO8 is powered by VDD_LP and its IO MUX F2 function is SPI2_D_PAD, with touch channel TOUCH_CHANNEL7 and LP_GPIO8 available. |
| 9 | VDD_LP | power_in | LP power domain supply; recommended input voltage is 3.0 V to 3.6 V (typ. 3.3 V). |
| 10 | GPIO9 | bidirectional | GPIO9 is powered by VDD_LP and its IO MUX F2 function is SPI2_CK_PAD, with touch channel TOUCH_CHANNEL8 and LP_GPIO9 available. |
| 11 | GPIO10 | bidirectional | GPIO10 is powered by VDD_LP and its IO MUX F2 function is SPI2_Q_PAD, with touch channel TOUCH_CHANNEL9 and LP_GPIO10 available. |
| 12 | GPIO11 | bidirectional | GPIO11 is powered by VDD_LP and its IO MUX F2 function is SPI2_WP_PAD, with touch channel TOUCH_CHANNEL10 and LP_GPIO11 available. |
| 13 | GPIO12 | bidirectional | GPIO12 is powered by VDD_LP and provides touch channel TOUCH_CHANNEL11, LP_GPIO12 and IO MUX GPIO function. |
| 14 | GPIO13 | bidirectional | GPIO13 is powered by VDD_LP and provides touch channel TOUCH_CHANNEL12, LP_GPIO13 and IO MUX GPIO function. |
| 15 | GPIO14 | bidirectional | GPIO14 is powered by VDD_LP and its LP IO MUX function is LP_UART_TXD_PAD, with touch channel TOUCH_CHANNEL13 and LP_GPIO14 available. |
| 16 | GPIO15 | bidirectional | GPIO15 is powered by VDD_LP and its LP IO MUX function is LP_UART_RXD_PAD, with touch channel TOUCH_CHANNEL14 and LP_GPIO15 available. |
| 17 | GPIO16 | bidirectional | GPIO16 is powered by VDD_IO_0 and provides IO MUX GPIO function and analog ADC1_CHANNEL0. |
| 18 | GPIO17 | bidirectional | GPIO17 is powered by VDD_IO_0 and provides IO MUX GPIO function and analog ADC1_CHANNEL1. |
| 19 | GPIO18 | bidirectional | GPIO18 is powered by VDD_IO_0 and provides IO MUX GPIO function and analog ADC1_CHANNEL2. |
| 20 | GPIO19 | bidirectional | GPIO19 is powered by VDD_IO_0 and provides IO MUX GPIO function and analog ADC1_CHANNEL3. |
| 21 | VDD_IO_0 | power_in | Digital power domain supply for HP IOs; recommended input voltage is 1.65 V to 3.6 V (typ. 3.3 V). |
| 22 | GPIO20 | bidirectional | GPIO20 is powered by VDD_IO_0 and provides IO MUX GPIO function and analog ADC1_CHANNEL4. |
| 23 | GPIO21 | bidirectional | GPIO21 is powered by VDD_IO_0 and provides IO MUX GPIO function and analog ADC1_CHANNEL5. |
| 24 | GPIO22 | bidirectional | GPIO22 is powered by VDD_IO_0 and provides IO MUX GPIO function and analog ADC1_CHANNEL6. |
| 25 | GPIO23 | bidirectional | GPIO23 is powered by VDD_IO_0, provides IO MUX GPIO function with REF_50M_CLK_PAD (50 MHz reference clock output) and analog ADC1_CHANNEL7. |
| 26 | VDD_HP_0 | power_in | Digital power domain supply; recommended input voltage is 0.99 V to 1.3 V (typ. 1.1 V). |
| 27 | FLASH_CS | output | Dedicated off-package flash chip-select output, powered by VDD_FLASHIO. |
| 28 | FLASH_Q | bidirectional | Dedicated off-package flash data output (DO) pin, powered by VDD_FLASHIO. |
| 29 | FLASH_WP | bidirectional | Dedicated off-package flash write-protect (WP#) pin, powered by VDD_FLASHIO. |
| 30 | VDD_FLASHIO | power_in | Power supply for flash IO; the voltage should be adjusted according to the specific flash model, and the datasheet describes 3.3 V flash as the example. |
| 31 | FLASH_HOLD | bidirectional | Dedicated off-package flash HOLD# pin, powered by VDD_FLASHIO. |
| 32 | FLASH_CK | output | Dedicated off-package flash clock output, powered by VDD_FLASHIO. |
| 33 | FLASH_D | bidirectional | Dedicated off-package flash data input (DI) pin, powered by VDD_FLASHIO. |
| 34 | DSI_REXT | passive | MIPI DSI PHY external 4.02 kΩ reference resistor connection, powered by VDD_MIPI_DPHY. |
| 35 | DSI_DATAP1 | bidirectional | MIPI DSI PHY data positive channel 1, powered by VDD_MIPI_DPHY. |
| 36 | DSI_DATAN1 | bidirectional | MIPI DSI PHY data negative channel 1, powered by VDD_MIPI_DPHY. |
| 37 | DSI_CLKN | bidirectional | MIPI DSI PHY clock negative channel, powered by VDD_MIPI_DPHY. |
| 38 | DSI_CLKP | bidirectional | MIPI DSI PHY clock positive channel, powered by VDD_MIPI_DPHY. |
| 39 | DSI_DATAP0 | bidirectional | MIPI DSI PHY data positive channel 0, powered by VDD_MIPI_DPHY. |
| 40 | DSI_DATAN0 | bidirectional | MIPI DSI PHY data negative channel 0, powered by VDD_MIPI_DPHY. |
| 41 | VDD_MIPI_DPHY | power_in | MIPI PHY supply; recommended input voltage is 2.25 V to 2.75 V (typ. 2.5 V). |
| 42 | CSI_DATAN0 | bidirectional | MIPI CSI PHY data negative channel 0, powered by VDD_MIPI_DPHY. |
| 43 | CSI_DATAP0 | bidirectional | MIPI CSI PHY data positive channel 0, powered by VDD_MIPI_DPHY. |
| 44 | CSI_CLKP | bidirectional | MIPI CSI PHY clock positive channel, powered by VDD_MIPI_DPHY. |
| 45 | CSI_CLKN | bidirectional | MIPI CSI PHY clock negative channel, powered by VDD_MIPI_DPHY. |
| 46 | CSI_DATAN1 | bidirectional | MIPI CSI PHY data negative channel 1, powered by VDD_MIPI_DPHY. |
| 47 | CSI_DATAP1 | bidirectional | MIPI CSI PHY data positive channel 1, powered by VDD_MIPI_DPHY. |
| 48 | CSI_REXT | passive | MIPI CSI PHY external 4.02 kΩ reference resistor connection, powered by VDD_MIPI_DPHY. |
| 49 | USB_DM | bidirectional | USB 2.0 High-Speed OTG PHY D- (USB_D-) signal, powered by VDD_USBPHY. |
| 50 | USB_DP | bidirectional | USB 2.0 High-Speed OTG PHY D+ (USB_D+) signal, powered by VDD_USBPHY. |
| 51 | VDD_USBPHY | power_in | USB PHY supply; recommended input voltage is 2.97 V to 3.63 V (typ. 3.3 V). |
| 52 | GPIO24 | bidirectional | GPIO24 is powered by VDD_IO_4, has a default drive strength of 40 mA, and provides analog USB1P1_N0 as its USB full-speed D- function. |
| 53 | GPIO25 | bidirectional | GPIO25 is powered by VDD_IO_4 with USB pull-up enabled at reset, has a default drive strength of 40 mA, and provides analog USB1P1_P0 as its USB full-speed D+ function. |
| 54 | NC | unconnected | No-connect pin; the datasheet specifies no function for this pin. |
| 55 | GPIO26 | bidirectional | GPIO26 is powered by VDD_IO_4 and provides analog USB1P1_N1 as a USB full-speed D- function; USB pins are enabled for USB by default. |
| 56 | GPIO27 | bidirectional | GPIO27 is powered by VDD_IO_4 and provides analog USB1P1_P1 as a USB full-speed D+ function; USB pins are enabled for USB by default. |
| 57 | GPIO28 | bidirectional | GPIO28 is powered by VDD_IO_4 and its IO MUX functions are SPI2_CS_PAD (F2) and GMAC_PHY_RXDV_PAD (F3, RMII/MII receive data valid). |
| 58 | GPIO29 | bidirectional | GPIO29 is powered by VDD_IO_4 and its IO MUX functions are SPI2_D_PAD (F2) and GMAC_PHY_RXD0_PAD (F3, Ethernet receive data line 0). |
| 59 | VDD_PSRAM_0 | power_in | PSRAM IO supply; recommended input voltage is 1.65 V to 1.95 V (typ. 1.8 V). |
| 60 | GPIO30 | bidirectional | GPIO30 is powered by VDD_IO_4 and its IO MUX functions are SPI2_CK_PAD (F2) and GMAC_PHY_RXD1_PAD (F3, Ethernet receive data line 1). |
| 61 | GPIO31 | bidirectional | GPIO31 is powered by VDD_IO_4 and its IO MUX functions are SPI2_Q_PAD (F2) and GMAC_PHY_RXER_PAD (F3, Ethernet receive error). |
| 62 | VDD_IO_4 | power_in | Digital power domain supply for HP IOs; recommended input voltage is 1.65 V to 3.6 V (typ. 3.3 V). |
| 63 | GPIO32 | bidirectional | GPIO32 is powered by VDD_IO_4 with input enabled at reset, and its IO MUX functions are SPI2_HOLD_PAD (F2) and GMAC_RMII_CLK_PAD (F3). |
| 64 | GPIO33 | bidirectional | GPIO33 is powered by VDD_IO_4 with input enabled at reset, and its IO MUX functions are SPI2_WP_PAD (F2) and GMAC_PHY_TXEN_PAD (F3, Ethernet transmit enable). |
| 65 | GPIO34 | bidirectional | GPIO34 is powered by VDD_IO_4 with input enabled at reset and is a strapping pin that selects the JTAG signal source (floating by default); its IO MUX functions are SPI2_IO4_PAD (F2) and GMAC_PHY_TXD0_PAD (F3). |
| 66 | GPIO35 | bidirectional | GPIO35 is powered by VDD_IO_4 with input enabled and weak pull-up enabled at reset, and is a chip boot mode strapping pin (weak pull-up, bit value 1 by default); its IO MUX functions are SPI2_IO5_PAD (F2) and GMAC_PHY_TXD1_PAD (F3). |
| 67 | VDD_PSRAM_1 | power_in | PSRAM IO supply; recommended input voltage is 1.65 V to 1.95 V (typ. 1.8 V). |
| 68 | GPIO36 | bidirectional | GPIO36 is powered by VDD_IO_4 with input enabled at reset and is a strapping pin for ROM message printing (floating by default); its IO MUX functions are SPI2_IO6_PAD (F2) and GMAC_PHY_TXER_PAD (F3). |
| 69 | GPIO37 | bidirectional | GPIO37 is powered by VDD_IO_4 and is a chip boot mode strapping pin; its IO MUX functions are UART0_TXD_PAD (F0) and SPI2_IO7_PAD (F2). |
| 70 | GPIO38 | bidirectional | GPIO38 is powered by VDD_IO_4 with input enabled at reset and is a chip boot mode strapping pin; its IO MUX functions are UART0_RXD_PAD (F0) and SPI2_DQS_PAD (F2). |
| 71 | VDDO_FLASH | power_out | Regulated output rail for off-package flash, supplying up to 50 mA at maximum. |
| 72 | VDDO_PSRAM | power_out | Regulated output rail for in-package and off-package PSRAM, supplying up to 50 mA at maximum. |
| 73 | VDDO_3 | power_out | Regulated output rail, supplying up to 50 mA at maximum. |
| 74 | VDDO_4 | power_out | Regulated output rail, supplying up to 50 mA at maximum. |
| 75 | VDD_LDO | power_in | Analog power domain supply for the LDOs; recommended input voltage is 3.0 V to 3.6 V (typ. 3.3 V). |
| 76 | VDD_HP_2 | power_in | Digital power domain supply; recommended input voltage is 0.99 V to 1.3 V (typ. 1.1 V). |
| 77 | VDD_DCDCC | power_in | Analog power domain supply for DC/DC control; recommended input voltage is 3.0 V to 3.6 V (typ. 3.3 V). |
| 78 | FB_DCDC | passive | Feedback pin of the external DC/DC power supply, which regulates VDD_HP_0/2/3 together with feedback resistors. |
| 79 | EN_DCDC | output | Enable pin of the external DC/DC converter. |
| 80 | GPIO39 | bidirectional | GPIO39 is powered by VDD_IO_5 and its IO MUX functions are SD1_CDATA0_PAD (F0) and REF_50M_CLK_PAD (F3, 50 MHz reference clock output). |
| 81 | GPIO40 | bidirectional | GPIO40 is powered by VDD_IO_5 and its IO MUX functions are SD1_CDATA1_PAD (F0) and GMAC_PHY_TXEN_PAD (F3). |
| 82 | GPIO41 | bidirectional | GPIO41 is powered by VDD_IO_5 and its IO MUX functions are SD1_CDATA2_PAD (F0) and GMAC_PHY_TXD0_PAD (F3). |
| 83 | GPIO42 | bidirectional | GPIO42 is powered by VDD_IO_5 and its IO MUX functions are SD1_CDATA3_PAD (F0) and GMAC_PHY_TXD1_PAD (F3). |
| 84 | GPIO43 | bidirectional | GPIO43 is powered by VDD_IO_5 and its IO MUX functions are SD1_CCLK_PAD (F0) and GMAC_PHY_TXER_PAD (F3). |
| 85 | VDD_IO_5 | power_in | Digital power domain supply for HP IOs; recommended input voltage is 1.65 V to 3.6 V (typ. 3.3 V). |
| 86 | GPIO44 | bidirectional | GPIO44 is powered by VDD_IO_5 and its IO MUX functions are SD1_CCMD_PAD (F0) and GMAC_RMII_CLK_PAD (F3). |
| 87 | GPIO45 | bidirectional | GPIO45 is powered by VDD_IO_5 and its IO MUX functions are SD1_CDATA4_PAD (F0) and GMAC_PHY_RXDV_PAD (F3). |
| 88 | GPIO46 | bidirectional | GPIO46 is powered by VDD_IO_5 and its IO MUX functions are SD1_CDATA5_PAD (F0) and GMAC_PHY_RXD0_PAD (F3). |
| 89 | GPIO47 | bidirectional | GPIO47 is powered by VDD_IO_5 and its IO MUX functions are SD1_CDATA6_PAD (F0) and GMAC_PHY_RXD1_PAD (F3). |
| 90 | GPIO48 | bidirectional | GPIO48 is powered by VDD_IO_5 and its IO MUX functions are SD1_CDATA7_PAD (F0) and GMAC_PHY_RXER_PAD (F3). |
| 91 | VDD_HP_3 | power_in | Digital power domain supply; recommended input voltage is 0.99 V to 1.3 V (typ. 1.1 V). |
| 92 | GPIO49 | bidirectional | GPIO49 is powered by VDD_IO_6 and provides analog ADC2_CHANNEL0 and IO MUX GMAC_PHY_TXEN_PAD (F3). |
| 93 | GPIO50 | bidirectional | GPIO50 is powered by VDD_IO_6 and provides analog ADC2_CHANNEL1 and IO MUX GMAC_RMII_CLK_PAD (F3). |
| 94 | GPIO51 | bidirectional | GPIO51 is powered by VDD_IO_6 and provides analog ADC2_CHANNEL2 and ANA_COMP0, and IO MUX GMAC_PHY_RXDV_PAD (F3). |
| 95 | GPIO52 | bidirectional | GPIO52 is powered by VDD_IO_6 and provides analog ADC2_CHANNEL3 and ANA_COMP0, and IO MUX GMAC_PHY_RXD0_PAD (F3). |
| 96 | VDD_IO_6 | power_in | Digital power domain supply for HP IOs; recommended input voltage is 1.65 V to 3.6 V (typ. 3.3 V). |
| 97 | GPIO53 | bidirectional | GPIO53 is powered by VDD_IO_6 and provides analog ADC2_CHANNEL4 and ANA_COMP1, and IO MUX GMAC_PHY_RXD1_PAD (F3). |
| 98 | GPIO54 | bidirectional | GPIO54 is powered by VDD_IO_6 and provides analog ADC2_CHANNEL5 and ANA_COMP1, and IO MUX GMAC_PHY_RXER_PAD (F3). |
| 99 | XTAL_N | passive | Differential negative external clock input/output connected to the chip's crystal or oscillator. |
| 100 | XTAL_P | passive | Differential positive external clock input/output connected to the chip's crystal or oscillator. |
| 101 | VDD_ANA | power_in | Analog power domain supply; recommended input voltage is 3.0 V to 3.6 V (typ. 3.3 V). |
| 102 | VDD_BAT | power_in | Analog power domain supply that can optionally connect to an external battery; recommended input voltage is 2.5 V to 3.6 V (typ. 3.3 V). |
| 103 | CHIP_PU | input | Chip enable: high enables the chip (powered up), low disables it (powered down), and the pin must not be left floating. |
| 104 | GPIO0 | bidirectional | GPIO0 is powered by VDD_LP/VDD_BAT, provides IO MUX GPIO function, LP_GPIO0 and analog XTAL_32K_N. |
| 105 | GND | power_in | External ground connection (exposed pad). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | ESPRESSIF |
| Package | QFN-104(10x10) |
| Category | Functional Modules |
| Pins | 105 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Allowed input voltage (VDD_LDO, VDD_DCDCC, VDD_ANA, VDD_BAT, VDD_LP) | -0.3 | 3.6 | V | 79 | |||
| Allowed input voltage (VDD_IO_0, VDD_FLASHIO, VDD_IO_4, VDD_IO_5, VDD_IO_6) | -0.3 | 3.6 | V | 79 | |||
| Allowed input voltage (VDD_PSRAM_0, VDD_PSRAM_1) | 1.62 | 1.98 | V | 79 | |||
| Allowed input voltage (VDD_HP_0, VDD_HP_2, VDD_HP_3) | 0 | 1.3 | V | 79 | |||
| Allowed input voltage (VDD_MIPI_DPHY) | 0 | 2.75 | V | 79 | |||
| Allowed input voltage (VDD_USBPHY) | -0.66 | 3.96 | V | 79 | |||
| Cumulative IO output current | Ioutput | 1500 | mA | 79 | |||
| Storage temperature | TSTORE | -40 | 150 | °C | 79 | ||
| Recommended input voltage (VDD_LDO, VDD_DCDCC, VDD_ANA, VDD_LP) | 3 | 3.3 | 3.6 | V | 79 | ||
| Recommended input voltage (VDD_BAT) | 2.5 | 3.3 | 3.6 | V | 79 | ||
| Recommended input voltage (VDD_IO_0, VDD_FLASHIO, VDD_IO_4, VDD_IO_5, VDD_IO_6) | 1.65 | 3.3 | 3.6 | V | 79 | ||
| Recommended input voltage (VDD_PSRAM_0, VDD_PSRAM_1) | 1.65 | 1.8 | 1.95 | V | 79 | ||
| Recommended input voltage (VDD_HP_0, VDD_HP_2, VDD_HP_3) | 0.99 | 1.1 | 1.3 | V | 79 | ||
| Recommended input voltage (VDD_MIPI_DPHY) | 2.25 | 2.5 | 2.75 | V | 79 | ||
| Recommended input voltage (VDD_USBPHY) | 2.97 | 3.3 | 3.63 | V | 79 | ||
| Current supplied to core | IVDD | 0.5 | A | 79 | |||
| Ambient temperature | TA | -40 | 85 | °C | 79 | ||
| Low-level input voltage | VIL | -0.3 | V | VDD = voltage of VDD_IO_0/4/5/6 (footnote 1) | 80 | ||
| High-level input current | IIH | 50 | nA | 80 | |||
| Low-level input current | IIL | 50 | nA | 80 | |||
| Chip reset voltage (CHIP_PU voltage is within the specified range) | VIL_nRST | -0.3 | V | CHIP_PU voltage is within the specified range | 80 | ||
| Differential nonlinearity (DNL) | DNL | -1 | 3 | LSB | 81 | ||
| Integral nonlinearity (INL) | INL | -5 | 3 | LSB | 81 | ||
| Sampling rate | 100 | kSPS | 81 | ||||
| Total error, ATTEN0 | -12 | 12 | mV | effective measurement range of 0-1000 | 81 | ||
| Total error, ATTEN1 | -12 | 12 | mV | effective measurement range of 0-1300 | 81 | ||
| Total error, ATTEN2 | -12 | 12 | mV | effective measurement range of 0-1900 | 81 | ||
| Total error, ATTEN3 | -15 | 15 | mV | effective measurement range of 0-3300 | 81 | ||
| Power supply voltage (1.8 V) | VCC | 1.62 | 1.8 | 1.98 | V | 82 | |
| Power supply voltage (3.3 V) | VCC | 2.7 | 3.3 | 3.6 | V | 82 | |
| Maximum clock frequency (PSRAM) | FC | 80 | MHz | 82 |
CAD (KiCad official)
- Symbol:
ESP32-P4NRW32 - Footprint:
PCM_Espressif:ESP32-P4 - 3D model: QFN-104(10x10), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.85 mm nominal QFN height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files:
esp32-p4nrw32-etched.step/esp32-p4nrw32-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);esp32-p4nrw32.step/esp32-p4nrw32.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: ESPRESSIF datasheet (94 pp, sha256
52ef629ec92510a6, retrieved 2026-10-28, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).