component

ESP32-P4NRW32

Public Made by Adom

by adom

ESPRESSIF Functional Modules, QFN-104(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D. Chip revision v1.x; ESP32-P4NRW32X is the newer revision (v3.x).

componentfunctional modulesesp32-p4nrw32factory-2.0.0extractor-text
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Publish 0.1.3

Ray ·de8bf31795 · ·parent 4b0386d
5 files changed +2838−2841
README.md+116−119esp32-p4nrw32-hero.overlay.json+2489−2487esp32-p4nrw32.step+1−1package.json+115−116page.json+117−118
README.md+116−119
@@ -4,115 +4,119 @@  ESP32-P4NRW32 from ESPRESSIF, in a QFN-104(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD. +## Silicon revision++ESP32-P4NRW32 is chip revision **v1.x**, the **older** revision. [ESP32-P4NRW32X](https://wiki.adom.inc/adom/esp32-p4nrw32x) is the **newer** revision, v3.x, in the same 104-pin 10 x 10 mm QFN; for a new design, use ESP32-P4NRW32X. Espressif documents them separately: v1.x in the ESP32-P4 chip revision v1.3 datasheet, v3.x in the ESP32-P4 Series datasheet (v0.7 covers v3.x only). Two differences matter for a board, both from Espressif's own KiCad symbols (ESP32-P4 and ESP32-P4X): pin 54 is NC on v1.x but VDD_HP_1 (a supply pin) on v3.x, so a board drawn for v1.x needs pin 54 wired to the supply before it takes a v3.x part; and the ADC pins move. On v1.x GPIO0 to GPIO23 and GPIO49 to GPIO54 are marked ADC; on v3.x only GPIO16 to GPIO23 (ADC1 channels 0 to 7) and GPIO49 to GPIO54 (ADC2 channels 0 to 5) are, so a v1.x design reading an analog input on GPIO0 to GPIO15 needs it moved. Check both against the datasheets before swapping one for the other.+ ## Pinout  | Pin | Name | Type | Function | |---|---|---|---|-| 1 | GPIO1 | bidirectional | GPIO1 is a general-purpose IO powered from VDD_LP/VDD_BAT that also carries the XTAL_32K_P analog function and LP_GPIO1 in Deep-sleep mode, with default drive strength 20 mA. |-| 2 | GPIO2 | bidirectional | GPIO2 is an LP IO powered from VDD_LP/VDD_BAT that carries the MTCK JTAG clock, TOUCH_CHANNEL1 and LP_GPIO2, and is input-enabled with weak pull-up at reset (EFUSE_DIS_PAD_JTAG dependent). |-| 3 | GPIO3 | bidirectional | GPIO3 is an LP IO powered from VDD_LP/VDD_BAT that carries the MTDI JTAG input, TOUCH_CHANNEL2 and LP_GPIO3, and is input-enabled at reset. |-| 4 | GPIO4 | bidirectional | GPIO4 is an LP IO powered from VDD_LP that carries the MTMS JTAG input, TOUCH_CHANNEL3 and LP_GPIO4, and is input-enabled at reset. |-| 5 | GPIO5 | bidirectional | GPIO5 is an LP IO powered from VDD_LP that carries the MTDO JTAG output (tri-state capable), TOUCH_CHANNEL4 and LP_GPIO5. |-| 6 | GPIO6 | bidirectional | GPIO6 is an LP IO powered from VDD_LP that carries the SPI2_HOLD_PAD (8-line/4-line SPI2 interface), TOUCH_CHANNEL5 and LP_GPIO6. |-| 7 | GPIO7 | bidirectional | GPIO7 is an LP IO powered from VDD_LP that carries the SPI2_CS_PAD chip select, TOUCH_CHANNEL6 and LP_GPIO7. |-| 8 | GPIO8 | bidirectional | GPIO8 is an LP IO powered from VDD_LP that carries the SPI2_D_PAD data input, TOUCH_CHANNEL7 and LP_GPIO8. |-| 9 | VDD_LP | power_in | VDD_LP is the LP power domain supply, recommended at 3.0 V to 3.6 V (typ. 3.3 V). |-| 10 | GPIO9 | bidirectional | GPIO9 is an LP IO powered from VDD_LP that carries the SPI2_CK_PAD clock, TOUCH_CHANNEL8 and LP_GPIO9. |-| 11 | GPIO10 | bidirectional | GPIO10 is an LP IO powered from VDD_LP that carries the SPI2_Q_PAD data output, TOUCH_CHANNEL9 and LP_GPIO10. |-| 12 | GPIO11 | bidirectional | GPIO11 is an LP IO powered from VDD_LP that carries the SPI2_WP_PAD write protect, TOUCH_CHANNEL10 and LP_GPIO11. |-| 13 | GPIO12 | bidirectional | GPIO12 is an LP IO powered from VDD_LP that carries TOUCH_CHANNEL11 and LP_GPIO12. |-| 14 | GPIO13 | bidirectional | GPIO13 is an LP IO powered from VDD_LP that carries TOUCH_CHANNEL12 and LP_GPIO13. |-| 15 | GPIO14 | bidirectional | GPIO14 is an LP IO powered from VDD_LP that carries the LP_UART_TXD_PAD transmit output, TOUCH_CHANNEL13 and LP_GPIO14. |-| 16 | GPIO15 | bidirectional | GPIO15 is an LP IO powered from VDD_LP that carries the LP_UART_RXD_PAD receive input, TOUCH_CHANNEL14 and LP_GPIO15. |-| 17 | GPIO16 | bidirectional | GPIO16 is an HP IO powered from VDD_IO_0 (1.65 V to 3.6 V) that carries the ADC1_CHANNEL0 analog input. |-| 18 | GPIO17 | bidirectional | GPIO17 is an HP IO powered from VDD_IO_0 (1.65 V to 3.6 V) that carries the ADC1_CHANNEL1 analog input. |-| 19 | GPIO18 | bidirectional | GPIO18 is an HP IO powered from VDD_IO_0 (1.65 V to 3.6 V) that carries the ADC1_CHANNEL2 analog input. |-| 20 | GPIO19 | bidirectional | GPIO19 is an HP IO powered from VDD_IO_0 (1.65 V to 3.6 V) that carries the ADC1_CHANNEL3 analog input. |-| 21 | VDD_IO_0 | power_in | VDD_IO_0 is the digital IO power supply for the HP IO group, recommended at 1.65 V to 3.6 V (typ. 3.3 V). |-| 22 | GPIO20 | bidirectional | GPIO20 is an HP IO powered from VDD_IO_0 (1.65 V to 3.6 V) that carries the ADC1_CHANNEL4 analog input. |-| 23 | GPIO21 | bidirectional | GPIO21 is an HP IO powered from VDD_IO_0 (1.65 V to 3.6 V) that carries the ADC1_CHANNEL5 analog input. |-| 24 | GPIO22 | bidirectional | GPIO22 is an HP IO powered from VDD_IO_0 (1.65 V to 3.6 V) that carries the ADC1_CHANNEL6 analog input. |-| 25 | GPIO23 | bidirectional | GPIO23 is an HP IO powered from VDD_IO_0 (1.65 V to 3.6 V) that carries the ADC1_CHANNEL7 analog input and the REF_50M_CLK_PAD 50 MHz reference clock output. |-| 26 | VDD_HP_0 | power_in | VDD_HP_0 is the digital core supply, recommended at 0.99 V to 1.3 V (typ. 1.1 V); the chip can adjust it automatically. |-| 27 | FLASH_CS | output | FLASH_CS is the dedicated off-package flash chip-select output, powered by VDD_FLASHIO. |-| 28 | FLASH_Q | bidirectional | FLASH_Q is the dedicated flash data-output line (DO) powered by VDD_FLASHIO. |-| 29 | FLASH_WP | bidirectional | FLASH_WP is the dedicated flash write-protect line (WP#) powered by VDD_FLASHIO. |-| 30 | VDD_FLASHIO | power_in | VDD_FLASHIO powers the flash IO and should be set according to the flash model; the datasheet uses 3.3 V flash as the example, with recommended input 1.65 V to 3.6 V. |-| 31 | FLASH_HOLD | bidirectional | FLASH_HOLD is the dedicated flash hold line (HOLD#) powered by VDD_FLASHIO. |-| 32 | FLASH_CK | output | FLASH_CK is the dedicated flash clock output (CLK) powered by VDD_FLASHIO. |-| 33 | FLASH_D | bidirectional | FLASH_D is the dedicated flash data-input line (DI) powered by VDD_FLASHIO. |-| 34 | DSI_REXT | bidirectional | DSI_REXT is the MIPI DSI PHY pin for the 4.02 kΩ external reference resistor, powered by VDD_MIPI_DPHY. |-| 35 | DSI_DATAP1 | bidirectional | DSI_DATAP1 is the positive data channel 1 of the MIPI DSI PHY (2-lane, 1.5 Gbps per lane), powered by VDD_MIPI_DPHY. |-| 36 | DSI_DATAN1 | bidirectional | DSI_DATAN1 is the negative data channel 1 of the MIPI DSI PHY, powered by VDD_MIPI_DPHY. |-| 37 | DSI_CLKN | bidirectional | DSI_CLKN is the negative clock channel of the MIPI DSI PHY, powered by VDD_MIPI_DPHY. |-| 38 | DSI_CLKP | bidirectional | DSI_CLKP is the positive clock channel of the MIPI DSI PHY, powered by VDD_MIPI_DPHY. |-| 39 | DSI_DATAP0 | bidirectional | DSI_DATAP0 is the positive data channel 0 of the MIPI DSI PHY, powered by VDD_MIPI_DPHY. |-| 40 | DSI_DATAN0 | bidirectional | DSI_DATAN0 is the negative data channel 0 of the MIPI DSI PHY, powered by VDD_MIPI_DPHY. |-| 41 | VDD_MIPI_DPHY | power_in | VDD_MIPI_DPHY is the MIPI PHY supply, recommended at 2.25 V to 2.75 V (typ. 2.5 V) with an absolute maximum of 2.75 V. |-| 42 | CSI_DATAN0 | bidirectional | CSI_DATAN0 is the negative data channel 0 of the MIPI CSI PHY, powered by VDD_MIPI_DPHY. |-| 43 | CSI_DATAP0 | bidirectional | CSI_DATAP0 is the positive data channel 0 of the MIPI CSI PHY, powered by VDD_MIPI_DPHY. |-| 44 | CSI_CLKP | bidirectional | CSI_CLKP is the positive clock channel of the MIPI CSI PHY, powered by VDD_MIPI_DPHY. |-| 45 | CSI_CLKN | bidirectional | CSI_CLKN is the negative clock channel of the MIPI CSI PHY, powered by VDD_MIPI_DPHY. |-| 46 | CSI_DATAN1 | bidirectional | CSI_DATAN1 is the negative data channel 1 of the MIPI CSI PHY, powered by VDD_MIPI_DPHY. |-| 47 | CSI_DATAP1 | bidirectional | CSI_DATAP1 is the positive data channel 1 of the MIPI CSI PHY, powered by VDD_MIPI_DPHY. |-| 48 | CSI_REXT | bidirectional | CSI_REXT is the MIPI CSI PHY pin for the 4.02 kΩ external reference resistor, powered by VDD_MIPI_DPHY. |-| 49 | USB_DM | bidirectional | USB_DM is the USB 2.0 High-Speed OTG PHY D- signal, powered by VDD_USBPHY. |-| 50 | USB_DP | bidirectional | USB_DP is the USB 2.0 High-Speed OTG PHY D+ signal, powered by VDD_USBPHY. |-| 51 | VDD_USBPHY | power_in | VDD_USBPHY is the USB PHY supply, recommended at 2.97 V to 3.63 V (typ. 3.3 V) with an absolute maximum of 3.96 V. |-| 52 | GPIO24 | bidirectional | GPIO24 is an HP IO powered from VDD_IO_4 with default drive strength 40 mA and the USB1P1_N0 analog function of the USB Full-Speed/Serial-JTAG pair. |-| 53 | GPIO25 | bidirectional | GPIO25 is an HP IO powered from VDD_IO_4 with default drive strength 40 mA, USB_PU pull-up enabled at reset, and the USB1P1_P0 analog function. |-| 54 | NC | unconnected | Pin 54 is listed as NC (no connection) in the datasheet pin table. |-| 55 | GPIO26 | bidirectional | GPIO26 is an HP IO powered from VDD_IO_4 that carries the USB1P1_N1 analog function of the second USB PHY pair, which is the default USB Full-Speed OTG pin pair. |-| 56 | GPIO27 | bidirectional | GPIO27 is an HP IO powered from VDD_IO_4 that carries the USB1P1_P1 analog function of the second USB PHY pair. |-| 57 | GPIO28 | bidirectional | GPIO28 is an HP IO powered from VDD_IO_4 that carries the SPI2_CS_PAD chip select (8-line SPI2) and the GMAC_PHY_RXDV_PAD RMII receive data valid input. |-| 58 | GPIO29 | bidirectional | GPIO29 is an HP IO powered from VDD_IO_4 that carries the SPI2_D_PAD data input and the GMAC_PHY_RXD0_PAD RMII receive data line 0. |-| 59 | VDD_PSRAM_0 | power_in | VDD_PSRAM_0 is the PSRAM IO supply, recommended at 1.65 V to 1.95 V (typ. 1.8 V). |-| 60 | GPIO30 | bidirectional | GPIO30 is an HP IO powered from VDD_IO_4 that carries the SPI2_CK_PAD clock and the GMAC_PHY_RXD1_PAD RMII receive data line 1. |-| 61 | GPIO31 | bidirectional | GPIO31 is an HP IO powered from VDD_IO_4 that carries the SPI2_Q_PAD data output and the GMAC_PHY_RXER_PAD receive error input. |-| 62 | VDD_IO_4 | power_in | VDD_IO_4 is the digital IO power supply for the HP IO group, recommended at 1.65 V to 3.6 V (typ. 3.3 V). |-| 63 | GPIO32 | bidirectional | GPIO32 is an HP IO powered from VDD_IO_4 with input enabled at reset, carrying the SPI2_HOLD_PAD signal, the GMAC_RMII_CLK_PAD RMII clock and the I3C clock/data routing option. |-| 64 | GPIO33 | bidirectional | GPIO33 is an HP IO powered from VDD_IO_4 with input enabled at reset, carrying the SPI2_WP_PAD write protect and the GMAC_PHY_TXEN_PAD transmit enable output. |-| 65 | GPIO34 | bidirectional | GPIO34 is an HP IO powered from VDD_IO_4 with input enabled at reset, carrying the SPI2_IO4_PAD signal and the GMAC_PHY_TXD0_PAD transmit data output, and is the JTAG-source strapping pin. |-| 66 | GPIO35 | bidirectional | GPIO35 is an HP IO powered from VDD_IO_4 with input enabled and weak pull-up at reset, carrying the SPI2_IO5_PAD signal and the GMAC_PHY_TXD1_PAD output, and is a chip boot-mode strapping pin. |-| 67 | VDD_PSRAM_1 | power_in | VDD_PSRAM_1 is the PSRAM IO supply, recommended at 1.65 V to 1.95 V (typ. 1.8 V). |-| 68 | GPIO36 | bidirectional | GPIO36 is an HP IO powered from VDD_IO_4 with input enabled at reset, carrying the SPI2_IO6_PAD signal and the GMAC_PHY_TXER_PAD output, and is a ROM message-printing strapping pin. |-| 69 | GPIO37 | bidirectional | GPIO37 is an HP IO powered from VDD_IO_4 that carries the UART0_TXD_PAD transmit output and the SPI2_IO7_PAD signal, and is a boot-mode strapping pin. |-| 70 | GPIO38 | bidirectional | GPIO38 is an HP IO powered from VDD_IO_4 with input enabled, carrying the UART0_RXD_PAD receive input and the SPI2_DQS_PAD data strobe, and is a boot-mode strapping pin. |-| 71 | VDDO_FLASH | power_out | VDDO_FLASH is a regulated output supply for the off-package flash, rated at 50 mA maximum. |-| 72 | VDDO_PSRAM | power_out | VDDO_PSRAM is a regulated output supply for in-package and off-package PSRAM, rated at 50 mA maximum. |-| 73 | VDDO_3 | power_out | VDDO_3 is a regulated output supply rated at 50 mA maximum. |-| 74 | VDDO_4 | power_out | VDDO_4 is a regulated output supply rated at 50 mA maximum. |-| 75 | VDD_LDO | power_in | VDD_LDO is the analog power domain supply for the internal LDOs, recommended at 3.0 V to 3.6 V (typ. 3.3 V). |-| 76 | VDD_HP_2 | power_in | VDD_HP_2 is a digital core supply, recommended at 0.99 V to 1.3 V (typ. 1.1 V). |-| 77 | VDD_DCDCC | power_in | VDD_DCDCC is the analog power supply for the DC/DC control circuit, recommended at 3.0 V to 3.6 V (typ. 3.3 V). |-| 78 | FB_DCDC | passive | FB_DCDC is the feedback pin of the external DC/DC supply, which regulates VDD_HP_0/2/3 together with external feedback resistors. |-| 79 | EN_DCDC | output | EN_DCDC is the enable output pin for the external DC/DC converter. |-| 80 | GPIO39 | bidirectional | GPIO39 is an HP IO powered from VDD_IO_5 that carries the SD1_CDATA0_PAD SDIO data line and the REF_50M_CLK_PAD 50 MHz clock output. |-| 81 | GPIO40 | bidirectional | GPIO40 is an HP IO powered from VDD_IO_5 that carries the SD1_CDATA1_PAD SDIO data line and the GMAC_PHY_TXEN_PAD transmit enable output. |-| 82 | GPIO41 | bidirectional | GPIO41 is an HP IO powered from VDD_IO_5 that carries the SD1_CDATA2_PAD SDIO data line and the GMAC_PHY_TXD0_PAD transmit data output. |-| 83 | GPIO42 | bidirectional | GPIO42 is an HP IO powered from VDD_IO_5 that carries the SD1_CDATA3_PAD SDIO data line and the GMAC_PHY_TXD1_PAD transmit data output. |-| 84 | GPIO43 | bidirectional | GPIO43 is an HP IO powered from VDD_IO_5 that carries the SD1_CCLK_PAD SDIO card clock output and the GMAC_PHY_TXER_PAD transmit error output. |-| 85 | VDD_IO_5 | power_in | VDD_IO_5 is the digital IO power supply for the HP IO group, recommended at 1.65 V to 3.6 V (typ. 3.3 V). |-| 86 | GPIO44 | bidirectional | GPIO44 is an HP IO powered from VDD_IO_5 that carries the SD1_CCMD_PAD SDIO command line and the GMAC_RMII_CLK_PAD RMII clock input. |-| 87 | GPIO45 | bidirectional | GPIO45 is an HP IO powered from VDD_IO_5 that carries the SD1_CDATA4_PAD SDIO data line and the GMAC_PHY_RXDV_PAD receive data valid input. |-| 88 | GPIO46 | bidirectional | GPIO46 is an HP IO powered from VDD_IO_5 that carries the SD1_CDATA5_PAD SDIO data line and the GMAC_PHY_RXD0_PAD receive data input. |-| 89 | GPIO47 | bidirectional | GPIO47 is an HP IO powered from VDD_IO_5 that carries the SD1_CDATA6_PAD SDIO data line and the GMAC_PHY_RXD1_PAD receive data input. |-| 90 | GPIO48 | bidirectional | GPIO48 is an HP IO powered from VDD_IO_5 that carries the SD1_CDATA7_PAD SDIO data line and the GMAC_PHY_RXER_PAD receive error input. |-| 91 | VDD_HP_3 | power_in | VDD_HP_3 is a digital core supply, recommended at 0.99 V to 1.3 V (typ. 1.1 V). |-| 92 | GPIO49 | bidirectional | GPIO49 is an HP IO powered from VDD_IO_6 that carries the ADC2_CHANNEL0 analog input and the GMAC_PHY_TXEN_PAD transmit enable output. |-| 93 | GPIO50 | bidirectional | GPIO50 is an HP IO powered from VDD_IO_6 that carries the ADC2_CHANNEL1 analog input and the GMAC_RMII_CLK_PAD RMII clock input. |-| 94 | GPIO51 | bidirectional | GPIO51 is an HP IO powered from VDD_IO_6 that carries the ADC2_CHANNEL2 and ANA_COMP0 analog functions and the GMAC_PHY_RXDV_PAD receive data valid input. |-| 95 | GPIO52 | bidirectional | GPIO52 is an HP IO powered from VDD_IO_6 that carries the ADC2_CHANNEL3 and ANA_COMP0 analog functions and the GMAC_PHY_RXD0_PAD receive data input. |-| 96 | VDD_IO_6 | power_in | VDD_IO_6 is the digital IO power supply for the HP IO group, recommended at 1.65 V to 3.6 V (typ. 3.3 V). |-| 97 | GPIO53 | bidirectional | GPIO53 is an HP IO powered from VDD_IO_6 that carries the ADC2_CHANNEL4 and ANA_COMP1 analog functions and the GMAC_PHY_RXD1_PAD receive data input. |-| 98 | GPIO54 | bidirectional | GPIO54 is an HP IO powered from VDD_IO_6 that carries the ADC2_CHANNEL5 and ANA_COMP1 analog functions and the GMAC_PHY_RXER_PAD receive error input. |-| 99 | XTAL_N | passive | XTAL_N is the negative side of the differential clock connection to the chip's crystal or oscillator. |-| 100 | XTAL_P | passive | XTAL_P is the positive side of the differential clock connection to the chip's crystal or oscillator. |-| 101 | VDD_ANA | power_in | VDD_ANA is the analog power domain supply, recommended at 3.0 V to 3.6 V (typ. 3.3 V). |-| 102 | VDD_BAT | power_in | VDD_BAT is the analog power domain supply that can optionally connect to an external battery, recommended at 2.5 V to 3.6 V (typ. 3.3 V). |-| 103 | CHIP_PU | input | CHIP_PU is the chip enable input: high enables the chip and low powers it down, and it must not be left floating. |-| 104 | GPIO0 | bidirectional | GPIO0 is an LP IO powered from VDD_LP/VDD_BAT that carries the XTAL_32K_N analog function and LP_GPIO0. |-| 105 | GND | power_in | GND is the external ground connection pin. |+| 1 | GPIO1 | bidirectional | GPIO1 is powered by VDD_LP/VDD_BAT, has no pin setting at reset, and offers IO MUX GPIO1, LP IO MUX LP_GPIO1 and analog XTAL_32K_P functions. |+| 2 | GPIO2 | bidirectional | GPIO2 is powered by VDD_LP/VDD_BAT with input enabled and weak pull-up enabled at reset, and its IO MUX F0 function is MTCK (JTAG test clock) with touch channel TOUCH_CHANNEL1. |+| 3 | GPIO3 | bidirectional | GPIO3 is powered by VDD_LP/VDD_BAT with input enabled at reset, and its IO MUX F0 function is MTDI (JTAG test data in) with touch channel TOUCH_CHANNEL2. |+| 4 | GPIO4 | bidirectional | GPIO4 is powered by VDD_LP with input enabled at reset, and its IO MUX F0 function is MTMS (JTAG test mode select) with touch channel TOUCH_CHANNEL3. |+| 5 | GPIO5 | bidirectional | GPIO5 is powered by VDD_LP, and its IO MUX F0 function is MTDO (JTAG test data out) with touch channel TOUCH_CHANNEL4. |+| 6 | GPIO6 | bidirectional | GPIO6 is powered by VDD_LP and its IO MUX F2 function is SPI2_HOLD_PAD, with touch channel TOUCH_CHANNEL5 and LP_GPIO6 available. |+| 7 | GPIO7 | bidirectional | GPIO7 is powered by VDD_LP and its IO MUX F2 function is SPI2_CS_PAD, with touch channel TOUCH_CHANNEL6 and LP_GPIO7 available. |+| 8 | GPIO8 | bidirectional | GPIO8 is powered by VDD_LP and its IO MUX F2 function is SPI2_D_PAD, with touch channel TOUCH_CHANNEL7 and LP_GPIO8 available. |+| 9 | VDD_LP | power_in | LP power domain supply; recommended input voltage is 3.0 V to 3.6 V (typ. 3.3 V). |+| 10 | GPIO9 | bidirectional | GPIO9 is powered by VDD_LP and its IO MUX F2 function is SPI2_CK_PAD, with touch channel TOUCH_CHANNEL8 and LP_GPIO9 available. |+| 11 | GPIO10 | bidirectional | GPIO10 is powered by VDD_LP and its IO MUX F2 function is SPI2_Q_PAD, with touch channel TOUCH_CHANNEL9 and LP_GPIO10 available. |+| 12 | GPIO11 | bidirectional | GPIO11 is powered by VDD_LP and its IO MUX F2 function is SPI2_WP_PAD, with touch channel TOUCH_CHANNEL10 and LP_GPIO11 available. |+| 13 | GPIO12 | bidirectional | GPIO12 is powered by VDD_LP and provides touch channel TOUCH_CHANNEL11, LP_GPIO12 and IO MUX GPIO function. |+| 14 | GPIO13 | bidirectional | GPIO13 is powered by VDD_LP and provides touch channel TOUCH_CHANNEL12, LP_GPIO13 and IO MUX GPIO function. |+| 15 | GPIO14 | bidirectional | GPIO14 is powered by VDD_LP and its LP IO MUX function is LP_UART_TXD_PAD, with touch channel TOUCH_CHANNEL13 and LP_GPIO14 available. |+| 16 | GPIO15 | bidirectional | GPIO15 is powered by VDD_LP and its LP IO MUX function is LP_UART_RXD_PAD, with touch channel TOUCH_CHANNEL14 and LP_GPIO15 available. |+| 17 | GPIO16 | bidirectional | GPIO16 is powered by VDD_IO_0 and provides IO MUX GPIO function and analog ADC1_CHANNEL0. |+| 18 | GPIO17 | bidirectional | GPIO17 is powered by VDD_IO_0 and provides IO MUX GPIO function and analog ADC1_CHANNEL1. |+| 19 | GPIO18 | bidirectional | GPIO18 is powered by VDD_IO_0 and provides IO MUX GPIO function and analog ADC1_CHANNEL2. |+| 20 | GPIO19 | bidirectional | GPIO19 is powered by VDD_IO_0 and provides IO MUX GPIO function and analog ADC1_CHANNEL3. |+| 21 | VDD_IO_0 | power_in | Digital power domain supply for HP IOs; recommended input voltage is 1.65 V to 3.6 V (typ. 3.3 V). |+| 22 | GPIO20 | bidirectional | GPIO20 is powered by VDD_IO_0 and provides IO MUX GPIO function and analog ADC1_CHANNEL4. |+| 23 | GPIO21 | bidirectional | GPIO21 is powered by VDD_IO_0 and provides IO MUX GPIO function and analog ADC1_CHANNEL5. |+| 24 | GPIO22 | bidirectional | GPIO22 is powered by VDD_IO_0 and provides IO MUX GPIO function and analog ADC1_CHANNEL6. |+| 25 | GPIO23 | bidirectional | GPIO23 is powered by VDD_IO_0, provides IO MUX GPIO function with REF_50M_CLK_PAD (50 MHz reference clock output) and analog ADC1_CHANNEL7. |+| 26 | VDD_HP_0 | power_in | Digital power domain supply; recommended input voltage is 0.99 V to 1.3 V (typ. 1.1 V). |+| 27 | FLASH_CS | output | Dedicated off-package flash chip-select output, powered by VDD_FLASHIO. |+| 28 | FLASH_Q | bidirectional | Dedicated off-package flash data output (DO) pin, powered by VDD_FLASHIO. |+| 29 | FLASH_WP | bidirectional | Dedicated off-package flash write-protect (WP#) pin, powered by VDD_FLASHIO. |+| 30 | VDD_FLASHIO | power_in | Power supply for flash IO; the voltage should be adjusted according to the specific flash model, and the datasheet describes 3.3 V flash as the example. |+| 31 | FLASH_HOLD | bidirectional | Dedicated off-package flash HOLD# pin, powered by VDD_FLASHIO. |+| 32 | FLASH_CK | output | Dedicated off-package flash clock output, powered by VDD_FLASHIO. |+| 33 | FLASH_D | bidirectional | Dedicated off-package flash data input (DI) pin, powered by VDD_FLASHIO. |+| 34 | DSI_REXT | passive | MIPI DSI PHY external 4.02 kΩ reference resistor connection, powered by VDD_MIPI_DPHY. |+| 35 | DSI_DATAP1 | bidirectional | MIPI DSI PHY data positive channel 1, powered by VDD_MIPI_DPHY. |+| 36 | DSI_DATAN1 | bidirectional | MIPI DSI PHY data negative channel 1, powered by VDD_MIPI_DPHY. |+| 37 | DSI_CLKN | bidirectional | MIPI DSI PHY clock negative channel, powered by VDD_MIPI_DPHY. |+| 38 | DSI_CLKP | bidirectional | MIPI DSI PHY clock positive channel, powered by VDD_MIPI_DPHY. |+| 39 | DSI_DATAP0 | bidirectional | MIPI DSI PHY data positive channel 0, powered by VDD_MIPI_DPHY. |+| 40 | DSI_DATAN0 | bidirectional | MIPI DSI PHY data negative channel 0, powered by VDD_MIPI_DPHY. |+| 41 | VDD_MIPI_DPHY | power_in | MIPI PHY supply; recommended input voltage is 2.25 V to 2.75 V (typ. 2.5 V). |+| 42 | CSI_DATAN0 | bidirectional | MIPI CSI PHY data negative channel 0, powered by VDD_MIPI_DPHY. |+| 43 | CSI_DATAP0 | bidirectional | MIPI CSI PHY data positive channel 0, powered by VDD_MIPI_DPHY. |+| 44 | CSI_CLKP | bidirectional | MIPI CSI PHY clock positive channel, powered by VDD_MIPI_DPHY. |+| 45 | CSI_CLKN | bidirectional | MIPI CSI PHY clock negative channel, powered by VDD_MIPI_DPHY. |+| 46 | CSI_DATAN1 | bidirectional | MIPI CSI PHY data negative channel 1, powered by VDD_MIPI_DPHY. |+| 47 | CSI_DATAP1 | bidirectional | MIPI CSI PHY data positive channel 1, powered by VDD_MIPI_DPHY. |+| 48 | CSI_REXT | passive | MIPI CSI PHY external 4.02 kΩ reference resistor connection, powered by VDD_MIPI_DPHY. |+| 49 | USB_DM | bidirectional | USB 2.0 High-Speed OTG PHY D- (USB_D-) signal, powered by VDD_USBPHY. |+| 50 | USB_DP | bidirectional | USB 2.0 High-Speed OTG PHY D+ (USB_D+) signal, powered by VDD_USBPHY. |+| 51 | VDD_USBPHY | power_in | USB PHY supply; recommended input voltage is 2.97 V to 3.63 V (typ. 3.3 V). |+| 52 | GPIO24 | bidirectional | GPIO24 is powered by VDD_IO_4, has a default drive strength of 40 mA, and provides analog USB1P1_N0 as its USB full-speed D- function. |+| 53 | GPIO25 | bidirectional | GPIO25 is powered by VDD_IO_4 with USB pull-up enabled at reset, has a default drive strength of 40 mA, and provides analog USB1P1_P0 as its USB full-speed D+ function. |+| 54 | NC | unconnected | No-connect pin; the datasheet specifies no function for this pin. |+| 55 | GPIO26 | bidirectional | GPIO26 is powered by VDD_IO_4 and provides analog USB1P1_N1 as a USB full-speed D- function; USB pins are enabled for USB by default. |+| 56 | GPIO27 | bidirectional | GPIO27 is powered by VDD_IO_4 and provides analog USB1P1_P1 as a USB full-speed D+ function; USB pins are enabled for USB by default. |+| 57 | GPIO28 | bidirectional | GPIO28 is powered by VDD_IO_4 and its IO MUX functions are SPI2_CS_PAD (F2) and GMAC_PHY_RXDV_PAD (F3, RMII/MII receive data valid). |+| 58 | GPIO29 | bidirectional | GPIO29 is powered by VDD_IO_4 and its IO MUX functions are SPI2_D_PAD (F2) and GMAC_PHY_RXD0_PAD (F3, Ethernet receive data line 0). |+| 59 | VDD_PSRAM_0 | power_in | PSRAM IO supply; recommended input voltage is 1.65 V to 1.95 V (typ. 1.8 V). |+| 60 | GPIO30 | bidirectional | GPIO30 is powered by VDD_IO_4 and its IO MUX functions are SPI2_CK_PAD (F2) and GMAC_PHY_RXD1_PAD (F3, Ethernet receive data line 1). |+| 61 | GPIO31 | bidirectional | GPIO31 is powered by VDD_IO_4 and its IO MUX functions are SPI2_Q_PAD (F2) and GMAC_PHY_RXER_PAD (F3, Ethernet receive error). |+| 62 | VDD_IO_4 | power_in | Digital power domain supply for HP IOs; recommended input voltage is 1.65 V to 3.6 V (typ. 3.3 V). |+| 63 | GPIO32 | bidirectional | GPIO32 is powered by VDD_IO_4 with input enabled at reset, and its IO MUX functions are SPI2_HOLD_PAD (F2) and GMAC_RMII_CLK_PAD (F3). |+| 64 | GPIO33 | bidirectional | GPIO33 is powered by VDD_IO_4 with input enabled at reset, and its IO MUX functions are SPI2_WP_PAD (F2) and GMAC_PHY_TXEN_PAD (F3, Ethernet transmit enable). |+| 65 | GPIO34 | bidirectional | GPIO34 is powered by VDD_IO_4 with input enabled at reset and is a strapping pin that selects the JTAG signal source (floating by default); its IO MUX functions are SPI2_IO4_PAD (F2) and GMAC_PHY_TXD0_PAD (F3). |+| 66 | GPIO35 | bidirectional | GPIO35 is powered by VDD_IO_4 with input enabled and weak pull-up enabled at reset, and is a chip boot mode strapping pin (weak pull-up, bit value 1 by default); its IO MUX functions are SPI2_IO5_PAD (F2) and GMAC_PHY_TXD1_PAD (F3). |+| 67 | VDD_PSRAM_1 | power_in | PSRAM IO supply; recommended input voltage is 1.65 V to 1.95 V (typ. 1.8 V). |+| 68 | GPIO36 | bidirectional | GPIO36 is powered by VDD_IO_4 with input enabled at reset and is a strapping pin for ROM message printing (floating by default); its IO MUX functions are SPI2_IO6_PAD (F2) and GMAC_PHY_TXER_PAD (F3). |+| 69 | GPIO37 | bidirectional | GPIO37 is powered by VDD_IO_4 and is a chip boot mode strapping pin; its IO MUX functions are UART0_TXD_PAD (F0) and SPI2_IO7_PAD (F2). |+| 70 | GPIO38 | bidirectional | GPIO38 is powered by VDD_IO_4 with input enabled at reset and is a chip boot mode strapping pin; its IO MUX functions are UART0_RXD_PAD (F0) and SPI2_DQS_PAD (F2). |+| 71 | VDDO_FLASH | power_out | Regulated output rail for off-package flash, supplying up to 50 mA at maximum. |+| 72 | VDDO_PSRAM | power_out | Regulated output rail for in-package and off-package PSRAM, supplying up to 50 mA at maximum. |+| 73 | VDDO_3 | power_out | Regulated output rail, supplying up to 50 mA at maximum. |+| 74 | VDDO_4 | power_out | Regulated output rail, supplying up to 50 mA at maximum. |+| 75 | VDD_LDO | power_in | Analog power domain supply for the LDOs; recommended input voltage is 3.0 V to 3.6 V (typ. 3.3 V). |+| 76 | VDD_HP_2 | power_in | Digital power domain supply; recommended input voltage is 0.99 V to 1.3 V (typ. 1.1 V). |+| 77 | VDD_DCDCC | power_in | Analog power domain supply for DC/DC control; recommended input voltage is 3.0 V to 3.6 V (typ. 3.3 V). |+| 78 | FB_DCDC | passive | Feedback pin of the external DC/DC power supply, which regulates VDD_HP_0/2/3 together with feedback resistors. |+| 79 | EN_DCDC | output | Enable pin of the external DC/DC converter. |+| 80 | GPIO39 | bidirectional | GPIO39 is powered by VDD_IO_5 and its IO MUX functions are SD1_CDATA0_PAD (F0) and REF_50M_CLK_PAD (F3, 50 MHz reference clock output). |+| 81 | GPIO40 | bidirectional | GPIO40 is powered by VDD_IO_5 and its IO MUX functions are SD1_CDATA1_PAD (F0) and GMAC_PHY_TXEN_PAD (F3). |+| 82 | GPIO41 | bidirectional | GPIO41 is powered by VDD_IO_5 and its IO MUX functions are SD1_CDATA2_PAD (F0) and GMAC_PHY_TXD0_PAD (F3). |+| 83 | GPIO42 | bidirectional | GPIO42 is powered by VDD_IO_5 and its IO MUX functions are SD1_CDATA3_PAD (F0) and GMAC_PHY_TXD1_PAD (F3). |+| 84 | GPIO43 | bidirectional | GPIO43 is powered by VDD_IO_5 and its IO MUX functions are SD1_CCLK_PAD (F0) and GMAC_PHY_TXER_PAD (F3). |+| 85 | VDD_IO_5 | power_in | Digital power domain supply for HP IOs; recommended input voltage is 1.65 V to 3.6 V (typ. 3.3 V). |+| 86 | GPIO44 | bidirectional | GPIO44 is powered by VDD_IO_5 and its IO MUX functions are SD1_CCMD_PAD (F0) and GMAC_RMII_CLK_PAD (F3). |+| 87 | GPIO45 | bidirectional | GPIO45 is powered by VDD_IO_5 and its IO MUX functions are SD1_CDATA4_PAD (F0) and GMAC_PHY_RXDV_PAD (F3). |+| 88 | GPIO46 | bidirectional | GPIO46 is powered by VDD_IO_5 and its IO MUX functions are SD1_CDATA5_PAD (F0) and GMAC_PHY_RXD0_PAD (F3). |+| 89 | GPIO47 | bidirectional | GPIO47 is powered by VDD_IO_5 and its IO MUX functions are SD1_CDATA6_PAD (F0) and GMAC_PHY_RXD1_PAD (F3). |+| 90 | GPIO48 | bidirectional | GPIO48 is powered by VDD_IO_5 and its IO MUX functions are SD1_CDATA7_PAD (F0) and GMAC_PHY_RXER_PAD (F3). |+| 91 | VDD_HP_3 | power_in | Digital power domain supply; recommended input voltage is 0.99 V to 1.3 V (typ. 1.1 V). |+| 92 | GPIO49 | bidirectional | GPIO49 is powered by VDD_IO_6 and provides analog ADC2_CHANNEL0 and IO MUX GMAC_PHY_TXEN_PAD (F3). |+| 93 | GPIO50 | bidirectional | GPIO50 is powered by VDD_IO_6 and provides analog ADC2_CHANNEL1 and IO MUX GMAC_RMII_CLK_PAD (F3). |+| 94 | GPIO51 | bidirectional | GPIO51 is powered by VDD_IO_6 and provides analog ADC2_CHANNEL2 and ANA_COMP0, and IO MUX GMAC_PHY_RXDV_PAD (F3). |+| 95 | GPIO52 | bidirectional | GPIO52 is powered by VDD_IO_6 and provides analog ADC2_CHANNEL3 and ANA_COMP0, and IO MUX GMAC_PHY_RXD0_PAD (F3). |+| 96 | VDD_IO_6 | power_in | Digital power domain supply for HP IOs; recommended input voltage is 1.65 V to 3.6 V (typ. 3.3 V). |+| 97 | GPIO53 | bidirectional | GPIO53 is powered by VDD_IO_6 and provides analog ADC2_CHANNEL4 and ANA_COMP1, and IO MUX GMAC_PHY_RXD1_PAD (F3). |+| 98 | GPIO54 | bidirectional | GPIO54 is powered by VDD_IO_6 and provides analog ADC2_CHANNEL5 and ANA_COMP1, and IO MUX GMAC_PHY_RXER_PAD (F3). |+| 99 | XTAL_N | passive | Differential negative external clock input/output connected to the chip's crystal or oscillator. |+| 100 | XTAL_P | passive | Differential positive external clock input/output connected to the chip's crystal or oscillator. |+| 101 | VDD_ANA | power_in | Analog power domain supply; recommended input voltage is 3.0 V to 3.6 V (typ. 3.3 V). |+| 102 | VDD_BAT | power_in | Analog power domain supply that can optionally connect to an external battery; recommended input voltage is 2.5 V to 3.6 V (typ. 3.3 V). |+| 103 | CHIP_PU | input | Chip enable: high enables the chip (powered up), low disables it (powered down), and the pin must not be left floating. |+| 104 | GPIO0 | bidirectional | GPIO0 is powered by VDD_LP/VDD_BAT, provides IO MUX GPIO function, LP_GPIO0 and analog XTAL_32K_N. |+| 105 | GND | power_in | External ground connection (exposed pad). |  ## Key specifications @@ -146,27 +150,20 @@ Limits as printed in the datasheet (page.json `metadata.characteristics` carries | Recommended input voltage (VDD_USBPHY) |  | 2.97 | 3.3 | 3.63 | V |  | 79 | | Current supplied to core | IVDD | 0.5 |  |  | A |  | 79 | | Ambient temperature | TA | -40 |  | 85 | °C |  | 79 |-| Low-level input voltage | VIL | -0.3 |  |  | V |  | 80 |+| Low-level input voltage | VIL | -0.3 |  |  | V | VDD = voltage of VDD_IO_0/4/5/6 (footnote 1) | 80 | | High-level input current | IIH |  |  | 50 | nA |  | 80 | | Low-level input current | IIL |  |  | 50 | nA |  | 80 |-| Chip reset voltage (low level) | VIL_nRST | -0.3 |  |  | V | Chip reset voltage (CHIP_PU voltage is within the specified range) | 80 |-| Pin capacitance | CIN |  | 2 |  | pF |  | 80 |-| High-level source current | IOH |  | 40 |  | mA | VDD = 3.3 V, VOH >= 2.64 V, PAD_DRIVER = 3 | 80 |-| Low-level sink current | IOL |  | 28 |  | mA | VDD = 3.3 V, VOL = 0.495 V, PAD_DRIVER = 3 | 80 |-| Internal weak pull-up resistor | RPU |  | 45 |  | kΩ |  | 80 |-| Internal weak pull-down resistor | RPD |  | 45 |  | kΩ |  | 80 |+| Chip reset voltage (CHIP_PU voltage is within the specified range) | VIL_nRST | -0.3 |  |  | V | CHIP_PU voltage is within the specified range | 80 | | Differential nonlinearity (DNL) | DNL | -1 |  | 3 | LSB |  | 81 | | Integral nonlinearity (INL) | INL | -5 |  | 3 | LSB |  | 81 | | Sampling rate |  |  |  | 100 | kSPS |  | 81 |-| Total error (ATTEN0) |  | -12 |  | 12 | mV | ATTEN0, effective measurement range of 0-1000 | 81 |-| Total error (ATTEN1) |  | -12 |  | 12 | mV | ATTEN1, effective measurement range of 0-1300 | 81 |-| Total error (ATTEN2) |  | -12 |  | 12 | mV | ATTEN2, effective measurement range of 0-1900 | 81 |-| Total error (ATTEN3) |  | -15 |  | 15 | mV | ATTEN3, effective measurement range of 0-3300 | 81 |+| Total error, ATTEN0 |  | -12 |  | 12 | mV | effective measurement range of 0-1000 | 81 |+| Total error, ATTEN1 |  | -12 |  | 12 | mV | effective measurement range of 0-1300 | 81 |+| Total error, ATTEN2 |  | -12 |  | 12 | mV | effective measurement range of 0-1900 | 81 |+| Total error, ATTEN3 |  | -15 |  | 15 | mV | effective measurement range of 0-3300 | 81 | | Power supply voltage (1.8 V) | VCC | 1.62 | 1.8 | 1.98 | V |  | 82 | | Power supply voltage (3.3 V) | VCC | 2.7 | 3.3 | 3.6 | V |  | 82 |-| Maximum clock frequency | FC | 80 |  |  | MHz |  | 82 |-| VDDO_FLASH powered by VDD_LDO via RVFB for 3.3 V flash | RVFB |  | 3 |  | Ω |  | 80 |-| Output current when VDDO_FLASH is powered by Flash Voltage Regulator for 1.8 V flash | IVFB |  | 50 |  | mA |  | 80 |+| Maximum clock frequency (PSRAM) | FC | 80 |  |  | MHz |  | 82 |  ## CAD (KiCad official)
esp32-p4nrw32-hero.overlay.json+2489−2487
@@ -1,2489 +1,2491 @@ {-  "spec": "adom-hero 1.4",-  "mpn": "ESP32-P4NRW32",-  "kind": "component + footprint reference art",-  "board_use": false,-  "plane_z_mm": -0.02,-  "units": "metre",-  "upAxis": "Z",-  "layers": {-    "pad_outlines": {-      "material": "Footprint pads - teal dashed outlines - 50 percent opacity",-      "rgba": [-        0.0,-        0.902,-        0.863,-        0.5-      ],-      "pads": 113,-      "span_mm": 11.85,-      "dash_mm": 0.2962,-      "gap_mm": 0.1778,-      "pad_stroke_mm": 0.0711-    },-    "silkscreen": {-      "material": "Silkscreen reference lines - 30 percent opacity",-      "rgba": [-        0.92,-        0.96,-        1.0,-        0.3-      ],-      "footprint_items": 8,-      "pin1": {-        "source": "footprint silkscreen",-        "pad": "1"-      }-    },-    "signal_names": {-      "material": "Signal names - 50 percent opacity",-      "rgba": [-        0.92,-        0.96,-        1.0,-        0.5-      ],-      "font": "DejaVu Sans Mono",-      "labels": 104,-      "sides": "top + mirrored underside (single-sided)",-      "fallback_to_pad_number": 0-    }-  },-  "align": {-    "ok": true,-    "centre_offset_mm": 0.0,-    "tolerance_mm": 0.832,-    "orientation_flipped": false,-    "contacts_bbox_mm": [-      -5.01,-      5.01,-      -5.01,-      5.01-    ],-    "pads_bbox_mm": [-      -5.2,-      5.2,-      -5.2,-      5.2-    ],-    "seating_z_mm": -0.0-  },-  "sources": {-    "glb": "esp32-p4nrw32-etched.glb",-    "glb_sha256": "be801779594464b29391c2919f88980fb6a6599188c44490225fcbaf5cf4fadb",-    "footprint": "esp32-p4nrw32.kicad_mod",-    "footprint_sha256": "24a69f53f57c82ef3e7e549692c28fd61d248e88812c1cc15dc19b25e09fbcf4",-    "pins": "page.json component.pins",-    "pins_sha256": "0977d8915396c03cdccb4089e16d0e824d516a6754403b5e53cf1c0b41d6df89"-  },-  "generator": "adom-wiki 1.8.0 (component_hero)",-  "labels": [-    {-      "pad": "1",-      "text": "GPIO1",-      "x": -5.3,-      "y": -4.375,-      "align": "right",-      "vertical": false,-      "h": 0.175-    },-    {-      "pad": "2",-      "text": "GPIO2",-      "x": -5.3,-      "y": -4.025,-      "align": "right",-      "vertical": false,-      "h": 0.175-    },-    {-      "pad": "3",-      "text": "GPIO3",-      "x": -5.3,-      "y": -3.675,-      "align": "right",-      "vertical": false,-      "h": 0.175-    },-    {-      "pad": "4",-      "text": "GPIO4",-      "x": -5.3,-      "y": -3.325,-      "align": "right",-      "vertical": false,-      "h": 0.175-    },-    {-      "pad": "5",-      "text": "GPIO5",-      "x": -5.3,-      "y": -2.975,-      "align": "right",-      "vertical": false,-      "h": 0.175-    },-    {-      "pad": "6",-      "text": "GPIO6",-      "x": -5.3,-      "y": -2.625,-      "align": "right",-      "vertical": false,-      "h": 0.175-    },-    {-      "pad": "7",-      "text": "GPIO7",-      "x": -5.3,-      "y": -2.275,-      "align": "right",-      "vertical": false,-      "h": 0.175-    },-    {-      "pad": "8",-      "text": "GPIO8",-      "x": -5.3,-      "y": -1.925,-      "align": "right",-      "vertical": false,-      "h": 0.175-    },-    {-      "pad": "9",-      "text": "VDD_LP",-      "x": -5.3,-      "y": -1.575,-      "align": "right",-      "vertical": false,-      "h": 0.175-    },-    {-      "pad": "10",-      "text": "GPIO9",-      "x": -5.3,-      "y": -1.225,-      "align": "right",-      "vertical": false,-      "h": 0.175-    },-    {-      "pad": "11",-      "text": "GPIO10",-      "x": -5.3,-      "y": -0.875,-      "align": "right",-      "vertical": false,-      "h": 0.175-    },-    {-      "pad": "12",-      "text": "GPIO11",-      "x": -5.3,-      "y": -0.525,-      "align": "right",-      "vertical": false,-      "h": 0.175-    },-    {-      "pad": "13",-      "text": "GPIO12",-      "x": -5.3,-      "y": -0.175,-      "align": "right",-      "vertical": false,-      "h": 0.175-    },-    {-      "pad": "14",-      "text": "GPIO13",-      "x": -5.3,-      "y": 0.175,-      "align": "right",-      "vertical": false,-      "h": 0.175-    },-    {-      "pad": "15",-      "text": "GPIO14",-      "x": -5.3,-      "y": 0.525,-      "align": "right",-      "vertical": false,-      "h": 0.175-    },-    {-      "pad": "16",-      "text": "GPIO15",-      "x": -5.3,-      "y": 0.875,-      "align": "right",-      "vertical": false,-      "h": 0.175-    },-    {-      "pad": "17",-      "text": "GPIO16",-      "x": -5.3,-      "y": 1.225,-      "align": "right",-      "vertical": false,-      "h": 0.175-    },-    {-      "pad": "18",-      "text": "GPIO17",-      "x": -5.3,-      "y": 1.575,-      "align": "right",-      "vertical": false,-      "h": 0.175-    },-    {-      "pad": "19",-      "text": "GPIO18",-      "x": -5.3,-      "y": 1.925,-      "align": "right",-      "vertical": false,-      "h": 0.175-    },-    {-      "pad": "20",-      "text": "GPIO19",-      "x": -5.3,-      "y": 2.275,-      "align": "right",-      "vertical": false,-      "h": 0.175-    },-    {-      "pad": "21",-      "text": "VDD_IO_0",-      "x": -5.3,-      "y": 2.625,-      "align": "right",-      "vertical": false,-      "h": 0.175-    },-    {-      "pad": "22",-      "text": "GPIO20",-      "x": -5.3,-      "y": 2.975,-      "align": "right",-      "vertical": false,-      "h": 0.175-    },-    {-      "pad": "23",-      "text": "GPIO21",-      "x": -5.3,-      "y": 3.325,-      "align": "right",-      "vertical": false,-      "h": 0.175-    },-    {-      "pad": "24",-      "text": "GPIO22",-      "x": -5.3,-      "y": 3.675,-      "align": "right",-      "vertical": false,-      "h": 0.175-    },-    {-      "pad": "25",-      "text": "GPIO23",-      "x": -5.3,-      "y": 4.025,-      "align": "right",-      "vertical": false,-      "h": 0.175-    },-    {-      "pad": "26",-      "text": "VDD_HP_0",-      "x": -5.3,-      "y": 4.375,-      "align": "right",-      "vertical": false,-      "h": 0.175-    },-    {-      "pad": "27",-      "text": "FLASH_CS",-      "x": -4.375,-      "y": 5.3,-      "align": "right",-      "vertical": true,-      "h": 0.175-    },-    {-      "pad": "28",-      "text": "FLASH_Q",-      "x": -4.025,-      "y": 5.3,-      "align": "right",-      "vertical": true,-      "h": 0.175-    },-    {-      "pad": "29",-      "text": "FLASH_WP",-      "x": -3.675,-      "y": 5.3,-      "align": "right",-      "vertical": true,-      "h": 0.175-    },-    {-      "pad": "30",-      "text": "VDD_FLASHIO",-      "x": -3.325,-      "y": 5.3,-      "align": "right",-      "vertical": true,-      "h": 0.175-    },-    {-      "pad": "31",-      "text": "FLASH_HOLD",-      "x": -2.975,-      "y": 5.3,-      "align": "right",-      "vertical": true,-      "h": 0.175-    },-    {-      "pad": "32",-      "text": "FLASH_CK",-      "x": -2.625,-      "y": 5.3,-      "align": "right",-      "vertical": true,-      "h": 0.175-    },-    {-      "pad": "33",-      "text": "FLASH_D",-      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esp32-p4nrw32.step+1−1
@@ -1,7 +1,7 @@ ISO-10303-21; HEADER; FILE_DESCRIPTION(('Open CASCADE Model'),'2;1');-FILE_NAME('Open CASCADE Shape Model','2026-10-28T19:12:50',('Author'),(+FILE_NAME('Open CASCADE Shape Model','2026-10-28T19:26:46',('Author'),(     'Open CASCADE'),'Open CASCADE STEP processor 7.9','Open CASCADE 7.9'   ,'Unknown'); FILE_SCHEMA(('AUTOMOTIVE_DESIGN { 1 0 10303 214 1 1 1 1 }'));
package.json+115−116
@@ -1,8 +1,8 @@ {   "slug": "esp32-p4nrw32",-  "version": "0.1.2",+  "version": "0.1.3",   "type": "component",-  "description": "ESPRESSIF Functional Modules, QFN-104(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+  "description": "ESPRESSIF Functional Modules, QFN-104(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D. Chip revision v1.x; ESP32-P4NRW32X is the newer revision (v3.x).",   "tags": [     "component",     "functional modules",@@ -52,7 +52,7 @@       "lcsc": "C22387510"     },     "distributor_check": {-      "checked_at": "2026-10-28T19:13:05Z",+      "checked_at": "2026-10-28T19:26:59Z",       "source": "Component Ocean /api/assign-pns",       "digikey": {         "pn": null,@@ -68,631 +68,631 @@         "number": "1",         "name": "GPIO1",         "type": "bidirectional",-        "description": "GPIO1 is a general-purpose IO powered from VDD_LP/VDD_BAT that also carries the XTAL_32K_P analog function and LP_GPIO1 in Deep-sleep mode, with default drive strength 20 mA."+        "description": "GPIO1 is powered by VDD_LP/VDD_BAT, has no pin setting at reset, and offers IO MUX GPIO1, LP IO MUX LP_GPIO1 and analog XTAL_32K_P functions."       },       {         "number": "2",         "name": "GPIO2",         "type": "bidirectional",-        "description": "GPIO2 is an LP IO powered from VDD_LP/VDD_BAT that carries the MTCK JTAG clock, TOUCH_CHANNEL1 and LP_GPIO2, and is input-enabled with weak pull-up at reset (EFUSE_DIS_PAD_JTAG dependent)."+        "description": "GPIO2 is powered by VDD_LP/VDD_BAT with input enabled and weak pull-up enabled at reset, and its IO MUX F0 function is MTCK (JTAG test clock) with touch channel TOUCH_CHANNEL1."       },       {         "number": "3",         "name": "GPIO3",         "type": "bidirectional",-        "description": "GPIO3 is an LP IO powered from VDD_LP/VDD_BAT that carries the MTDI JTAG input, TOUCH_CHANNEL2 and LP_GPIO3, and is input-enabled at reset."+        "description": "GPIO3 is powered by VDD_LP/VDD_BAT with input enabled at reset, and its IO MUX F0 function is MTDI (JTAG test data in) with touch channel TOUCH_CHANNEL2."       },       {         "number": "4",         "name": "GPIO4",         "type": "bidirectional",-        "description": "GPIO4 is an LP IO powered from VDD_LP that carries the MTMS JTAG input, TOUCH_CHANNEL3 and LP_GPIO4, and is input-enabled at reset."+        "description": "GPIO4 is powered by VDD_LP with input enabled at reset, and its IO MUX F0 function is MTMS (JTAG test mode select) with touch channel TOUCH_CHANNEL3."       },       {         "number": "5",         "name": "GPIO5",         "type": "bidirectional",-        "description": "GPIO5 is an LP IO powered from VDD_LP that carries the MTDO JTAG output (tri-state capable), TOUCH_CHANNEL4 and LP_GPIO5."+        "description": "GPIO5 is powered by VDD_LP, and its IO MUX F0 function is MTDO (JTAG test data out) with touch channel TOUCH_CHANNEL4."       },       {         "number": "6",         "name": "GPIO6",         "type": "bidirectional",-        "description": "GPIO6 is an LP IO powered from VDD_LP that carries the SPI2_HOLD_PAD (8-line/4-line SPI2 interface), TOUCH_CHANNEL5 and LP_GPIO6."+        "description": "GPIO6 is powered by VDD_LP and its IO MUX F2 function is SPI2_HOLD_PAD, with touch channel TOUCH_CHANNEL5 and LP_GPIO6 available."       },       {         "number": "7",         "name": "GPIO7",         "type": "bidirectional",-        "description": "GPIO7 is an LP IO powered from VDD_LP that carries the SPI2_CS_PAD chip select, TOUCH_CHANNEL6 and LP_GPIO7."+        "description": "GPIO7 is powered by VDD_LP and its IO MUX F2 function is SPI2_CS_PAD, with touch channel TOUCH_CHANNEL6 and LP_GPIO7 available."       },       {         "number": "8",         "name": "GPIO8",         "type": "bidirectional",-        "description": "GPIO8 is an LP IO powered from VDD_LP that carries the SPI2_D_PAD data input, TOUCH_CHANNEL7 and LP_GPIO8."+        "description": "GPIO8 is powered by VDD_LP and its IO MUX F2 function is SPI2_D_PAD, with touch channel TOUCH_CHANNEL7 and LP_GPIO8 available."       },       {         "number": "9",         "name": "VDD_LP",         "type": "power_in",-        "description": "VDD_LP is the LP power domain supply, recommended at 3.0 V to 3.6 V (typ. 3.3 V)."+        "description": "LP power domain supply; recommended input voltage is 3.0 V to 3.6 V (typ. 3.3 V)."       },       {         "number": "10",         "name": "GPIO9",         "type": "bidirectional",-        "description": "GPIO9 is an LP IO powered from VDD_LP that carries the SPI2_CK_PAD clock, TOUCH_CHANNEL8 and LP_GPIO9."+        "description": "GPIO9 is powered by VDD_LP and its IO MUX F2 function is SPI2_CK_PAD, with touch channel TOUCH_CHANNEL8 and LP_GPIO9 available."       },       {         "number": "11",         "name": "GPIO10",         "type": "bidirectional",-        "description": "GPIO10 is an LP IO powered from VDD_LP that carries the SPI2_Q_PAD data output, TOUCH_CHANNEL9 and LP_GPIO10."+        "description": "GPIO10 is powered by VDD_LP and its IO MUX F2 function is SPI2_Q_PAD, with touch channel TOUCH_CHANNEL9 and LP_GPIO10 available."       },       {         "number": "12",         "name": "GPIO11",         "type": "bidirectional",-        "description": "GPIO11 is an LP IO powered from VDD_LP that carries the SPI2_WP_PAD write protect, TOUCH_CHANNEL10 and LP_GPIO11."+        "description": "GPIO11 is powered by VDD_LP and its IO MUX F2 function is SPI2_WP_PAD, with touch channel TOUCH_CHANNEL10 and LP_GPIO11 available."       },       {         "number": "13",         "name": "GPIO12",         "type": "bidirectional",-        "description": "GPIO12 is an LP IO powered from VDD_LP that carries TOUCH_CHANNEL11 and LP_GPIO12."+        "description": "GPIO12 is powered by VDD_LP and provides touch channel TOUCH_CHANNEL11, LP_GPIO12 and IO MUX GPIO function."       },       {         "number": "14",         "name": "GPIO13",         "type": "bidirectional",-        "description": "GPIO13 is an LP IO powered from VDD_LP that carries TOUCH_CHANNEL12 and LP_GPIO13."+        "description": "GPIO13 is powered by VDD_LP and provides touch channel TOUCH_CHANNEL12, LP_GPIO13 and IO MUX GPIO function."       },       {         "number": "15",         "name": "GPIO14",         "type": "bidirectional",-        "description": "GPIO14 is an LP IO powered from VDD_LP that carries the LP_UART_TXD_PAD transmit output, TOUCH_CHANNEL13 and LP_GPIO14."+        "description": "GPIO14 is powered by VDD_LP and its LP IO MUX function is LP_UART_TXD_PAD, with touch channel TOUCH_CHANNEL13 and LP_GPIO14 available."       },       {         "number": "16",         "name": "GPIO15",         "type": "bidirectional",-        "description": "GPIO15 is an LP IO powered from VDD_LP that carries the LP_UART_RXD_PAD receive input, TOUCH_CHANNEL14 and LP_GPIO15."+        "description": "GPIO15 is powered by VDD_LP and its LP IO MUX function is LP_UART_RXD_PAD, with touch channel TOUCH_CHANNEL14 and LP_GPIO15 available."       },       {         "number": "17",         "name": "GPIO16",         "type": "bidirectional",-        "description": "GPIO16 is an HP IO powered from VDD_IO_0 (1.65 V to 3.6 V) that carries the ADC1_CHANNEL0 analog input."+        "description": "GPIO16 is powered by VDD_IO_0 and provides IO MUX GPIO function and analog ADC1_CHANNEL0."       },       {         "number": "18",         "name": "GPIO17",         "type": "bidirectional",-        "description": "GPIO17 is an HP IO powered from VDD_IO_0 (1.65 V to 3.6 V) that carries the ADC1_CHANNEL1 analog input."+        "description": "GPIO17 is powered by VDD_IO_0 and provides IO MUX GPIO function and analog ADC1_CHANNEL1."       },       {         "number": "19",         "name": "GPIO18",         "type": "bidirectional",-        "description": "GPIO18 is an HP IO powered from VDD_IO_0 (1.65 V to 3.6 V) that carries the ADC1_CHANNEL2 analog input."+        "description": "GPIO18 is powered by VDD_IO_0 and provides IO MUX GPIO function and analog ADC1_CHANNEL2."       },       {         "number": "20",         "name": "GPIO19",         "type": "bidirectional",-        "description": "GPIO19 is an HP IO powered from VDD_IO_0 (1.65 V to 3.6 V) that carries the ADC1_CHANNEL3 analog input."+        "description": "GPIO19 is powered by VDD_IO_0 and provides IO MUX GPIO function and analog ADC1_CHANNEL3."       },       {         "number": "21",         "name": "VDD_IO_0",         "type": "power_in",-        "description": "VDD_IO_0 is the digital IO power supply for the HP IO group, recommended at 1.65 V to 3.6 V (typ. 3.3 V)."+        "description": "Digital power domain supply for HP IOs; recommended input voltage is 1.65 V to 3.6 V (typ. 3.3 V)."       },       {         "number": "22",         "name": "GPIO20",         "type": "bidirectional",-        "description": "GPIO20 is an HP IO powered from VDD_IO_0 (1.65 V to 3.6 V) that carries the ADC1_CHANNEL4 analog input."+        "description": "GPIO20 is powered by VDD_IO_0 and provides IO MUX GPIO function and analog ADC1_CHANNEL4."       },       {         "number": "23",         "name": "GPIO21",         "type": "bidirectional",-        "description": "GPIO21 is an HP IO powered from VDD_IO_0 (1.65 V to 3.6 V) that carries the ADC1_CHANNEL5 analog input."+        "description": "GPIO21 is powered by VDD_IO_0 and provides IO MUX GPIO function and analog ADC1_CHANNEL5."       },       {         "number": "24",         "name": "GPIO22",         "type": "bidirectional",-        "description": "GPIO22 is an HP IO powered from VDD_IO_0 (1.65 V to 3.6 V) that carries the ADC1_CHANNEL6 analog input."+        "description": "GPIO22 is powered by VDD_IO_0 and provides IO MUX GPIO function and analog ADC1_CHANNEL6."       },       {         "number": "25",         "name": "GPIO23",         "type": "bidirectional",-        "description": "GPIO23 is an HP IO powered from VDD_IO_0 (1.65 V to 3.6 V) that carries the ADC1_CHANNEL7 analog input and the REF_50M_CLK_PAD 50 MHz reference clock output."+        "description": "GPIO23 is powered by VDD_IO_0, provides IO MUX GPIO function with REF_50M_CLK_PAD (50 MHz reference clock output) and analog ADC1_CHANNEL7."       },       {         "number": "26",         "name": "VDD_HP_0",         "type": "power_in",-        "description": "VDD_HP_0 is the digital core supply, recommended at 0.99 V to 1.3 V (typ. 1.1 V); the chip can adjust it automatically."+        "description": "Digital power domain supply; recommended input voltage is 0.99 V to 1.3 V (typ. 1.1 V)."       },       {         "number": "27",         "name": "FLASH_CS",         "type": "output",-        "description": "FLASH_CS is the dedicated off-package flash chip-select output, powered by VDD_FLASHIO."+        "description": "Dedicated off-package flash chip-select output, powered by VDD_FLASHIO."       },       {         "number": "28",         "name": "FLASH_Q",         "type": "bidirectional",-        "description": "FLASH_Q is the dedicated flash data-output line (DO) powered by VDD_FLASHIO."+        "description": "Dedicated off-package flash data output (DO) pin, powered by VDD_FLASHIO."       },       {         "number": "29",         "name": "FLASH_WP",         "type": "bidirectional",-        "description": "FLASH_WP is the dedicated flash write-protect line (WP#) powered by VDD_FLASHIO."+        "description": "Dedicated off-package flash write-protect (WP#) pin, powered by VDD_FLASHIO."       },       {         "number": "30",         "name": "VDD_FLASHIO",         "type": "power_in",-        "description": "VDD_FLASHIO powers the flash IO and should be set according to the flash model; the datasheet uses 3.3 V flash as the example, with recommended input 1.65 V to 3.6 V."+        "description": "Power supply for flash IO; the voltage should be adjusted according to the specific flash model, and the datasheet describes 3.3 V flash as the example."       },       {         "number": "31",         "name": "FLASH_HOLD",         "type": "bidirectional",-        "description": "FLASH_HOLD is the dedicated flash hold line (HOLD#) powered by VDD_FLASHIO."+        "description": "Dedicated off-package flash HOLD# pin, powered by VDD_FLASHIO."       },       {         "number": "32",         "name": "FLASH_CK",         "type": "output",-        "description": "FLASH_CK is the dedicated flash clock output (CLK) powered by VDD_FLASHIO."+        "description": "Dedicated off-package flash clock output, powered by VDD_FLASHIO."       },       {         "number": "33",         "name": "FLASH_D",         "type": "bidirectional",-        "description": "FLASH_D is the dedicated flash data-input line (DI) powered by VDD_FLASHIO."+        "description": "Dedicated off-package flash data input (DI) pin, powered by VDD_FLASHIO."       },       {         "number": "34",         "name": "DSI_REXT",-        "type": "bidirectional",-        "description": "DSI_REXT is the MIPI DSI PHY pin for the 4.02 kΩ external reference resistor, powered by VDD_MIPI_DPHY."+        "type": "passive",+        "description": "MIPI DSI PHY external 4.02 kΩ reference resistor connection, powered by VDD_MIPI_DPHY."       },       {         "number": "35",         "name": "DSI_DATAP1",         "type": "bidirectional",-        "description": "DSI_DATAP1 is the positive data channel 1 of the MIPI DSI PHY (2-lane, 1.5 Gbps per lane), powered by VDD_MIPI_DPHY."+        "description": "MIPI DSI PHY data positive channel 1, powered by VDD_MIPI_DPHY."       },       {         "number": "36",         "name": "DSI_DATAN1",         "type": "bidirectional",-        "description": "DSI_DATAN1 is the negative data channel 1 of the MIPI DSI PHY, powered by VDD_MIPI_DPHY."+        "description": "MIPI DSI PHY data negative channel 1, powered by VDD_MIPI_DPHY."       },       {         "number": "37",         "name": "DSI_CLKN",         "type": "bidirectional",-        "description": "DSI_CLKN is the negative clock channel of the MIPI DSI PHY, powered by VDD_MIPI_DPHY."+        "description": "MIPI DSI PHY clock negative channel, powered by VDD_MIPI_DPHY."       },       {         "number": "38",         "name": "DSI_CLKP",         "type": "bidirectional",-        "description": "DSI_CLKP is the positive clock channel of the MIPI DSI PHY, powered by VDD_MIPI_DPHY."+        "description": "MIPI DSI PHY clock positive channel, powered by VDD_MIPI_DPHY."       },       {         "number": "39",         "name": "DSI_DATAP0",         "type": "bidirectional",-        "description": "DSI_DATAP0 is the positive data channel 0 of the MIPI DSI PHY, powered by VDD_MIPI_DPHY."+        "description": "MIPI DSI PHY data positive channel 0, powered by VDD_MIPI_DPHY."       },       {         "number": "40",         "name": "DSI_DATAN0",         "type": "bidirectional",-        "description": "DSI_DATAN0 is the negative data channel 0 of the MIPI DSI PHY, powered by VDD_MIPI_DPHY."+        "description": "MIPI DSI PHY data negative channel 0, powered by VDD_MIPI_DPHY."       },       {         "number": "41",         "name": "VDD_MIPI_DPHY",         "type": "power_in",-        "description": "VDD_MIPI_DPHY is the MIPI PHY supply, recommended at 2.25 V to 2.75 V (typ. 2.5 V) with an absolute maximum of 2.75 V."+        "description": "MIPI PHY supply; recommended input voltage is 2.25 V to 2.75 V (typ. 2.5 V)."       },       {         "number": "42",         "name": "CSI_DATAN0",         "type": "bidirectional",-        "description": "CSI_DATAN0 is the negative data channel 0 of the MIPI CSI PHY, powered by VDD_MIPI_DPHY."+        "description": "MIPI CSI PHY data negative channel 0, powered by VDD_MIPI_DPHY."       },       {         "number": "43",         "name": "CSI_DATAP0",         "type": "bidirectional",-        "description": "CSI_DATAP0 is the positive data channel 0 of the MIPI CSI PHY, powered by VDD_MIPI_DPHY."+        "description": "MIPI CSI PHY data positive channel 0, powered by VDD_MIPI_DPHY."       },       {         "number": "44",         "name": "CSI_CLKP",         "type": "bidirectional",-        "description": "CSI_CLKP is the positive clock channel of the MIPI CSI PHY, powered by VDD_MIPI_DPHY."+        "description": "MIPI CSI PHY clock positive channel, powered by VDD_MIPI_DPHY."       },       {         "number": "45",         "name": "CSI_CLKN",         "type": "bidirectional",-        "description": "CSI_CLKN is the negative clock channel of the MIPI CSI PHY, powered by VDD_MIPI_DPHY."+        "description": "MIPI CSI PHY clock negative channel, powered by VDD_MIPI_DPHY."       },       {         "number": "46",         "name": "CSI_DATAN1",         "type": "bidirectional",-        "description": "CSI_DATAN1 is the negative data channel 1 of the MIPI CSI PHY, powered by VDD_MIPI_DPHY."+        "description": "MIPI CSI PHY data negative channel 1, powered by VDD_MIPI_DPHY."       },       {         "number": "47",         "name": "CSI_DATAP1",         "type": "bidirectional",-        "description": "CSI_DATAP1 is the positive data channel 1 of the MIPI CSI PHY, powered by VDD_MIPI_DPHY."+        "description": "MIPI CSI PHY data positive channel 1, powered by VDD_MIPI_DPHY."       },       {         "number": "48",         "name": "CSI_REXT",-        "type": "bidirectional",-        "description": "CSI_REXT is the MIPI CSI PHY pin for the 4.02 kΩ external reference resistor, powered by VDD_MIPI_DPHY."+        "type": "passive",+        "description": "MIPI CSI PHY external 4.02 kΩ reference resistor connection, powered by VDD_MIPI_DPHY."       },       {         "number": "49",         "name": "USB_DM",         "type": "bidirectional",-        "description": "USB_DM is the USB 2.0 High-Speed OTG PHY D- signal, powered by VDD_USBPHY."+        "description": "USB 2.0 High-Speed OTG PHY D- (USB_D-) signal, powered by VDD_USBPHY."       },       {         "number": "50",         "name": "USB_DP",         "type": "bidirectional",-        "description": "USB_DP is the USB 2.0 High-Speed OTG PHY D+ signal, powered by VDD_USBPHY."+        "description": "USB 2.0 High-Speed OTG PHY D+ (USB_D+) signal, powered by VDD_USBPHY."       },       {         "number": "51",         "name": "VDD_USBPHY",         "type": "power_in",-        "description": "VDD_USBPHY is the USB PHY supply, recommended at 2.97 V to 3.63 V (typ. 3.3 V) with an absolute maximum of 3.96 V."+        "description": "USB PHY supply; recommended input voltage is 2.97 V to 3.63 V (typ. 3.3 V)."       },       {         "number": "52",         "name": "GPIO24",         "type": "bidirectional",-        "description": "GPIO24 is an HP IO powered from VDD_IO_4 with default drive strength 40 mA and the USB1P1_N0 analog function of the USB Full-Speed/Serial-JTAG pair."+        "description": "GPIO24 is powered by VDD_IO_4, has a default drive strength of 40 mA, and provides analog USB1P1_N0 as its USB full-speed D- function."       },       {         "number": "53",         "name": "GPIO25",         "type": "bidirectional",-        "description": "GPIO25 is an HP IO powered from VDD_IO_4 with default drive strength 40 mA, USB_PU pull-up enabled at reset, and the USB1P1_P0 analog function."+        "description": "GPIO25 is powered by VDD_IO_4 with USB pull-up enabled at reset, has a default drive strength of 40 mA, and provides analog USB1P1_P0 as its USB full-speed D+ function."       },       {         "number": "54",         "name": "NC",         "type": "unconnected",-        "description": "Pin 54 is listed as NC (no connection) in the datasheet pin table."+        "description": "No-connect pin; the datasheet specifies no function for this pin."       },       {         "number": "55",         "name": "GPIO26",         "type": "bidirectional",-        "description": "GPIO26 is an HP IO powered from VDD_IO_4 that carries the USB1P1_N1 analog function of the second USB PHY pair, which is the default USB Full-Speed OTG pin pair."+        "description": "GPIO26 is powered by VDD_IO_4 and provides analog USB1P1_N1 as a USB full-speed D- function; USB pins are enabled for USB by default."       },       {         "number": "56",         "name": "GPIO27",         "type": "bidirectional",-        "description": "GPIO27 is an HP IO powered from VDD_IO_4 that carries the USB1P1_P1 analog function of the second USB PHY pair."+        "description": "GPIO27 is powered by VDD_IO_4 and provides analog USB1P1_P1 as a USB full-speed D+ function; USB pins are enabled for USB by default."       },       {         "number": "57",         "name": "GPIO28",         "type": "bidirectional",-        "description": "GPIO28 is an HP IO powered from VDD_IO_4 that carries the SPI2_CS_PAD chip select (8-line SPI2) and the GMAC_PHY_RXDV_PAD RMII receive data valid input."+        "description": "GPIO28 is powered by VDD_IO_4 and its IO MUX functions are SPI2_CS_PAD (F2) and GMAC_PHY_RXDV_PAD (F3, RMII/MII receive data valid)."       },       {         "number": "58",         "name": "GPIO29",         "type": "bidirectional",-        "description": "GPIO29 is an HP IO powered from VDD_IO_4 that carries the SPI2_D_PAD data input and the GMAC_PHY_RXD0_PAD RMII receive data line 0."+        "description": "GPIO29 is powered by VDD_IO_4 and its IO MUX functions are SPI2_D_PAD (F2) and GMAC_PHY_RXD0_PAD (F3, Ethernet receive data line 0)."       },       {         "number": "59",         "name": "VDD_PSRAM_0",         "type": "power_in",-        "description": "VDD_PSRAM_0 is the PSRAM IO supply, recommended at 1.65 V to 1.95 V (typ. 1.8 V)."+        "description": "PSRAM IO supply; recommended input voltage is 1.65 V to 1.95 V (typ. 1.8 V)."       },       {         "number": "60",         "name": "GPIO30",         "type": "bidirectional",-        "description": "GPIO30 is an HP IO powered from VDD_IO_4 that carries the SPI2_CK_PAD clock and the GMAC_PHY_RXD1_PAD RMII receive data line 1."+        "description": "GPIO30 is powered by VDD_IO_4 and its IO MUX functions are SPI2_CK_PAD (F2) and GMAC_PHY_RXD1_PAD (F3, Ethernet receive data line 1)."       },       {         "number": "61",         "name": "GPIO31",         "type": "bidirectional",-        "description": "GPIO31 is an HP IO powered from VDD_IO_4 that carries the SPI2_Q_PAD data output and the GMAC_PHY_RXER_PAD receive error input."+        "description": "GPIO31 is powered by VDD_IO_4 and its IO MUX functions are SPI2_Q_PAD (F2) and GMAC_PHY_RXER_PAD (F3, Ethernet receive error)."       },       {         "number": "62",         "name": "VDD_IO_4",         "type": "power_in",-        "description": "VDD_IO_4 is the digital IO power supply for the HP IO group, recommended at 1.65 V to 3.6 V (typ. 3.3 V)."+        "description": "Digital power domain supply for HP IOs; recommended input voltage is 1.65 V to 3.6 V (typ. 3.3 V)."       },       {         "number": "63",         "name": "GPIO32",         "type": "bidirectional",-        "description": "GPIO32 is an HP IO powered from VDD_IO_4 with input enabled at reset, carrying the SPI2_HOLD_PAD signal, the GMAC_RMII_CLK_PAD RMII clock and the I3C clock/data routing option."+        "description": "GPIO32 is powered by VDD_IO_4 with input enabled at reset, and its IO MUX functions are SPI2_HOLD_PAD (F2) and GMAC_RMII_CLK_PAD (F3)."       },       {         "number": "64",         "name": "GPIO33",         "type": "bidirectional",-        "description": "GPIO33 is an HP IO powered from VDD_IO_4 with input enabled at reset, carrying the SPI2_WP_PAD write protect and the GMAC_PHY_TXEN_PAD transmit enable output."+        "description": "GPIO33 is powered by VDD_IO_4 with input enabled at reset, and its IO MUX functions are SPI2_WP_PAD (F2) and GMAC_PHY_TXEN_PAD (F3, Ethernet transmit enable)."       },       {         "number": "65",         "name": "GPIO34",         "type": "bidirectional",-        "description": "GPIO34 is an HP IO powered from VDD_IO_4 with input enabled at reset, carrying the SPI2_IO4_PAD signal and the GMAC_PHY_TXD0_PAD transmit data output, and is the JTAG-source strapping pin."+        "description": "GPIO34 is powered by VDD_IO_4 with input enabled at reset and is a strapping pin that selects the JTAG signal source (floating by default); its IO MUX functions are SPI2_IO4_PAD (F2) and GMAC_PHY_TXD0_PAD (F3)."       },       {         "number": "66",         "name": "GPIO35",         "type": "bidirectional",-        "description": "GPIO35 is an HP IO powered from VDD_IO_4 with input enabled and weak pull-up at reset, carrying the SPI2_IO5_PAD signal and the GMAC_PHY_TXD1_PAD output, and is a chip boot-mode strapping pin."+        "description": "GPIO35 is powered by VDD_IO_4 with input enabled and weak pull-up enabled at reset, and is a chip boot mode strapping pin (weak pull-up, bit value 1 by default); its IO MUX functions are SPI2_IO5_PAD (F2) and GMAC_PHY_TXD1_PAD (F3)."       },       {         "number": "67",         "name": "VDD_PSRAM_1",         "type": "power_in",-        "description": "VDD_PSRAM_1 is the PSRAM IO supply, recommended at 1.65 V to 1.95 V (typ. 1.8 V)."+        "description": "PSRAM IO supply; recommended input voltage is 1.65 V to 1.95 V (typ. 1.8 V)."       },       {         "number": "68",         "name": "GPIO36",         "type": "bidirectional",-        "description": "GPIO36 is an HP IO powered from VDD_IO_4 with input enabled at reset, carrying the SPI2_IO6_PAD signal and the GMAC_PHY_TXER_PAD output, and is a ROM message-printing strapping pin."+        "description": "GPIO36 is powered by VDD_IO_4 with input enabled at reset and is a strapping pin for ROM message printing (floating by default); its IO MUX functions are SPI2_IO6_PAD (F2) and GMAC_PHY_TXER_PAD (F3)."       },       {         "number": "69",         "name": "GPIO37",         "type": "bidirectional",-        "description": "GPIO37 is an HP IO powered from VDD_IO_4 that carries the UART0_TXD_PAD transmit output and the SPI2_IO7_PAD signal, and is a boot-mode strapping pin."+        "description": "GPIO37 is powered by VDD_IO_4 and is a chip boot mode strapping pin; its IO MUX functions are UART0_TXD_PAD (F0) and SPI2_IO7_PAD (F2)."       },       {         "number": "70",         "name": "GPIO38",         "type": "bidirectional",-        "description": "GPIO38 is an HP IO powered from VDD_IO_4 with input enabled, carrying the UART0_RXD_PAD receive input and the SPI2_DQS_PAD data strobe, and is a boot-mode strapping pin."+        "description": "GPIO38 is powered by VDD_IO_4 with input enabled at reset and is a chip boot mode strapping pin; its IO MUX functions are UART0_RXD_PAD (F0) and SPI2_DQS_PAD (F2)."       },       {         "number": "71",         "name": "VDDO_FLASH",         "type": "power_out",-        "description": "VDDO_FLASH is a regulated output supply for the off-package flash, rated at 50 mA maximum."+        "description": "Regulated output rail for off-package flash, supplying up to 50 mA at maximum."       },       {         "number": "72",         "name": "VDDO_PSRAM",         "type": "power_out",-        "description": "VDDO_PSRAM is a regulated output supply for in-package and off-package PSRAM, rated at 50 mA maximum."+        "description": "Regulated output rail for in-package and off-package PSRAM, supplying up to 50 mA at maximum."       },       {         "number": "73",         "name": "VDDO_3",         "type": "power_out",-        "description": "VDDO_3 is a regulated output supply rated at 50 mA maximum."+        "description": "Regulated output rail, supplying up to 50 mA at maximum."       },       {         "number": "74",         "name": "VDDO_4",         "type": "power_out",-        "description": "VDDO_4 is a regulated output supply rated at 50 mA maximum."+        "description": "Regulated output rail, supplying up to 50 mA at maximum."       },       {         "number": "75",         "name": "VDD_LDO",         "type": "power_in",-        "description": "VDD_LDO is the analog power domain supply for the internal LDOs, recommended at 3.0 V to 3.6 V (typ. 3.3 V)."+        "description": "Analog power domain supply for the LDOs; recommended input voltage is 3.0 V to 3.6 V (typ. 3.3 V)."       },       {         "number": "76",         "name": "VDD_HP_2",         "type": "power_in",-        "description": "VDD_HP_2 is a digital core supply, recommended at 0.99 V to 1.3 V (typ. 1.1 V)."+        "description": "Digital power domain supply; recommended input voltage is 0.99 V to 1.3 V (typ. 1.1 V)."       },       {         "number": "77",         "name": "VDD_DCDCC",         "type": "power_in",-        "description": "VDD_DCDCC is the analog power supply for the DC/DC control circuit, recommended at 3.0 V to 3.6 V (typ. 3.3 V)."+        "description": "Analog power domain supply for DC/DC control; recommended input voltage is 3.0 V to 3.6 V (typ. 3.3 V)."       },       {         "number": "78",         "name": "FB_DCDC",         "type": "passive",-        "description": "FB_DCDC is the feedback pin of the external DC/DC supply, which regulates VDD_HP_0/2/3 together with external feedback resistors."+        "description": "Feedback pin of the external DC/DC power supply, which regulates VDD_HP_0/2/3 together with feedback resistors."       },       {         "number": "79",         "name": "EN_DCDC",         "type": "output",-        "description": "EN_DCDC is the enable output pin for the external DC/DC converter."+        "description": "Enable pin of the external DC/DC converter."       },       {         "number": "80",         "name": "GPIO39",         "type": "bidirectional",-        "description": "GPIO39 is an HP IO powered from VDD_IO_5 that carries the SD1_CDATA0_PAD SDIO data line and the REF_50M_CLK_PAD 50 MHz clock output."+        "description": "GPIO39 is powered by VDD_IO_5 and its IO MUX functions are SD1_CDATA0_PAD (F0) and REF_50M_CLK_PAD (F3, 50 MHz reference clock output)."       },       {         "number": "81",         "name": "GPIO40",         "type": "bidirectional",-        "description": "GPIO40 is an HP IO powered from VDD_IO_5 that carries the SD1_CDATA1_PAD SDIO data line and the GMAC_PHY_TXEN_PAD transmit enable output."+        "description": "GPIO40 is powered by VDD_IO_5 and its IO MUX functions are SD1_CDATA1_PAD (F0) and GMAC_PHY_TXEN_PAD (F3)."       },       {         "number": "82",         "name": "GPIO41",         "type": "bidirectional",-        "description": "GPIO41 is an HP IO powered from VDD_IO_5 that carries the SD1_CDATA2_PAD SDIO data line and the GMAC_PHY_TXD0_PAD transmit data output."+        "description": "GPIO41 is powered by VDD_IO_5 and its IO MUX functions are SD1_CDATA2_PAD (F0) and GMAC_PHY_TXD0_PAD (F3)."       },       {         "number": "83",         "name": "GPIO42",         "type": "bidirectional",-        "description": "GPIO42 is an HP IO powered from VDD_IO_5 that carries the SD1_CDATA3_PAD SDIO data line and the GMAC_PHY_TXD1_PAD transmit data output."+        "description": "GPIO42 is powered by VDD_IO_5 and its IO MUX functions are SD1_CDATA3_PAD (F0) and GMAC_PHY_TXD1_PAD (F3)."       },       {         "number": "84",         "name": "GPIO43",         "type": "bidirectional",-        "description": "GPIO43 is an HP IO powered from VDD_IO_5 that carries the SD1_CCLK_PAD SDIO card clock output and the GMAC_PHY_TXER_PAD transmit error output."+        "description": "GPIO43 is powered by VDD_IO_5 and its IO MUX functions are SD1_CCLK_PAD (F0) and GMAC_PHY_TXER_PAD (F3)."       },       {         "number": "85",         "name": "VDD_IO_5",         "type": "power_in",-        "description": "VDD_IO_5 is the digital IO power supply for the HP IO group, recommended at 1.65 V to 3.6 V (typ. 3.3 V)."+        "description": "Digital power domain supply for HP IOs; recommended input voltage is 1.65 V to 3.6 V (typ. 3.3 V)."       },       {         "number": "86",         "name": "GPIO44",         "type": "bidirectional",-        "description": "GPIO44 is an HP IO powered from VDD_IO_5 that carries the SD1_CCMD_PAD SDIO command line and the GMAC_RMII_CLK_PAD RMII clock input."+        "description": "GPIO44 is powered by VDD_IO_5 and its IO MUX functions are SD1_CCMD_PAD (F0) and GMAC_RMII_CLK_PAD (F3)."       },       {         "number": "87",         "name": "GPIO45",         "type": "bidirectional",-        "description": "GPIO45 is an HP IO powered from VDD_IO_5 that carries the SD1_CDATA4_PAD SDIO data line and the GMAC_PHY_RXDV_PAD receive data valid input."+        "description": "GPIO45 is powered by VDD_IO_5 and its IO MUX functions are SD1_CDATA4_PAD (F0) and GMAC_PHY_RXDV_PAD (F3)."       },       {         "number": "88",         "name": "GPIO46",         "type": "bidirectional",-        "description": "GPIO46 is an HP IO powered from VDD_IO_5 that carries the SD1_CDATA5_PAD SDIO data line and the GMAC_PHY_RXD0_PAD receive data input."+        "description": "GPIO46 is powered by VDD_IO_5 and its IO MUX functions are SD1_CDATA5_PAD (F0) and GMAC_PHY_RXD0_PAD (F3)."       },       {         "number": "89",         "name": "GPIO47",         "type": "bidirectional",-        "description": "GPIO47 is an HP IO powered from VDD_IO_5 that carries the SD1_CDATA6_PAD SDIO data line and the GMAC_PHY_RXD1_PAD receive data input."+        "description": "GPIO47 is powered by VDD_IO_5 and its IO MUX functions are SD1_CDATA6_PAD (F0) and GMAC_PHY_RXD1_PAD (F3)."       },       {         "number": "90",         "name": "GPIO48",         "type": "bidirectional",-        "description": "GPIO48 is an HP IO powered from VDD_IO_5 that carries the SD1_CDATA7_PAD SDIO data line and the GMAC_PHY_RXER_PAD receive error input."+        "description": "GPIO48 is powered by VDD_IO_5 and its IO MUX functions are SD1_CDATA7_PAD (F0) and GMAC_PHY_RXER_PAD (F3)."       },       {         "number": "91",         "name": "VDD_HP_3",         "type": "power_in",-        "description": "VDD_HP_3 is a digital core supply, recommended at 0.99 V to 1.3 V (typ. 1.1 V)."+        "description": "Digital power domain supply; recommended input voltage is 0.99 V to 1.3 V (typ. 1.1 V)."       },       {         "number": "92",         "name": "GPIO49",         "type": "bidirectional",-        "description": "GPIO49 is an HP IO powered from VDD_IO_6 that carries the ADC2_CHANNEL0 analog input and the GMAC_PHY_TXEN_PAD transmit enable output."+        "description": "GPIO49 is powered by VDD_IO_6 and provides analog ADC2_CHANNEL0 and IO MUX GMAC_PHY_TXEN_PAD (F3)."       },       {         "number": "93",         "name": "GPIO50",         "type": "bidirectional",-        "description": "GPIO50 is an HP IO powered from VDD_IO_6 that carries the ADC2_CHANNEL1 analog input and the GMAC_RMII_CLK_PAD RMII clock input."+        "description": "GPIO50 is powered by VDD_IO_6 and provides analog ADC2_CHANNEL1 and IO MUX GMAC_RMII_CLK_PAD (F3)."       },       {         "number": "94",         "name": "GPIO51",         "type": "bidirectional",-        "description": "GPIO51 is an HP IO powered from VDD_IO_6 that carries the ADC2_CHANNEL2 and ANA_COMP0 analog functions and the GMAC_PHY_RXDV_PAD receive data valid input."+        "description": "GPIO51 is powered by VDD_IO_6 and provides analog ADC2_CHANNEL2 and ANA_COMP0, and IO MUX GMAC_PHY_RXDV_PAD (F3)."       },       {         "number": "95",         "name": "GPIO52",         "type": "bidirectional",-        "description": "GPIO52 is an HP IO powered from VDD_IO_6 that carries the ADC2_CHANNEL3 and ANA_COMP0 analog functions and the GMAC_PHY_RXD0_PAD receive data input."+        "description": "GPIO52 is powered by VDD_IO_6 and provides analog ADC2_CHANNEL3 and ANA_COMP0, and IO MUX GMAC_PHY_RXD0_PAD (F3)."       },       {         "number": "96",         "name": "VDD_IO_6",         "type": "power_in",-        "description": "VDD_IO_6 is the digital IO power supply for the HP IO group, recommended at 1.65 V to 3.6 V (typ. 3.3 V)."+        "description": "Digital power domain supply for HP IOs; recommended input voltage is 1.65 V to 3.6 V (typ. 3.3 V)."       },       {         "number": "97",         "name": "GPIO53",         "type": "bidirectional",-        "description": "GPIO53 is an HP IO powered from VDD_IO_6 that carries the ADC2_CHANNEL4 and ANA_COMP1 analog functions and the GMAC_PHY_RXD1_PAD receive data input."+        "description": "GPIO53 is powered by VDD_IO_6 and provides analog ADC2_CHANNEL4 and ANA_COMP1, and IO MUX GMAC_PHY_RXD1_PAD (F3)."       },       {         "number": "98",         "name": "GPIO54",         "type": "bidirectional",-        "description": "GPIO54 is an HP IO powered from VDD_IO_6 that carries the ADC2_CHANNEL5 and ANA_COMP1 analog functions and the GMAC_PHY_RXER_PAD receive error input."+        "description": "GPIO54 is powered by VDD_IO_6 and provides analog ADC2_CHANNEL5 and ANA_COMP1, and IO MUX GMAC_PHY_RXER_PAD (F3)."       },       {         "number": "99",         "name": "XTAL_N",         "type": "passive",-        "description": "XTAL_N is the negative side of the differential clock connection to the chip's crystal or oscillator."+        "description": "Differential negative external clock input/output connected to the chip's crystal or oscillator."       },       {         "number": "100",         "name": "XTAL_P",         "type": "passive",-        "description": "XTAL_P is the positive side of the differential clock connection to the chip's crystal or oscillator."+        "description": "Differential positive external clock input/output connected to the chip's crystal or oscillator."       },       {         "number": "101",         "name": "VDD_ANA",         "type": "power_in",-        "description": "VDD_ANA is the analog power domain supply, recommended at 3.0 V to 3.6 V (typ. 3.3 V)."+        "description": "Analog power domain supply; recommended input voltage is 3.0 V to 3.6 V (typ. 3.3 V)."       },       {         "number": "102",         "name": "VDD_BAT",         "type": "power_in",-        "description": "VDD_BAT is the analog power domain supply that can optionally connect to an external battery, recommended at 2.5 V to 3.6 V (typ. 3.3 V)."+        "description": "Analog power domain supply that can optionally connect to an external battery; recommended input voltage is 2.5 V to 3.6 V (typ. 3.3 V)."       },       {         "number": "103",         "name": "CHIP_PU",         "type": "input",-        "description": "CHIP_PU is the chip enable input: high enables the chip and low powers it down, and it must not be left floating."+        "description": "Chip enable: high enables the chip (powered up), low disables it (powered down), and the pin must not be left floating."       },       {         "number": "104",         "name": "GPIO0",         "type": "bidirectional",-        "description": "GPIO0 is an LP IO powered from VDD_LP/VDD_BAT that carries the XTAL_32K_N analog function and LP_GPIO0."+        "description": "GPIO0 is powered by VDD_LP/VDD_BAT, provides IO MUX GPIO function, LP_GPIO0 and analog XTAL_32K_N."       },       {         "number": "105",         "name": "GND",         "type": "power_in",-        "description": "GND is the external ground connection pin."+        "description": "External ground connection (exposed pad)."       }     ],     "provenance": {@@ -706,12 +706,11 @@         "consensus": "agreed",         "guards": "pin_guards 0.1: passed",         "guard_notes": [-          "extractor flagged: The datasheet marks ESP32-P4NRW32 as End of life (EOL), upgraded to ESP32-P4NRW32X, and refers to th; The datasheet pin table (Table 2-1 and Appendix A) lists the QFN104 package for this series. The pac; Pin 30 is named VDD_FLASHIO in Table 2-1 and Figure 2-1, but Table 2-11 writes VDD_FLASHIO2 with a f",-          "9/105 pins cited to the wrong page (name found elsewhere): ['9:VDD_LP@p79', '21:VDD_IO_0@p79', '30:VDD_FLASHIO@p79', '41:VDD_MIPI_DPHY@p79']"+          "extractor flagged: MPN ESP32-P4NRW32 is marked End of life (EOL) in the datasheet and is upgraded to ESP32-P4NRW32X; co; Pin 30 is named VDD_FLASHIO in Table 2-1 and Table 2-11 but written as VDD_FLASHIO2 in the Table 2-1; EN_DCDC (pin 79) is typed 'Analog' in Table 2-1 but 'O' (output) in Table 2-10; output was used. FB_"         ],         "pages_sent": 53,-        "cost_usd": 0.2825,-        "at": "2026-10-28T19:12:25"+        "cost_usd": 0.1085,+        "at": "2026-10-28T19:26:23"       },       "datasheet": {         "url": "https://www.espressif.com/sites/default/files/documentation/esp32-p4-chip-revision-v1.3_datasheet_en.pdf",@@ -747,7 +746,7 @@         "zmin_mm": 0.0,         "centre_offset_mm": 0.0,         "footprint_binding": "none",-        "sha256": "457ab6b63d8e996dbb736b913bc7e8e932306d4c484c72ca3c2c8c8418cd18a8",+        "sha256": "254f1f267e61a0f8af253946e3650817a1b84b20d3a060157191e18b3fc57f84",         "checked": "2026-10-28",         "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"       },@@ -766,7 +765,7 @@         "zmin_mm": 0.0,         "centre_offset_mm": 0.0,         "footprint_binding": "none",-        "sha256": "4c84a2b1fdb66dfa038957de4bc65ed976e3e63b5fd37b1524e854a4d58def9a",+        "sha256": "05248e5caf5986f22caae7d75e05e2bbc851c4bdd8c11bb4c8fa6cfb365ecd54",         "checked": "2026-10-28",         "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"       }
page.json+117−118
@@ -4,7 +4,7 @@   "slug": "esp32-p4nrw32",   "title": "ESP32-P4NRW32",   "brief": "ESPRESSIF Functional Modules, QFN-104(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",-  "version": "0.1.0",+  "version": "0.1.3",   "license": "CC-BY-SA-4.0",   "tags": [     "component",@@ -34,7 +34,7 @@       "lcsc": "C22387510"     },     "distributor_check": {-      "checked_at": "2026-10-28T19:13:05Z",+      "checked_at": "2026-10-28T19:26:59Z",       "source": "Component Ocean /api/assign-pns",       "digikey": {         "pn": null,@@ -50,631 +50,631 @@         "number": "1",         "name": "GPIO1",         "type": "bidirectional",-        "description": "GPIO1 is a general-purpose IO powered from VDD_LP/VDD_BAT that also carries the XTAL_32K_P analog function and LP_GPIO1 in Deep-sleep mode, with default drive strength 20 mA."+        "description": "GPIO1 is powered by VDD_LP/VDD_BAT, has no pin setting at reset, and offers IO MUX GPIO1, LP IO MUX LP_GPIO1 and analog XTAL_32K_P functions."       },       {         "number": "2",         "name": "GPIO2",         "type": "bidirectional",-        "description": "GPIO2 is an LP IO powered from VDD_LP/VDD_BAT that carries the MTCK JTAG clock, TOUCH_CHANNEL1 and LP_GPIO2, and is input-enabled with weak pull-up at reset (EFUSE_DIS_PAD_JTAG dependent)."+        "description": "GPIO2 is powered by VDD_LP/VDD_BAT with input enabled and weak pull-up enabled at reset, and its IO MUX F0 function is MTCK (JTAG test clock) with touch channel TOUCH_CHANNEL1."       },       {         "number": "3",         "name": "GPIO3",         "type": "bidirectional",-        "description": "GPIO3 is an LP IO powered from VDD_LP/VDD_BAT that carries the MTDI JTAG input, TOUCH_CHANNEL2 and LP_GPIO3, and is input-enabled at reset."+        "description": "GPIO3 is powered by VDD_LP/VDD_BAT with input enabled at reset, and its IO MUX F0 function is MTDI (JTAG test data in) with touch channel TOUCH_CHANNEL2."       },       {         "number": "4",         "name": "GPIO4",         "type": "bidirectional",-        "description": "GPIO4 is an LP IO powered from VDD_LP that carries the MTMS JTAG input, TOUCH_CHANNEL3 and LP_GPIO4, and is input-enabled at reset."+        "description": "GPIO4 is powered by VDD_LP with input enabled at reset, and its IO MUX F0 function is MTMS (JTAG test mode select) with touch channel TOUCH_CHANNEL3."       },       {         "number": "5",         "name": "GPIO5",         "type": "bidirectional",-        "description": "GPIO5 is an LP IO powered from VDD_LP that carries the MTDO JTAG output (tri-state capable), TOUCH_CHANNEL4 and LP_GPIO5."+        "description": "GPIO5 is powered by VDD_LP, and its IO MUX F0 function is MTDO (JTAG test data out) with touch channel TOUCH_CHANNEL4."       },       {         "number": "6",         "name": "GPIO6",         "type": "bidirectional",-        "description": "GPIO6 is an LP IO powered from VDD_LP that carries the SPI2_HOLD_PAD (8-line/4-line SPI2 interface), TOUCH_CHANNEL5 and LP_GPIO6."+        "description": "GPIO6 is powered by VDD_LP and its IO MUX F2 function is SPI2_HOLD_PAD, with touch channel TOUCH_CHANNEL5 and LP_GPIO6 available."       },       {         "number": "7",         "name": "GPIO7",         "type": "bidirectional",-        "description": "GPIO7 is an LP IO powered from VDD_LP that carries the SPI2_CS_PAD chip select, TOUCH_CHANNEL6 and LP_GPIO7."+        "description": "GPIO7 is powered by VDD_LP and its IO MUX F2 function is SPI2_CS_PAD, with touch channel TOUCH_CHANNEL6 and LP_GPIO7 available."       },       {         "number": "8",         "name": "GPIO8",         "type": "bidirectional",-        "description": "GPIO8 is an LP IO powered from VDD_LP that carries the SPI2_D_PAD data input, TOUCH_CHANNEL7 and LP_GPIO8."+        "description": "GPIO8 is powered by VDD_LP and its IO MUX F2 function is SPI2_D_PAD, with touch channel TOUCH_CHANNEL7 and LP_GPIO8 available."       },       {         "number": "9",         "name": "VDD_LP",         "type": "power_in",-        "description": "VDD_LP is the LP power domain supply, recommended at 3.0 V to 3.6 V (typ. 3.3 V)."+        "description": "LP power domain supply; recommended input voltage is 3.0 V to 3.6 V (typ. 3.3 V)."       },       {         "number": "10",         "name": "GPIO9",         "type": "bidirectional",-        "description": "GPIO9 is an LP IO powered from VDD_LP that carries the SPI2_CK_PAD clock, TOUCH_CHANNEL8 and LP_GPIO9."+        "description": "GPIO9 is powered by VDD_LP and its IO MUX F2 function is SPI2_CK_PAD, with touch channel TOUCH_CHANNEL8 and LP_GPIO9 available."       },       {         "number": "11",         "name": "GPIO10",         "type": "bidirectional",-        "description": "GPIO10 is an LP IO powered from VDD_LP that carries the SPI2_Q_PAD data output, TOUCH_CHANNEL9 and LP_GPIO10."+        "description": "GPIO10 is powered by VDD_LP and its IO MUX F2 function is SPI2_Q_PAD, with touch channel TOUCH_CHANNEL9 and LP_GPIO10 available."       },       {         "number": "12",         "name": "GPIO11",         "type": "bidirectional",-        "description": "GPIO11 is an LP IO powered from VDD_LP that carries the SPI2_WP_PAD write protect, TOUCH_CHANNEL10 and LP_GPIO11."+        "description": "GPIO11 is powered by VDD_LP and its IO MUX F2 function is SPI2_WP_PAD, with touch channel TOUCH_CHANNEL10 and LP_GPIO11 available."       },       {         "number": "13",         "name": "GPIO12",         "type": "bidirectional",-        "description": "GPIO12 is an LP IO powered from VDD_LP that carries TOUCH_CHANNEL11 and LP_GPIO12."+        "description": "GPIO12 is powered by VDD_LP and provides touch channel TOUCH_CHANNEL11, LP_GPIO12 and IO MUX GPIO function."       },       {         "number": "14",         "name": "GPIO13",         "type": "bidirectional",-        "description": "GPIO13 is an LP IO powered from VDD_LP that carries TOUCH_CHANNEL12 and LP_GPIO13."+        "description": "GPIO13 is powered by VDD_LP and provides touch channel TOUCH_CHANNEL12, LP_GPIO13 and IO MUX GPIO function."       },       {         "number": "15",         "name": "GPIO14",         "type": "bidirectional",-        "description": "GPIO14 is an LP IO powered from VDD_LP that carries the LP_UART_TXD_PAD transmit output, TOUCH_CHANNEL13 and LP_GPIO14."+        "description": "GPIO14 is powered by VDD_LP and its LP IO MUX function is LP_UART_TXD_PAD, with touch channel TOUCH_CHANNEL13 and LP_GPIO14 available."       },       {         "number": "16",         "name": "GPIO15",         "type": "bidirectional",-        "description": "GPIO15 is an LP IO powered from VDD_LP that carries the LP_UART_RXD_PAD receive input, TOUCH_CHANNEL14 and LP_GPIO15."+        "description": "GPIO15 is powered by VDD_LP and its LP IO MUX function is LP_UART_RXD_PAD, with touch channel TOUCH_CHANNEL14 and LP_GPIO15 available."       },       {         "number": "17",         "name": "GPIO16",         "type": "bidirectional",-        "description": "GPIO16 is an HP IO powered from VDD_IO_0 (1.65 V to 3.6 V) that carries the ADC1_CHANNEL0 analog input."+        "description": "GPIO16 is powered by VDD_IO_0 and provides IO MUX GPIO function and analog ADC1_CHANNEL0."       },       {         "number": "18",         "name": "GPIO17",         "type": "bidirectional",-        "description": "GPIO17 is an HP IO powered from VDD_IO_0 (1.65 V to 3.6 V) that carries the ADC1_CHANNEL1 analog input."+        "description": "GPIO17 is powered by VDD_IO_0 and provides IO MUX GPIO function and analog ADC1_CHANNEL1."       },       {         "number": "19",         "name": "GPIO18",         "type": "bidirectional",-        "description": "GPIO18 is an HP IO powered from VDD_IO_0 (1.65 V to 3.6 V) that carries the ADC1_CHANNEL2 analog input."+        "description": "GPIO18 is powered by VDD_IO_0 and provides IO MUX GPIO function and analog ADC1_CHANNEL2."       },       {         "number": "20",         "name": "GPIO19",         "type": "bidirectional",-        "description": "GPIO19 is an HP IO powered from VDD_IO_0 (1.65 V to 3.6 V) that carries the ADC1_CHANNEL3 analog input."+        "description": "GPIO19 is powered by VDD_IO_0 and provides IO MUX GPIO function and analog ADC1_CHANNEL3."       },       {         "number": "21",         "name": "VDD_IO_0",         "type": "power_in",-        "description": "VDD_IO_0 is the digital IO power supply for the HP IO group, recommended at 1.65 V to 3.6 V (typ. 3.3 V)."+        "description": "Digital power domain supply for HP IOs; recommended input voltage is 1.65 V to 3.6 V (typ. 3.3 V)."       },       {         "number": "22",         "name": "GPIO20",         "type": "bidirectional",-        "description": "GPIO20 is an HP IO powered from VDD_IO_0 (1.65 V to 3.6 V) that carries the ADC1_CHANNEL4 analog input."+        "description": "GPIO20 is powered by VDD_IO_0 and provides IO MUX GPIO function and analog ADC1_CHANNEL4."       },       {         "number": "23",         "name": "GPIO21",         "type": "bidirectional",-        "description": "GPIO21 is an HP IO powered from VDD_IO_0 (1.65 V to 3.6 V) that carries the ADC1_CHANNEL5 analog input."+        "description": "GPIO21 is powered by VDD_IO_0 and provides IO MUX GPIO function and analog ADC1_CHANNEL5."       },       {         "number": "24",         "name": "GPIO22",         "type": "bidirectional",-        "description": "GPIO22 is an HP IO powered from VDD_IO_0 (1.65 V to 3.6 V) that carries the ADC1_CHANNEL6 analog input."+        "description": "GPIO22 is powered by VDD_IO_0 and provides IO MUX GPIO function and analog ADC1_CHANNEL6."       },       {         "number": "25",         "name": "GPIO23",         "type": "bidirectional",-        "description": "GPIO23 is an HP IO powered from VDD_IO_0 (1.65 V to 3.6 V) that carries the ADC1_CHANNEL7 analog input and the REF_50M_CLK_PAD 50 MHz reference clock output."+        "description": "GPIO23 is powered by VDD_IO_0, provides IO MUX GPIO function with REF_50M_CLK_PAD (50 MHz reference clock output) and analog ADC1_CHANNEL7."       },       {         "number": "26",         "name": "VDD_HP_0",         "type": "power_in",-        "description": "VDD_HP_0 is the digital core supply, recommended at 0.99 V to 1.3 V (typ. 1.1 V); the chip can adjust it automatically."+        "description": "Digital power domain supply; recommended input voltage is 0.99 V to 1.3 V (typ. 1.1 V)."       },       {         "number": "27",         "name": "FLASH_CS",         "type": "output",-        "description": "FLASH_CS is the dedicated off-package flash chip-select output, powered by VDD_FLASHIO."+        "description": "Dedicated off-package flash chip-select output, powered by VDD_FLASHIO."       },       {         "number": "28",         "name": "FLASH_Q",         "type": "bidirectional",-        "description": "FLASH_Q is the dedicated flash data-output line (DO) powered by VDD_FLASHIO."+        "description": "Dedicated off-package flash data output (DO) pin, powered by VDD_FLASHIO."       },       {         "number": "29",         "name": "FLASH_WP",         "type": "bidirectional",-        "description": "FLASH_WP is the dedicated flash write-protect line (WP#) powered by VDD_FLASHIO."+        "description": "Dedicated off-package flash write-protect (WP#) pin, powered by VDD_FLASHIO."       },       {         "number": "30",         "name": "VDD_FLASHIO",         "type": "power_in",-        "description": "VDD_FLASHIO powers the flash IO and should be set according to the flash model; the datasheet uses 3.3 V flash as the example, with recommended input 1.65 V to 3.6 V."+        "description": "Power supply for flash IO; the voltage should be adjusted according to the specific flash model, and the datasheet describes 3.3 V flash as the example."       },       {         "number": "31",         "name": "FLASH_HOLD",         "type": "bidirectional",-        "description": "FLASH_HOLD is the dedicated flash hold line (HOLD#) powered by VDD_FLASHIO."+        "description": "Dedicated off-package flash HOLD# pin, powered by VDD_FLASHIO."       },       {         "number": "32",         "name": "FLASH_CK",         "type": "output",-        "description": "FLASH_CK is the dedicated flash clock output (CLK) powered by VDD_FLASHIO."+        "description": "Dedicated off-package flash clock output, powered by VDD_FLASHIO."       },       {         "number": "33",         "name": "FLASH_D",         "type": "bidirectional",-        "description": "FLASH_D is the dedicated flash data-input line (DI) powered by VDD_FLASHIO."+        "description": "Dedicated off-package flash data input (DI) pin, powered by VDD_FLASHIO."       },       {         "number": "34",         "name": "DSI_REXT",-        "type": "bidirectional",-        "description": "DSI_REXT is the MIPI DSI PHY pin for the 4.02 kΩ external reference resistor, powered by VDD_MIPI_DPHY."+        "type": "passive",+        "description": "MIPI DSI PHY external 4.02 kΩ reference resistor connection, powered by VDD_MIPI_DPHY."       },       {         "number": "35",         "name": "DSI_DATAP1",         "type": "bidirectional",-        "description": "DSI_DATAP1 is the positive data channel 1 of the MIPI DSI PHY (2-lane, 1.5 Gbps per lane), powered by VDD_MIPI_DPHY."+        "description": "MIPI DSI PHY data positive channel 1, powered by VDD_MIPI_DPHY."       },       {         "number": "36",         "name": "DSI_DATAN1",         "type": "bidirectional",-        "description": "DSI_DATAN1 is the negative data channel 1 of the MIPI DSI PHY, powered by VDD_MIPI_DPHY."+        "description": "MIPI DSI PHY data negative channel 1, powered by VDD_MIPI_DPHY."       },       {         "number": "37",         "name": "DSI_CLKN",         "type": "bidirectional",-        "description": "DSI_CLKN is the negative clock channel of the MIPI DSI PHY, powered by VDD_MIPI_DPHY."+        "description": "MIPI DSI PHY clock negative channel, powered by VDD_MIPI_DPHY."       },       {         "number": "38",         "name": "DSI_CLKP",         "type": "bidirectional",-        "description": "DSI_CLKP is the positive clock channel of the MIPI DSI PHY, powered by VDD_MIPI_DPHY."+        "description": "MIPI DSI PHY clock positive channel, powered by VDD_MIPI_DPHY."       },       {         "number": "39",         "name": "DSI_DATAP0",         "type": "bidirectional",-        "description": "DSI_DATAP0 is the positive data channel 0 of the MIPI DSI PHY, powered by VDD_MIPI_DPHY."+        "description": "MIPI DSI PHY data positive channel 0, powered by VDD_MIPI_DPHY."       },       {         "number": "40",         "name": "DSI_DATAN0",         "type": "bidirectional",-        "description": "DSI_DATAN0 is the negative data channel 0 of the MIPI DSI PHY, powered by VDD_MIPI_DPHY."+        "description": "MIPI DSI PHY data negative channel 0, powered by VDD_MIPI_DPHY."       },       {         "number": "41",         "name": "VDD_MIPI_DPHY",         "type": "power_in",-        "description": "VDD_MIPI_DPHY is the MIPI PHY supply, recommended at 2.25 V to 2.75 V (typ. 2.5 V) with an absolute maximum of 2.75 V."+        "description": "MIPI PHY supply; recommended input voltage is 2.25 V to 2.75 V (typ. 2.5 V)."       },       {         "number": "42",         "name": "CSI_DATAN0",         "type": "bidirectional",-        "description": "CSI_DATAN0 is the negative data channel 0 of the MIPI CSI PHY, powered by VDD_MIPI_DPHY."+        "description": "MIPI CSI PHY data negative channel 0, powered by VDD_MIPI_DPHY."       },       {         "number": "43",         "name": "CSI_DATAP0",         "type": "bidirectional",-        "description": "CSI_DATAP0 is the positive data channel 0 of the MIPI CSI PHY, powered by VDD_MIPI_DPHY."+        "description": "MIPI CSI PHY data positive channel 0, powered by VDD_MIPI_DPHY."       },       {         "number": "44",         "name": "CSI_CLKP",         "type": "bidirectional",-        "description": "CSI_CLKP is the positive clock channel of the MIPI CSI PHY, powered by VDD_MIPI_DPHY."+        "description": "MIPI CSI PHY clock positive channel, powered by VDD_MIPI_DPHY."       },       {         "number": "45",         "name": "CSI_CLKN",         "type": "bidirectional",-        "description": "CSI_CLKN is the negative clock channel of the MIPI CSI PHY, powered by VDD_MIPI_DPHY."+        "description": "MIPI CSI PHY clock negative channel, powered by VDD_MIPI_DPHY."       },       {         "number": "46",         "name": "CSI_DATAN1",         "type": "bidirectional",-        "description": "CSI_DATAN1 is the negative data channel 1 of the MIPI CSI PHY, powered by VDD_MIPI_DPHY."+        "description": "MIPI CSI PHY data negative channel 1, powered by VDD_MIPI_DPHY."       },       {         "number": "47",         "name": "CSI_DATAP1",         "type": "bidirectional",-        "description": "CSI_DATAP1 is the positive data channel 1 of the MIPI CSI PHY, powered by VDD_MIPI_DPHY."+        "description": "MIPI CSI PHY data positive channel 1, powered by VDD_MIPI_DPHY."       },       {         "number": "48",         "name": "CSI_REXT",-        "type": "bidirectional",-        "description": "CSI_REXT is the MIPI CSI PHY pin for the 4.02 kΩ external reference resistor, powered by VDD_MIPI_DPHY."+        "type": "passive",+        "description": "MIPI CSI PHY external 4.02 kΩ reference resistor connection, powered by VDD_MIPI_DPHY."       },       {         "number": "49",         "name": "USB_DM",         "type": "bidirectional",-        "description": "USB_DM is the USB 2.0 High-Speed OTG PHY D- signal, powered by VDD_USBPHY."+        "description": "USB 2.0 High-Speed OTG PHY D- (USB_D-) signal, powered by VDD_USBPHY."       },       {         "number": "50",         "name": "USB_DP",         "type": "bidirectional",-        "description": "USB_DP is the USB 2.0 High-Speed OTG PHY D+ signal, powered by VDD_USBPHY."+        "description": "USB 2.0 High-Speed OTG PHY D+ (USB_D+) signal, powered by VDD_USBPHY."       },       {         "number": "51",         "name": "VDD_USBPHY",         "type": "power_in",-        "description": "VDD_USBPHY is the USB PHY supply, recommended at 2.97 V to 3.63 V (typ. 3.3 V) with an absolute maximum of 3.96 V."+        "description": "USB PHY supply; recommended input voltage is 2.97 V to 3.63 V (typ. 3.3 V)."       },       {         "number": "52",         "name": "GPIO24",         "type": "bidirectional",-        "description": "GPIO24 is an HP IO powered from VDD_IO_4 with default drive strength 40 mA and the USB1P1_N0 analog function of the USB Full-Speed/Serial-JTAG pair."+        "description": "GPIO24 is powered by VDD_IO_4, has a default drive strength of 40 mA, and provides analog USB1P1_N0 as its USB full-speed D- function."       },       {         "number": "53",         "name": "GPIO25",         "type": "bidirectional",-        "description": "GPIO25 is an HP IO powered from VDD_IO_4 with default drive strength 40 mA, USB_PU pull-up enabled at reset, and the USB1P1_P0 analog function."+        "description": "GPIO25 is powered by VDD_IO_4 with USB pull-up enabled at reset, has a default drive strength of 40 mA, and provides analog USB1P1_P0 as its USB full-speed D+ function."       },       {         "number": "54",         "name": "NC",         "type": "unconnected",-        "description": "Pin 54 is listed as NC (no connection) in the datasheet pin table."+        "description": "No-connect pin; the datasheet specifies no function for this pin."       },       {         "number": "55",         "name": "GPIO26",         "type": "bidirectional",-        "description": "GPIO26 is an HP IO powered from VDD_IO_4 that carries the USB1P1_N1 analog function of the second USB PHY pair, which is the default USB Full-Speed OTG pin pair."+        "description": "GPIO26 is powered by VDD_IO_4 and provides analog USB1P1_N1 as a USB full-speed D- function; USB pins are enabled for USB by default."       },       {         "number": "56",         "name": "GPIO27",         "type": "bidirectional",-        "description": "GPIO27 is an HP IO powered from VDD_IO_4 that carries the USB1P1_P1 analog function of the second USB PHY pair."+        "description": "GPIO27 is powered by VDD_IO_4 and provides analog USB1P1_P1 as a USB full-speed D+ function; USB pins are enabled for USB by default."       },       {         "number": "57",         "name": "GPIO28",         "type": "bidirectional",-        "description": "GPIO28 is an HP IO powered from VDD_IO_4 that carries the SPI2_CS_PAD chip select (8-line SPI2) and the GMAC_PHY_RXDV_PAD RMII receive data valid input."+        "description": "GPIO28 is powered by VDD_IO_4 and its IO MUX functions are SPI2_CS_PAD (F2) and GMAC_PHY_RXDV_PAD (F3, RMII/MII receive data valid)."       },       {         "number": "58",         "name": "GPIO29",         "type": "bidirectional",-        "description": "GPIO29 is an HP IO powered from VDD_IO_4 that carries the SPI2_D_PAD data input and the GMAC_PHY_RXD0_PAD RMII receive data line 0."+        "description": "GPIO29 is powered by VDD_IO_4 and its IO MUX functions are SPI2_D_PAD (F2) and GMAC_PHY_RXD0_PAD (F3, Ethernet receive data line 0)."       },       {         "number": "59",         "name": "VDD_PSRAM_0",         "type": "power_in",-        "description": "VDD_PSRAM_0 is the PSRAM IO supply, recommended at 1.65 V to 1.95 V (typ. 1.8 V)."+        "description": "PSRAM IO supply; recommended input voltage is 1.65 V to 1.95 V (typ. 1.8 V)."       },       {         "number": "60",         "name": "GPIO30",         "type": "bidirectional",-        "description": "GPIO30 is an HP IO powered from VDD_IO_4 that carries the SPI2_CK_PAD clock and the GMAC_PHY_RXD1_PAD RMII receive data line 1."+        "description": "GPIO30 is powered by VDD_IO_4 and its IO MUX functions are SPI2_CK_PAD (F2) and GMAC_PHY_RXD1_PAD (F3, Ethernet receive data line 1)."       },       {         "number": "61",         "name": "GPIO31",         "type": "bidirectional",-        "description": "GPIO31 is an HP IO powered from VDD_IO_4 that carries the SPI2_Q_PAD data output and the GMAC_PHY_RXER_PAD receive error input."+        "description": "GPIO31 is powered by VDD_IO_4 and its IO MUX functions are SPI2_Q_PAD (F2) and GMAC_PHY_RXER_PAD (F3, Ethernet receive error)."       },       {         "number": "62",         "name": "VDD_IO_4",         "type": "power_in",-        "description": "VDD_IO_4 is the digital IO power supply for the HP IO group, recommended at 1.65 V to 3.6 V (typ. 3.3 V)."+        "description": "Digital power domain supply for HP IOs; recommended input voltage is 1.65 V to 3.6 V (typ. 3.3 V)."       },       {         "number": "63",         "name": "GPIO32",         "type": "bidirectional",-        "description": "GPIO32 is an HP IO powered from VDD_IO_4 with input enabled at reset, carrying the SPI2_HOLD_PAD signal, the GMAC_RMII_CLK_PAD RMII clock and the I3C clock/data routing option."+        "description": "GPIO32 is powered by VDD_IO_4 with input enabled at reset, and its IO MUX functions are SPI2_HOLD_PAD (F2) and GMAC_RMII_CLK_PAD (F3)."       },       {         "number": "64",         "name": "GPIO33",         "type": "bidirectional",-        "description": "GPIO33 is an HP IO powered from VDD_IO_4 with input enabled at reset, carrying the SPI2_WP_PAD write protect and the GMAC_PHY_TXEN_PAD transmit enable output."+        "description": "GPIO33 is powered by VDD_IO_4 with input enabled at reset, and its IO MUX functions are SPI2_WP_PAD (F2) and GMAC_PHY_TXEN_PAD (F3, Ethernet transmit enable)."       },       {         "number": "65",         "name": "GPIO34",         "type": "bidirectional",-        "description": "GPIO34 is an HP IO powered from VDD_IO_4 with input enabled at reset, carrying the SPI2_IO4_PAD signal and the GMAC_PHY_TXD0_PAD transmit data output, and is the JTAG-source strapping pin."+        "description": "GPIO34 is powered by VDD_IO_4 with input enabled at reset and is a strapping pin that selects the JTAG signal source (floating by default); its IO MUX functions are SPI2_IO4_PAD (F2) and GMAC_PHY_TXD0_PAD (F3)."       },       {         "number": "66",         "name": "GPIO35",         "type": "bidirectional",-        "description": "GPIO35 is an HP IO powered from VDD_IO_4 with input enabled and weak pull-up at reset, carrying the SPI2_IO5_PAD signal and the GMAC_PHY_TXD1_PAD output, and is a chip boot-mode strapping pin."+        "description": "GPIO35 is powered by VDD_IO_4 with input enabled and weak pull-up enabled at reset, and is a chip boot mode strapping pin (weak pull-up, bit value 1 by default); its IO MUX functions are SPI2_IO5_PAD (F2) and GMAC_PHY_TXD1_PAD (F3)."       },       {         "number": "67",         "name": "VDD_PSRAM_1",         "type": "power_in",-        "description": "VDD_PSRAM_1 is the PSRAM IO supply, recommended at 1.65 V to 1.95 V (typ. 1.8 V)."+        "description": "PSRAM IO supply; recommended input voltage is 1.65 V to 1.95 V (typ. 1.8 V)."       },       {         "number": "68",         "name": "GPIO36",         "type": "bidirectional",-        "description": "GPIO36 is an HP IO powered from VDD_IO_4 with input enabled at reset, carrying the SPI2_IO6_PAD signal and the GMAC_PHY_TXER_PAD output, and is a ROM message-printing strapping pin."+        "description": "GPIO36 is powered by VDD_IO_4 with input enabled at reset and is a strapping pin for ROM message printing (floating by default); its IO MUX functions are SPI2_IO6_PAD (F2) and GMAC_PHY_TXER_PAD (F3)."       },       {         "number": "69",         "name": "GPIO37",         "type": "bidirectional",-        "description": "GPIO37 is an HP IO powered from VDD_IO_4 that carries the UART0_TXD_PAD transmit output and the SPI2_IO7_PAD signal, and is a boot-mode strapping pin."+        "description": "GPIO37 is powered by VDD_IO_4 and is a chip boot mode strapping pin; its IO MUX functions are UART0_TXD_PAD (F0) and SPI2_IO7_PAD (F2)."       },       {         "number": "70",         "name": "GPIO38",         "type": "bidirectional",-        "description": "GPIO38 is an HP IO powered from VDD_IO_4 with input enabled, carrying the UART0_RXD_PAD receive input and the SPI2_DQS_PAD data strobe, and is a boot-mode strapping pin."+        "description": "GPIO38 is powered by VDD_IO_4 with input enabled at reset and is a chip boot mode strapping pin; its IO MUX functions are UART0_RXD_PAD (F0) and SPI2_DQS_PAD (F2)."       },       {         "number": "71",         "name": "VDDO_FLASH",         "type": "power_out",-        "description": "VDDO_FLASH is a regulated output supply for the off-package flash, rated at 50 mA maximum."+        "description": "Regulated output rail for off-package flash, supplying up to 50 mA at maximum."       },       {         "number": "72",         "name": "VDDO_PSRAM",         "type": "power_out",-        "description": "VDDO_PSRAM is a regulated output supply for in-package and off-package PSRAM, rated at 50 mA maximum."+        "description": "Regulated output rail for in-package and off-package PSRAM, supplying up to 50 mA at maximum."       },       {         "number": "73",         "name": "VDDO_3",         "type": "power_out",-        "description": "VDDO_3 is a regulated output supply rated at 50 mA maximum."+        "description": "Regulated output rail, supplying up to 50 mA at maximum."       },       {         "number": "74",         "name": "VDDO_4",         "type": "power_out",-        "description": "VDDO_4 is a regulated output supply rated at 50 mA maximum."+        "description": "Regulated output rail, supplying up to 50 mA at maximum."       },       {         "number": "75",         "name": "VDD_LDO",         "type": "power_in",-        "description": "VDD_LDO is the analog power domain supply for the internal LDOs, recommended at 3.0 V to 3.6 V (typ. 3.3 V)."+        "description": "Analog power domain supply for the LDOs; recommended input voltage is 3.0 V to 3.6 V (typ. 3.3 V)."       },       {         "number": "76",         "name": "VDD_HP_2",         "type": "power_in",-        "description": "VDD_HP_2 is a digital core supply, recommended at 0.99 V to 1.3 V (typ. 1.1 V)."+        "description": "Digital power domain supply; recommended input voltage is 0.99 V to 1.3 V (typ. 1.1 V)."       },       {         "number": "77",         "name": "VDD_DCDCC",         "type": "power_in",-        "description": "VDD_DCDCC is the analog power supply for the DC/DC control circuit, recommended at 3.0 V to 3.6 V (typ. 3.3 V)."+        "description": "Analog power domain supply for DC/DC control; recommended input voltage is 3.0 V to 3.6 V (typ. 3.3 V)."       },       {         "number": "78",         "name": "FB_DCDC",         "type": "passive",-        "description": "FB_DCDC is the feedback pin of the external DC/DC supply, which regulates VDD_HP_0/2/3 together with external feedback resistors."+        "description": "Feedback pin of the external DC/DC power supply, which regulates VDD_HP_0/2/3 together with feedback resistors."       },       {         "number": "79",         "name": "EN_DCDC",         "type": "output",-        "description": "EN_DCDC is the enable output pin for the external DC/DC converter."+        "description": "Enable pin of the external DC/DC converter."       },       {         "number": "80",         "name": "GPIO39",         "type": "bidirectional",-        "description": "GPIO39 is an HP IO powered from VDD_IO_5 that carries the SD1_CDATA0_PAD SDIO data line and the REF_50M_CLK_PAD 50 MHz clock output."+        "description": "GPIO39 is powered by VDD_IO_5 and its IO MUX functions are SD1_CDATA0_PAD (F0) and REF_50M_CLK_PAD (F3, 50 MHz reference clock output)."       },       {         "number": "81",         "name": "GPIO40",         "type": "bidirectional",-        "description": "GPIO40 is an HP IO powered from VDD_IO_5 that carries the SD1_CDATA1_PAD SDIO data line and the GMAC_PHY_TXEN_PAD transmit enable output."+        "description": "GPIO40 is powered by VDD_IO_5 and its IO MUX functions are SD1_CDATA1_PAD (F0) and GMAC_PHY_TXEN_PAD (F3)."       },       {         "number": "82",         "name": "GPIO41",         "type": "bidirectional",-        "description": "GPIO41 is an HP IO powered from VDD_IO_5 that carries the SD1_CDATA2_PAD SDIO data line and the GMAC_PHY_TXD0_PAD transmit data output."+        "description": "GPIO41 is powered by VDD_IO_5 and its IO MUX functions are SD1_CDATA2_PAD (F0) and GMAC_PHY_TXD0_PAD (F3)."       },       {         "number": "83",         "name": "GPIO42",         "type": "bidirectional",-        "description": "GPIO42 is an HP IO powered from VDD_IO_5 that carries the SD1_CDATA3_PAD SDIO data line and the GMAC_PHY_TXD1_PAD transmit data output."+        "description": "GPIO42 is powered by VDD_IO_5 and its IO MUX functions are SD1_CDATA3_PAD (F0) and GMAC_PHY_TXD1_PAD (F3)."       },       {         "number": "84",         "name": "GPIO43",         "type": "bidirectional",-        "description": "GPIO43 is an HP IO powered from VDD_IO_5 that carries the SD1_CCLK_PAD SDIO card clock output and the GMAC_PHY_TXER_PAD transmit error output."+        "description": "GPIO43 is powered by VDD_IO_5 and its IO MUX functions are SD1_CCLK_PAD (F0) and GMAC_PHY_TXER_PAD (F3)."       },       {         "number": "85",         "name": "VDD_IO_5",         "type": "power_in",-        "description": "VDD_IO_5 is the digital IO power supply for the HP IO group, recommended at 1.65 V to 3.6 V (typ. 3.3 V)."+        "description": "Digital power domain supply for HP IOs; recommended input voltage is 1.65 V to 3.6 V (typ. 3.3 V)."       },       {         "number": "86",         "name": "GPIO44",         "type": "bidirectional",-        "description": "GPIO44 is an HP IO powered from VDD_IO_5 that carries the SD1_CCMD_PAD SDIO command line and the GMAC_RMII_CLK_PAD RMII clock input."+        "description": "GPIO44 is powered by VDD_IO_5 and its IO MUX functions are SD1_CCMD_PAD (F0) and GMAC_RMII_CLK_PAD (F3)."       },       {         "number": "87",         "name": "GPIO45",         "type": "bidirectional",-        "description": "GPIO45 is an HP IO powered from VDD_IO_5 that carries the SD1_CDATA4_PAD SDIO data line and the GMAC_PHY_RXDV_PAD receive data valid input."+        "description": "GPIO45 is powered by VDD_IO_5 and its IO MUX functions are SD1_CDATA4_PAD (F0) and GMAC_PHY_RXDV_PAD (F3)."       },       {         "number": "88",         "name": "GPIO46",         "type": "bidirectional",-        "description": "GPIO46 is an HP IO powered from VDD_IO_5 that carries the SD1_CDATA5_PAD SDIO data line and the GMAC_PHY_RXD0_PAD receive data input."+        "description": "GPIO46 is powered by VDD_IO_5 and its IO MUX functions are SD1_CDATA5_PAD (F0) and GMAC_PHY_RXD0_PAD (F3)."       },       {         "number": "89",         "name": "GPIO47",         "type": "bidirectional",-        "description": "GPIO47 is an HP IO powered from VDD_IO_5 that carries the SD1_CDATA6_PAD SDIO data line and the GMAC_PHY_RXD1_PAD receive data input."+        "description": "GPIO47 is powered by VDD_IO_5 and its IO MUX functions are SD1_CDATA6_PAD (F0) and GMAC_PHY_RXD1_PAD (F3)."       },       {         "number": "90",         "name": "GPIO48",         "type": "bidirectional",-        "description": "GPIO48 is an HP IO powered from VDD_IO_5 that carries the SD1_CDATA7_PAD SDIO data line and the GMAC_PHY_RXER_PAD receive error input."+        "description": "GPIO48 is powered by VDD_IO_5 and its IO MUX functions are SD1_CDATA7_PAD (F0) and GMAC_PHY_RXER_PAD (F3)."       },       {         "number": "91",         "name": "VDD_HP_3",         "type": "power_in",-        "description": "VDD_HP_3 is a digital core supply, recommended at 0.99 V to 1.3 V (typ. 1.1 V)."+        "description": "Digital power domain supply; recommended input voltage is 0.99 V to 1.3 V (typ. 1.1 V)."       },       {         "number": "92",         "name": "GPIO49",         "type": "bidirectional",-        "description": "GPIO49 is an HP IO powered from VDD_IO_6 that carries the ADC2_CHANNEL0 analog input and the GMAC_PHY_TXEN_PAD transmit enable output."+        "description": "GPIO49 is powered by VDD_IO_6 and provides analog ADC2_CHANNEL0 and IO MUX GMAC_PHY_TXEN_PAD (F3)."       },       {         "number": "93",         "name": "GPIO50",         "type": "bidirectional",-        "description": "GPIO50 is an HP IO powered from VDD_IO_6 that carries the ADC2_CHANNEL1 analog input and the GMAC_RMII_CLK_PAD RMII clock input."+        "description": "GPIO50 is powered by VDD_IO_6 and provides analog ADC2_CHANNEL1 and IO MUX GMAC_RMII_CLK_PAD (F3)."       },       {         "number": "94",         "name": "GPIO51",         "type": "bidirectional",-        "description": "GPIO51 is an HP IO powered from VDD_IO_6 that carries the ADC2_CHANNEL2 and ANA_COMP0 analog functions and the GMAC_PHY_RXDV_PAD receive data valid input."+        "description": "GPIO51 is powered by VDD_IO_6 and provides analog ADC2_CHANNEL2 and ANA_COMP0, and IO MUX GMAC_PHY_RXDV_PAD (F3)."       },       {         "number": "95",         "name": "GPIO52",         "type": "bidirectional",-        "description": "GPIO52 is an HP IO powered from VDD_IO_6 that carries the ADC2_CHANNEL3 and ANA_COMP0 analog functions and the GMAC_PHY_RXD0_PAD receive data input."+        "description": "GPIO52 is powered by VDD_IO_6 and provides analog ADC2_CHANNEL3 and ANA_COMP0, and IO MUX GMAC_PHY_RXD0_PAD (F3)."       },       {         "number": "96",         "name": "VDD_IO_6",         "type": "power_in",-        "description": "VDD_IO_6 is the digital IO power supply for the HP IO group, recommended at 1.65 V to 3.6 V (typ. 3.3 V)."+        "description": "Digital power domain supply for HP IOs; recommended input voltage is 1.65 V to 3.6 V (typ. 3.3 V)."       },       {         "number": "97",         "name": "GPIO53",         "type": "bidirectional",-        "description": "GPIO53 is an HP IO powered from VDD_IO_6 that carries the ADC2_CHANNEL4 and ANA_COMP1 analog functions and the GMAC_PHY_RXD1_PAD receive data input."+        "description": "GPIO53 is powered by VDD_IO_6 and provides analog ADC2_CHANNEL4 and ANA_COMP1, and IO MUX GMAC_PHY_RXD1_PAD (F3)."       },       {         "number": "98",         "name": "GPIO54",         "type": "bidirectional",-        "description": "GPIO54 is an HP IO powered from VDD_IO_6 that carries the ADC2_CHANNEL5 and ANA_COMP1 analog functions and the GMAC_PHY_RXER_PAD receive error input."+        "description": "GPIO54 is powered by VDD_IO_6 and provides analog ADC2_CHANNEL5 and ANA_COMP1, and IO MUX GMAC_PHY_RXER_PAD (F3)."       },       {         "number": "99",         "name": "XTAL_N",         "type": "passive",-        "description": "XTAL_N is the negative side of the differential clock connection to the chip's crystal or oscillator."+        "description": "Differential negative external clock input/output connected to the chip's crystal or oscillator."       },       {         "number": "100",         "name": "XTAL_P",         "type": "passive",-        "description": "XTAL_P is the positive side of the differential clock connection to the chip's crystal or oscillator."+        "description": "Differential positive external clock input/output connected to the chip's crystal or oscillator."       },       {         "number": "101",         "name": "VDD_ANA",         "type": "power_in",-        "description": "VDD_ANA is the analog power domain supply, recommended at 3.0 V to 3.6 V (typ. 3.3 V)."+        "description": "Analog power domain supply; recommended input voltage is 3.0 V to 3.6 V (typ. 3.3 V)."       },       {         "number": "102",         "name": "VDD_BAT",         "type": "power_in",-        "description": "VDD_BAT is the analog power domain supply that can optionally connect to an external battery, recommended at 2.5 V to 3.6 V (typ. 3.3 V)."+        "description": "Analog power domain supply that can optionally connect to an external battery; recommended input voltage is 2.5 V to 3.6 V (typ. 3.3 V)."       },       {         "number": "103",         "name": "CHIP_PU",         "type": "input",-        "description": "CHIP_PU is the chip enable input: high enables the chip and low powers it down, and it must not be left floating."+        "description": "Chip enable: high enables the chip (powered up), low disables it (powered down), and the pin must not be left floating."       },       {         "number": "104",         "name": "GPIO0",         "type": "bidirectional",-        "description": "GPIO0 is an LP IO powered from VDD_LP/VDD_BAT that carries the XTAL_32K_N analog function and LP_GPIO0."+        "description": "GPIO0 is powered by VDD_LP/VDD_BAT, provides IO MUX GPIO function, LP_GPIO0 and analog XTAL_32K_N."       },       {         "number": "105",         "name": "GND",         "type": "power_in",-        "description": "GND is the external ground connection pin."+        "description": "External ground connection (exposed pad)."       }     ],     "provenance": {@@ -688,12 +688,11 @@         "consensus": "agreed",         "guards": "pin_guards 0.1: passed",         "guard_notes": [-          "extractor flagged: The datasheet marks ESP32-P4NRW32 as End of life (EOL), upgraded to ESP32-P4NRW32X, and refers to th; The datasheet pin table (Table 2-1 and Appendix A) lists the QFN104 package for this series. The pac; Pin 30 is named VDD_FLASHIO in Table 2-1 and Figure 2-1, but Table 2-11 writes VDD_FLASHIO2 with a f",-          "9/105 pins cited to the wrong page (name found elsewhere): ['9:VDD_LP@p79', '21:VDD_IO_0@p79', '30:VDD_FLASHIO@p79', '41:VDD_MIPI_DPHY@p79']"+          "extractor flagged: MPN ESP32-P4NRW32 is marked End of life (EOL) in the datasheet and is upgraded to ESP32-P4NRW32X; co; Pin 30 is named VDD_FLASHIO in Table 2-1 and Table 2-11 but written as VDD_FLASHIO2 in the Table 2-1; EN_DCDC (pin 79) is typed 'Analog' in Table 2-1 but 'O' (output) in Table 2-10; output was used. FB_"         ],         "pages_sent": 53,-        "cost_usd": 0.2825,-        "at": "2026-10-28T19:12:25"+        "cost_usd": 0.1085,+        "at": "2026-10-28T19:26:23"       },       "datasheet": {         "url": "https://www.espressif.com/sites/default/files/documentation/esp32-p4-chip-revision-v1.3_datasheet_en.pdf",@@ -729,7 +728,7 @@         "zmin_mm": 0,         "centre_offset_mm": 0,         "footprint_binding": "none",-        "sha256": "457ab6b63d8e996dbb736b913bc7e8e932306d4c484c72ca3c2c8c8418cd18a8",+        "sha256": "254f1f267e61a0f8af253946e3650817a1b84b20d3a060157191e18b3fc57f84",         "checked": "2026-10-28",         "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"       },@@ -748,7 +747,7 @@         "zmin_mm": 0,         "centre_offset_mm": 0,         "footprint_binding": "none",-        "sha256": "4c84a2b1fdb66dfa038957de4bc65ed976e3e63b5fd37b1524e854a4d58def9a",+        "sha256": "05248e5caf5986f22caae7d75e05e2bbc851c4bdd8c11bb4c8fa6cfb365ecd54",         "checked": "2026-10-28",         "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"       }@@ -1262,7 +1261,7 @@     "esp32-p4nrw32-hero.overlay.json",     "esp32-p4nrw32-etched.glb"   ],-  "visibility": {-    "public": true-  }+  "visibility": "public",+  "description": "ESPRESSIF Functional Modules, QFN-104(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D. Chip revision v1.x; ESP32-P4NRW32X is the newer revision (v3.x).",+  "org": "adom" }\ No newline at end of file