ESP32-P4NRW32

@@ -8,110 +8,110 @@ ESP32-P4NRW32 from ESPRESSIF, in a QFN-104(10x10). Pinout and pin descriptions e  | Pin | Name | Type | Function | |---|---|---|---|-| 1 | GPIO1 | bidirectional | IO pin powered by VDD_LP/VDD_BAT with IO MUX, LP IO MUX and XTAL_32K_P analog functions, default drive strength 20 mA. |-| 2 | GPIO2 | bidirectional | IO pin powered by VDD_LP/VDD_BAT, input enabled with weak pull-up at reset, used as MTCK and TOUCH_CHANNEL1, default drive strength 20 mA. |-| 3 | GPIO3 | bidirectional | IO pin powered by VDD_LP/VDD_BAT, input enabled at reset, used as MTDI (JTAG) and TOUCH_CHANNEL2, default drive strength 20 mA. |-| 4 | GPIO4 | bidirectional | IO pin powered by VDD_LP, input enabled at reset, used as MTMS (JTAG) and TOUCH_CHANNEL3, default drive strength 20 mA. |-| 5 | GPIO5 | bidirectional | IO pin powered by VDD_LP, used as MTDO (JTAG) and TOUCH_CHANNEL4, default drive strength 20 mA. |-| 6 | GPIO6 | bidirectional | IO pin powered by VDD_LP, with TOUCH_CHANNEL5 analog function and SPI2_HOLD_PAD on IO MUX F2, default drive strength 20 mA. |-| 7 | GPIO7 | bidirectional | IO pin powered by VDD_LP, with TOUCH_CHANNEL6 analog function and SPI2_CS_PAD on IO MUX F2, default drive strength 20 mA. |-| 8 | GPIO8 | bidirectional | IO pin powered by VDD_LP, with TOUCH_CHANNEL7, UART0_RTS_PAD and SPI2_D_PAD functions, default drive strength 20 mA. |-| 9 | VDD_LP | power_in | LP power domain supply pin; recommended input voltage 3.0 to 3.6 V and allowed input voltage -0.3 to 3.6 V. |-| 10 | GPIO9 | bidirectional | IO pin powered by VDD_LP, with TOUCH_CHANNEL8, UART0_CTS_PAD and SPI2_CK_PAD functions, default drive strength 20 mA. |-| 11 | GPIO10 | bidirectional | IO pin powered by VDD_LP, with TOUCH_CHANNEL9, UART1_TXD_PAD and SPI2_Q_PAD functions, default drive strength 20 mA. |-| 12 | GPIO11 | bidirectional | IO pin powered by VDD_LP, with TOUCH_CHANNEL10, UART1_RXD_PAD and SPI2_WP_PAD functions, default drive strength 20 mA. |-| 13 | GPIO12 | bidirectional | IO pin powered by VDD_LP, with TOUCH_CHANNEL11 and UART1_RTS_PAD functions, default drive strength 20 mA. |-| 14 | GPIO13 | bidirectional | IO pin powered by VDD_LP, with TOUCH_CHANNEL12 and UART1_CTS_PAD functions, default drive strength 20 mA. |-| 15 | GPIO14 | bidirectional | IO pin powered by VDD_LP, with TOUCH_CHANNEL13 and LP_UART_TXD_PAD functions, default drive strength 20 mA. |-| 16 | GPIO15 | bidirectional | IO pin powered by VDD_LP, with TOUCH_CHANNEL14 and LP_UART_RXD_PAD functions, default drive strength 20 mA. |-| 17 | GPIO16 | bidirectional | IO pin powered by VDD_IO_0, with ADC1_CHANNEL0 analog function, default drive strength 20 mA. |-| 18 | GPIO17 | bidirectional | IO pin powered by VDD_IO_0, with ADC1_CHANNEL1 analog function, default drive strength 20 mA. |-| 19 | GPIO18 | bidirectional | IO pin powered by VDD_IO_0, with ADC1_CHANNEL2 analog function, default drive strength 20 mA. |-| 20 | GPIO19 | bidirectional | IO pin powered by VDD_IO_0, with ADC1_CHANNEL3 analog function, default drive strength 20 mA. |-| 21 | VDD_IO_0 | power_in | Digital power domain supply for HP IO pins GPIO16 to GPIO23; recommended input voltage 1.65 to 3.6 V. |-| 22 | GPIO20 | bidirectional | IO pin powered by VDD_IO_0, with ADC1_CHANNEL4 analog function, default drive strength 20 mA. |-| 23 | GPIO21 | bidirectional | IO pin powered by VDD_IO_0, with ADC1_CHANNEL5 analog function, default drive strength 20 mA. |-| 24 | GPIO22 | bidirectional | IO pin powered by VDD_IO_0, with ADC1_CHANNEL6 analog function, default drive strength 20 mA. |-| 25 | GPIO23 | bidirectional | IO pin powered by VDD_IO_0, with ADC1_CHANNEL7 analog function and REF_50M_CLK_PAD output on IO MUX F2, default drive strength 20 mA. |-| 26 | VDD_HP_0 | power_in | Digital power domain supply pin regulated by the external DC/DC via FB_DCDC; allowed input voltage 0 to 1.3 V. |-| 27 | FLASH_CS | output | Dedicated chip-select output to off-package flash, powered by VDD_FLASHIO. |-| 28 | FLASH_Q | bidirectional | Dedicated flash data-output (DO) pin to off-package flash, powered by VDD_FLASHIO. |-| 29 | FLASH_WP | bidirectional | Dedicated flash write-protect (WP#) pin to off-package flash, powered by VDD_FLASHIO. |-| 30 | VDD_FLASHIO | power_in | Power supply for flash IO pins; the voltage should be adjusted to the flash model, with 3.3 V flash used as the example in the datasheet. |-| 31 | FLASH_HOLD | bidirectional | Dedicated flash HOLD# pin to off-package flash, powered by VDD_FLASHIO. |-| 32 | FLASH_CK | output | Dedicated flash clock output to off-package flash, powered by VDD_FLASHIO. |-| 33 | FLASH_D | bidirectional | Dedicated flash data-input (DI) pin to off-package flash, powered by VDD_FLASHIO. |-| 34 | DSI_REXT | bidirectional | MIPI DSI PHY external 4.02 kΩ reference resistor pin, powered by VDD_MIPI_DPHY. |-| 35 | DSI_DATAP1 | bidirectional | MIPI DSI PHY data positive channel 1 pin, powered by VDD_MIPI_DPHY. |-| 36 | DSI_DATAN1 | bidirectional | MIPI DSI PHY data negative channel 1 pin, powered by VDD_MIPI_DPHY. |-| 37 | DSI_CLKN | bidirectional | MIPI DSI PHY clock negative pin, powered by VDD_MIPI_DPHY. |-| 38 | DSI_CLKP | bidirectional | MIPI DSI PHY clock positive pin, powered by VDD_MIPI_DPHY. |-| 39 | DSI_DATAP0 | bidirectional | MIPI DSI PHY data positive channel 0 pin, powered by VDD_MIPI_DPHY. |-| 40 | DSI_DATAN0 | bidirectional | MIPI DSI PHY data negative channel 0 pin, powered by VDD_MIPI_DPHY. |-| 41 | VDD_MIPI_DPHY | power_in | Supply for the MIPI PHY pins; allowed input voltage 0 to 2.75 V. |-| 42 | CSI_DATAN0 | bidirectional | MIPI CSI PHY data negative channel 0 pin, powered by VDD_MIPI_DPHY. |-| 43 | CSI_DATAP0 | bidirectional | MIPI CSI PHY data positive channel 0 pin, powered by VDD_MIPI_DPHY. |-| 44 | CSI_CLKP | bidirectional | MIPI CSI PHY clock positive pin, powered by VDD_MIPI_DPHY. |-| 45 | CSI_CLKN | bidirectional | MIPI CSI PHY clock negative pin, powered by VDD_MIPI_DPHY. |-| 46 | CSI_DATAN1 | bidirectional | MIPI CSI PHY data negative channel 1 pin, powered by VDD_MIPI_DPHY. |-| 47 | CSI_DATAP1 | bidirectional | MIPI CSI PHY data positive channel 1 pin, powered by VDD_MIPI_DPHY. |-| 48 | CSI_REXT | bidirectional | MIPI CSI PHY external 4.02 kΩ reference resistor pin, powered by VDD_MIPI_DPHY. |-| 49 | USB_DM | bidirectional | USB 2.0 High-Speed OTG PHY D- pin, powered by VDD_USBPHY. |-| 50 | USB_DP | bidirectional | USB 2.0 High-Speed OTG PHY D+ pin, powered by VDD_USBPHY. |-| 51 | VDD_USBPHY | power_in | Supply for the USB PHY pins; allowed input voltage -0.66 to 3.96 V. |-| 52 | GPIO24 | bidirectional | IO pin powered by VDD_IO_4 with USB1P1_N0 analog function, default drive strength 40 mA. |-| 53 | GPIO25 | bidirectional | IO pin powered by VDD_IO_4 with USB1P1_P0 analog function, default drive strength 40 mA. |-| 54 | VDD_HP_1 | power_in | Digital power domain supply pin regulated by the external DC/DC via FB_DCDC; allowed input voltage 0 to 1.3 V. |-| 55 | GPIO26 | bidirectional | IO pin powered by VDD_IO_4 with USB1P1_N1 analog function, default drive strength 20 mA. |-| 56 | GPIO27 | bidirectional | IO pin powered by VDD_IO_4 with USB1P1_P1 analog function, default drive strength 20 mA. |-| 57 | GPIO28 | bidirectional | IO pin powered by VDD_IO_4 with SPI2_CS_PAD and GMAC_PHY_RXDV_PAD functions, default drive strength 20 mA. |-| 58 | GPIO29 | bidirectional | IO pin powered by VDD_IO_4 with SPI2_D_PAD and GMAC_PHY_RXD0_PAD functions, default drive strength 20 mA. |-| 59 | VDD_PSRAM_0 | power_in | PSRAM power supply pin; recommended input voltage 1.65 to 1.95 V for the 1.8 V PSRAM. |-| 60 | GPIO30 | bidirectional | IO pin powered by VDD_IO_4 with SPI2_CK_PAD and GMAC_PHY_RXD1_PAD functions, default drive strength 20 mA. |-| 61 | GPIO31 | bidirectional | IO pin powered by VDD_IO_4 with SPI2_Q_PAD and GMAC_PHY_RXER_PAD functions, default drive strength 20 mA. |-| 62 | VDD_IO_4 | power_in | Digital power domain supply for HP IO pins GPIO24 to GPIO38; recommended input voltage 1.65 to 3.6 V. |-| 63 | GPIO32 | bidirectional | IO pin powered by VDD_IO_4, input enabled at reset, with SPI2_HOLD_PAD, I3C_MST_SCL_PAD (configurable pull-up) and GMAC_RMII_CLK_PAD functions. |-| 64 | GPIO33 | bidirectional | IO pin powered by VDD_IO_4, input enabled at reset, with SPI2_WP_PAD, I3C_MST_SDA_PAD (configurable pull-up) and GMAC_PHY_TXEN_PAD functions. |-| 65 | GPIO34 | bidirectional | IO pin powered by VDD_IO_4, input enabled at reset, a strapping pin for JTAG signal source control, with SPI2_IO4_PAD and GMAC_PHY_TXD0_PAD functions. |-| 66 | GPIO35 | bidirectional | IO pin powered by VDD_IO_4, input enabled with weak pull-up at reset, a strapping pin for chip boot mode, with SPI2_IO5_PAD and GMAC_PHY_TXD1_PAD functions. |-| 67 | VDD_PSRAM_1 | power_in | PSRAM power supply pin; recommended input voltage 1.65 to 1.95 V for the 1.8 V PSRAM. |-| 68 | GPIO36 | bidirectional | IO pin powered by VDD_IO_4, input enabled at reset, a strapping pin for ROM message printing control, with SPI2_IO6_PAD and GMAC_PHY_TXER_PAD functions. |-| 69 | GPIO37 | bidirectional | IO pin powered by VDD_IO_4, a strapping pin for chip boot mode, with UART0_TXD_PAD and SPI2_IO7_PAD functions. |-| 70 | GPIO38 | bidirectional | IO pin powered by VDD_IO_4, input enabled at reset, a strapping pin for chip boot mode, with UART0_RXD_PAD and SPI2_DQS_PAD functions. |-| 71 | VDDO_FLASH | power_out | Output supply for off-package flash, delivering up to 50 mA at maximum. |-| 72 | VDDO_PSRAM | power_out | Output supply for in-package and off-package PSRAM, delivering up to 50 mA at maximum. |-| 73 | VDDO_3 | power_out | Output supply from a voltage regulator, delivering up to 50 mA at maximum. |-| 74 | VDDO_4 | power_out | Output supply from a voltage regulator, delivering up to 50 mA at maximum. |-| 75 | VDD_LDO | power_in | Analog power domain supply providing power for LDOs; recommended input voltage 3.0 to 3.6 V. |-| 76 | VDD_HP_2 | power_in | Digital power domain supply pin regulated by the external DC/DC via FB_DCDC; allowed input voltage 0 to 1.3 V. |-| 77 | VDD_DCDCC | power_in | Analog power domain supply for DC/DC control; recommended input voltage 3.0 to 3.6 V. |-| 78 | FB_DCDC | passive | Feedback pin of the external DC/DC supply, which regulates VDD_HP_0/1/2/3 together with feedback resistors. |-| 79 | EN_DCDC | output | Enable output pin for the external DC/DC converter. |-| 80 | GPIO39 | bidirectional | IO pin powered by VDD_IO_5 with SD1_CDATA0_PAD and REF_50M_CLK_PAD output functions. |-| 81 | GPIO40 | bidirectional | IO pin powered by VDD_IO_5 with SD1_CDATA1_PAD and GMAC_PHY_TXEN_PAD output functions. |-| 82 | GPIO41 | bidirectional | IO pin powered by VDD_IO_5 with SD1_CDATA2_PAD and GMAC_PHY_TXD0_PAD output functions. |-| 83 | GPIO42 | bidirectional | IO pin powered by VDD_IO_5 with SD1_CDATA3_PAD and GMAC_PHY_TXD1_PAD output functions. |-| 84 | GPIO43 | bidirectional | IO pin powered by VDD_IO_5 with SD1_CCLK_PAD and GMAC_PHY_TXER_PAD output functions. |-| 85 | VDD_IO_5 | power_in | Digital power domain supply for HP IO pins GPIO39 to GPIO48; recommended input voltage 1.65 to 3.6 V. |-| 86 | GPIO44 | bidirectional | IO pin powered by VDD_IO_5 with SD1_CCMD_PAD and GMAC_RMII_CLK_PAD functions. |-| 87 | GPIO45 | bidirectional | IO pin powered by VDD_IO_5 with SD1_CDATA4_PAD and GMAC_PHY_RXDV_PAD functions. |-| 88 | GPIO46 | bidirectional | IO pin powered by VDD_IO_5 with SD1_CDATA5_PAD and GMAC_PHY_RXD0_PAD functions. |-| 89 | GPIO47 | bidirectional | IO pin powered by VDD_IO_5 with SD1_CDATA6_PAD and GMAC_PHY_RXD1_PAD functions. |-| 90 | GPIO48 | bidirectional | IO pin powered by VDD_IO_5 with SD1_CDATA7_PAD and GMAC_PHY_RXER_PAD functions. |-| 91 | VDD_HP_3 | power_in | Digital power domain supply pin regulated by the external DC/DC via FB_DCDC; allowed input voltage 0 to 1.3 V. |-| 92 | GPIO49 | bidirectional | IO pin powered by VDD_IO_6 with ADC2_CHANNEL0 analog function and GMAC_PHY_TXEN_PAD output on IO MUX F2. |-| 93 | GPIO50 | bidirectional | IO pin powered by VDD_IO_6 with ADC2_CHANNEL1 analog function and GMAC_RMII_CLK_PAD on IO MUX F2. |-| 94 | GPIO51 | bidirectional | IO pin powered by VDD_IO_6 with ADC2_CHANNEL2, ANA_COMP0 analog function and GMAC_PHY_RXDV_PAD on IO MUX F2. |-| 95 | GPIO52 | bidirectional | IO pin powered by VDD_IO_6 with ADC2_CHANNEL3, ANA_COMP0 analog function and GMAC_PHY_RXD0_PAD on IO MUX F2. |-| 96 | VDD_IO_6 | power_in | Digital power domain supply for HP IO pins GPIO49 to GPIO54; recommended input voltage 1.65 to 3.6 V. |-| 97 | GPIO53 | bidirectional | IO pin powered by VDD_IO_6 with ADC2_CHANNEL4, ANA_COMP1 analog function and GMAC_PHY_RXD1_PAD on IO MUX F2. |-| 98 | GPIO54 | bidirectional | IO pin powered by VDD_IO_6 with ADC2_CHANNEL5, ANA_COMP1 analog function and GMAC_PHY_RXER_PAD on IO MUX F2. |-| 99 | XTAL_N | passive | External clock input/output connected to the chip's crystal or oscillator, negative side of the differential clock. |-| 100 | XTAL_P | passive | External clock input/output connected to the chip's crystal or oscillator, positive side of the differential clock. |-| 101 | VDD_ANA | power_in | Analog power domain supply; recommended input voltage 3.0 to 3.6 V. |-| 102 | VDD_BAT | power_in | Analog power domain supply, optionally connected to an external battery; recommended input voltage 2.5 to 3.6 V. |-| 103 | CHIP_PU | input | Chip enable: high enables the chip and low powers it down; the pin must not be left floating. |-| 104 | GPIO0 | bidirectional | IO pin powered by VDD_LP/VDD_BAT with XTAL_32K_N analog function and LP_GPIO0, default drive strength 20 mA. |+| 1 | GPIO1 | bidirectional | GPIO1 is powered by VDD_LP or VDD_BAT and also offers LP IO MUX and XTAL_32K_P analog functions. |+| 2 | GPIO2 | bidirectional | GPIO2 is powered by VDD_LP or VDD_BAT, has input enable and weak pull-up enabled at reset, and offers MTCK and touch channel 1. |+| 3 | GPIO3 | bidirectional | GPIO3 is powered by VDD_LP or VDD_BAT, has input enable at reset, and offers MTDI and touch channel 2. |+| 4 | GPIO4 | bidirectional | GPIO4 is powered by VDD_LP, has input enable at reset, and offers MTMS and touch channel 3. |+| 5 | GPIO5 | bidirectional | GPIO5 is powered by VDD_LP and offers the MTDO JTAG output and touch channel 4. |+| 6 | GPIO6 | bidirectional | GPIO6 is powered by VDD_LP and offers SPI2_HOLD and touch channel 5. |+| 7 | GPIO7 | bidirectional | GPIO7 is powered by VDD_LP and offers SPI2_CS and touch channel 6. |+| 8 | GPIO8 | bidirectional | GPIO8 is powered by VDD_LP and offers SPI2_D and touch channel 7. |+| 9 | VDD_LP | power_in | LP power domain supply input, recommended 3.0 to 3.6 V (3.3 V typ) per Table 5-2. |+| 10 | GPIO9 | bidirectional | GPIO9 is powered by VDD_LP and offers SPI2_CK and touch channel 8. |+| 11 | GPIO10 | bidirectional | GPIO10 is powered by VDD_LP and offers SPI2_Q and touch channel 9. |+| 12 | GPIO11 | bidirectional | GPIO11 is powered by VDD_LP and offers SPI2_WP and touch channel 10. |+| 13 | GPIO12 | bidirectional | GPIO12 is powered by VDD_LP and offers touch channel 11. |+| 14 | GPIO13 | bidirectional | GPIO13 is powered by VDD_LP and offers touch channel 12. |+| 15 | GPIO14 | bidirectional | GPIO14 is powered by VDD_LP and offers LP_UART_TXD and touch channel 13. |+| 16 | GPIO15 | bidirectional | GPIO15 is powered by VDD_LP and offers LP_UART_RXD and touch channel 14. |+| 17 | GPIO16 | bidirectional | GPIO16 is powered by VDD_IO_0 and offers ADC1_CHANNEL0 as an analog function. |+| 18 | GPIO17 | bidirectional | GPIO17 is powered by VDD_IO_0 and offers ADC1_CHANNEL1 as an analog function. |+| 19 | GPIO18 | bidirectional | GPIO18 is powered by VDD_IO_0 and offers ADC1_CHANNEL2 as an analog function. |+| 20 | GPIO19 | bidirectional | GPIO19 is powered by VDD_IO_0 and offers ADC1_CHANNEL3 as an analog function. |+| 21 | VDD_IO_0 | power_in | Digital HP IO supply for GPIO16 to GPIO23, recommended 1.65 to 3.6 V (3.3 V typ) per Table 5-2. |+| 22 | GPIO20 | bidirectional | GPIO20 is powered by VDD_IO_0 and offers ADC1_CHANNEL4 as an analog function. |+| 23 | GPIO21 | bidirectional | GPIO21 is powered by VDD_IO_0 and offers ADC1_CHANNEL5 as an analog function. |+| 24 | GPIO22 | bidirectional | GPIO22 is powered by VDD_IO_0 and offers ADC1_CHANNEL6 as an analog function. |+| 25 | GPIO23 | bidirectional | GPIO23 is powered by VDD_IO_0 and offers ADC1_CHANNEL7 and the REF_50M_CLK output. |+| 26 | VDD_HP_0 | power_in | HP digital core supply, recommended 0.99 to 1.3 V (1.1 V typ) per Table 5-2. |+| 27 | FLASH_CS | output | Dedicated chip-select output to the off-package flash, powered by VDD_FLASHIO. |+| 28 | FLASH_Q | bidirectional | Dedicated flash data output line (DO) for off-package flash, powered by VDD_FLASHIO. |+| 29 | FLASH_WP | bidirectional | Dedicated flash write-protect line (WP#) for off-package flash, powered by VDD_FLASHIO. |+| 30 | VDD_FLASHIO | power_in | Power supply for flash IO, which should be adjusted to the flash model (3.3 V flash used as the example). |+| 31 | FLASH_HOLD | bidirectional | Dedicated flash HOLD# line for off-package flash, powered by VDD_FLASHIO. |+| 32 | FLASH_CK | output | Dedicated flash clock output for off-package flash, powered by VDD_FLASHIO. |+| 33 | FLASH_D | bidirectional | Dedicated flash data input line (DI) for off-package flash, powered by VDD_FLASHIO. |+| 34 | DSI_REXT | bidirectional | Connects the external 4.02 kΩ reference resistor for the MIPI DSI PHY. |+| 35 | DSI_DATAP1 | bidirectional | MIPI DSI PHY positive data channel 1, powered by VDD_MIPI_DPHY. |+| 36 | DSI_DATAN1 | bidirectional | MIPI DSI PHY negative data channel 1, powered by VDD_MIPI_DPHY. |+| 37 | DSI_CLKN | bidirectional | MIPI DSI PHY negative clock channel, powered by VDD_MIPI_DPHY. |+| 38 | DSI_CLKP | bidirectional | MIPI DSI PHY positive clock channel, powered by VDD_MIPI_DPHY. |+| 39 | DSI_DATAP0 | bidirectional | MIPI DSI PHY positive data channel 0, powered by VDD_MIPI_DPHY. |+| 40 | DSI_DATAN0 | bidirectional | MIPI DSI PHY negative data channel 0, powered by VDD_MIPI_DPHY. |+| 41 | VDD_MIPI_DPHY | power_in | MIPI PHY supply, recommended 2.25 to 2.75 V (2.5 V typ) per Table 5-2. |+| 42 | CSI_DATAN0 | bidirectional | MIPI CSI PHY negative data channel 0, powered by VDD_MIPI_DPHY. |+| 43 | CSI_DATAP0 | bidirectional | MIPI CSI PHY positive data channel 0, powered by VDD_MIPI_DPHY. |+| 44 | CSI_CLKP | bidirectional | MIPI CSI PHY positive clock channel, powered by VDD_MIPI_DPHY. |+| 45 | CSI_CLKN | bidirectional | MIPI CSI PHY negative clock channel, powered by VDD_MIPI_DPHY. |+| 46 | CSI_DATAN1 | bidirectional | MIPI CSI PHY negative data channel 1, powered by VDD_MIPI_DPHY. |+| 47 | CSI_DATAP1 | bidirectional | MIPI CSI PHY positive data channel 1, powered by VDD_MIPI_DPHY. |+| 48 | CSI_REXT | bidirectional | Connects the external 4.02 kΩ reference resistor for the MIPI CSI PHY. |+| 49 | USB_DM | bidirectional | USB 2.0 OTG high-speed PHY D- signal, powered by VDD_USBPHY (2.97 to 3.63 V). |+| 50 | USB_DP | bidirectional | USB 2.0 OTG high-speed PHY D+ signal, powered by VDD_USBPHY (2.97 to 3.63 V). |+| 51 | VDD_USBPHY | power_in | USB PHY supply, recommended 2.97 to 3.63 V (3.3 V typ) per Table 5-2. |+| 52 | GPIO24 | bidirectional | GPIO24 is powered by VDD_IO_4 with a default drive strength of 40 mA and offers USB1P1_N0. |+| 53 | GPIO25 | bidirectional | GPIO25 is powered by VDD_IO_4 with a default drive strength of 40 mA, USB pull-up enabled at reset, and offers USB1P1_P0. |+| 54 | NC | unconnected | Pin is not connected (NC) in the package. |+| 55 | GPIO26 | bidirectional | GPIO26 is powered by VDD_IO_4 with a default drive strength of 20 mA and offers USB1P1_N1. |+| 56 | GPIO27 | bidirectional | GPIO27 is powered by VDD_IO_4 with a default drive strength of 20 mA and offers USB1P1_P1. |+| 57 | GPIO28 | bidirectional | GPIO28 is powered by VDD_IO_4 and offers SPI2_CS and the GMAC_PHY_RXDV input. |+| 58 | GPIO29 | bidirectional | GPIO29 is powered by VDD_IO_4 and offers SPI2_D and the GMAC_PHY_RXD0 input. |+| 59 | VDD_PSRAM_0 | power_in | In-package PSRAM supply, recommended 1.65 to 1.95 V (1.8 V typ) per Table 5-2. |+| 60 | GPIO30 | bidirectional | GPIO30 is powered by VDD_IO_4 and offers SPI2_CK and the GMAC_PHY_RXD1 input. |+| 61 | GPIO31 | bidirectional | GPIO31 is powered by VDD_IO_4 and offers SPI2_Q and the GMAC_PHY_RXER input. |+| 62 | VDD_IO_4 | power_in | Digital HP IO supply for GPIO24 to GPIO38, recommended 1.65 to 3.6 V (3.3 V typ) per Table 5-2. |+| 63 | GPIO32 | bidirectional | GPIO32 is powered by VDD_IO_4, has input enable at reset, and offers SPI2_HOLD and the GMAC_RMII_CLK input. |+| 64 | GPIO33 | bidirectional | GPIO33 is powered by VDD_IO_4, has input enable at reset, and offers SPI2_WP and the GMAC_PHY_TXEN output. |+| 65 | GPIO34 | bidirectional | GPIO34 is powered by VDD_IO_4 with input enable at reset, and is the strapping pin for the JTAG signal source control. |+| 66 | GPIO35 | bidirectional | GPIO35 is powered by VDD_IO_4 with input enable and weak pull-up at reset, and is the default-high strapping pin for boot mode control. |+| 67 | VDD_PSRAM_1 | power_in | In-package PSRAM supply, recommended 1.65 to 1.95 V (1.8 V typ) per Table 5-2. |+| 68 | GPIO36 | bidirectional | GPIO36 is powered by VDD_IO_4 with input enable at reset, and is the strapping pin for ROM message printing control. |+| 69 | GPIO37 | bidirectional | GPIO37 is powered by VDD_IO_4 with input enable at reset, a boot mode strapping pin, and offers the UART0_TXD output. |+| 70 | GPIO38 | bidirectional | GPIO38 is powered by VDD_IO_4 with input enable at reset, a boot mode strapping pin, and offers the UART0_RXD input. |+| 71 | VDDO_FLASH | power_out | Flash power output, 3.3 V by default or 1.8 V after EFUSE_0PXA_TIEH_SEL_0 is burnt, supplying up to 50 mA. |+| 72 | VDDO_PSRAM | power_out | Output rail for in-package and off-package PSRAM, supplying up to 50 mA. |+| 73 | VDDO_3 | power_out | VO3 LDO output rail for external devices, configurable 0.5 to 2.7 V or 3.3 V, supplying up to 50 mA. |+| 74 | VDDO_4 | power_out | VO4 LDO output rail for external devices, configurable 0.5 to 2.7 V or 3.3 V, supplying up to 50 mA. |+| 75 | VDD_LDO | power_in | Analog power domain input that provides power for the LDOs, recommended 3.0 to 3.6 V. |+| 76 | VDD_HP_2 | power_in | HP digital core supply, recommended 0.99 to 1.3 V (1.1 V typ) per Table 5-2. |+| 77 | VDD_DCDCC | power_in | Analog power domain input for DC/DC control, recommended 3.0 to 3.6 V. |+| 78 | FB_DCDC | passive | Feedback pin of the external DC/DC supply, which regulates VDD_HP_0/2/3 together with feedback resistors. |+| 79 | EN_DCDC | output | Enable output for the external DC/DC converter. |+| 80 | GPIO39 | bidirectional | GPIO39 is powered by VDD_IO_5 and offers SD1_CDATA0 and the REF_50M_CLK output. |+| 81 | GPIO40 | bidirectional | GPIO40 is powered by VDD_IO_5 and offers SD1_CDATA1 and the GMAC_PHY_TXEN output. |+| 82 | GPIO41 | bidirectional | GPIO41 is powered by VDD_IO_5 and offers SD1_CDATA2 and the GMAC_PHY_TXD0 output. |+| 83 | GPIO42 | bidirectional | GPIO42 is powered by VDD_IO_5 and offers SD1_CDATA3 and the GMAC_PHY_TXD1 output. |+| 84 | GPIO43 | bidirectional | GPIO43 is powered by VDD_IO_5 and offers the SD1_CCLK output and the GMAC_PHY_TXER output. |+| 85 | VDD_IO_5 | power_in | Digital HP IO supply for GPIO39 to GPIO48, recommended 1.65 to 3.6 V (3.3 V typ) per Table 5-2. |+| 86 | GPIO44 | bidirectional | GPIO44 is powered by VDD_IO_5 and offers SD1_CCMD and the GMAC_RMII_CLK input. |+| 87 | GPIO45 | bidirectional | GPIO45 is powered by VDD_IO_5 and offers SD1_CDATA4 and the GMAC_PHY_RXDV input. |+| 88 | GPIO46 | bidirectional | GPIO46 is powered by VDD_IO_5 and offers SD1_CDATA5 and the GMAC_PHY_RXD0 input. |+| 89 | GPIO47 | bidirectional | GPIO47 is powered by VDD_IO_5 and offers SD1_CDATA6 and the GMAC_PHY_RXD1 input. |+| 90 | GPIO48 | bidirectional | GPIO48 is powered by VDD_IO_5 and offers SD1_CDATA7 and the GMAC_PHY_RXER input. |+| 91 | VDD_HP_3 | power_in | HP digital core supply, recommended 0.99 to 1.3 V (1.1 V typ) per Table 5-2. |+| 92 | GPIO49 | bidirectional | GPIO49 is powered by VDD_IO_6, offers ADC2_CHANNEL0, and offers the GMAC_PHY_TXEN output. |+| 93 | GPIO50 | bidirectional | GPIO50 is powered by VDD_IO_6, offers ADC2_CHANNEL1, and offers the GMAC_RMII_CLK input. |+| 94 | GPIO51 | bidirectional | GPIO51 is powered by VDD_IO_6, offers ADC2_CHANNEL2, and offers ANA_COMP0. |+| 95 | GPIO52 | bidirectional | GPIO52 is powered by VDD_IO_6, offers ADC2_CHANNEL3, and offers ANA_COMP0. |+| 96 | VDD_IO_6 | power_in | Digital HP IO supply for GPIO49 to GPIO54, recommended 1.65 to 3.6 V (3.3 V typ) per Table 5-2. |+| 97 | GPIO53 | bidirectional | GPIO53 is powered by VDD_IO_6, offers ADC2_CHANNEL4, and offers ANA_COMP1. |+| 98 | GPIO54 | bidirectional | GPIO54 is powered by VDD_IO_6, offers ADC2_CHANNEL5, and offers ANA_COMP1. |+| 99 | XTAL_N | passive | Negative side of the external clock input/output connected to the chip crystal or oscillator (40 MHz XTAL_CLK). |+| 100 | XTAL_P | passive | Positive side of the external clock input/output connected to the chip crystal or oscillator (40 MHz XTAL_CLK). |+| 101 | VDD_ANA | power_in | Analog power domain supply, recommended 3.0 to 3.6 V. |+| 102 | VDD_BAT | power_in | Analog power domain input that can optionally connect to an external battery, recommended 2.5 to 3.6 V. |+| 103 | CHIP_PU | input | Chip enable: high powers up and enables the chip, low powers it down, and it must not be left floating. |+| 104 | GPIO0 | bidirectional | GPIO0 is powered by VDD_LP or VDD_BAT and also offers LP_GPIO0 and XTAL_32K_N analog function. | | 105 | GND | power_in | External ground connection. |  ## Key specifications@@ -129,47 +129,45 @@ Limits as printed in the datasheet (page.json `metadata.characteristics` carries  | Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page | |---|---|---|---|---|---|---|---|-| Allowed input voltage (VDD_LDO, VDD_DCDCC, VDD_ANA, VDD_BAT, VDD_LP) |  | -0.3 |  | 3.6 | V |  | 88 |-| Allowed input voltage (VDD_IO_0, VDD_FLASHIO, VDD_IO_4, VDD_IO_5, VDD_IO_6) |  | -0.3 |  | 3.6 | V |  | 88 |-| Allowed input voltage (VDD_PSRAM_0, VDD_PSRAM_1) |  | 1.62 |  | 1.98 | V |  | 88 |-| Allowed input voltage (VDD_HP_0, VDD_HP_1, VDD_HP_2, VDD_HP_3) |  | 0 |  | 1.3 | V |  | 88 |-| Allowed input voltage (VDD_MIPI_DPHY) |  | 0 |  | 2.75 | V |  | 88 |-| Allowed input voltage (VDD_USBPHY) |  | -0.66 |  | 3.96 | V |  | 88 |-| Cumulative IO output current | Ioutput |  |  | 1500 | mA |  | 88 |-| Storage temperature | TSTORE | -40 |  | 150 | °C |  | 88 |-| Recommended input voltage (VDD_LDO, VDD_DCDCC, VDD_ANA, VDD_LP) |  | 3 | 3.3 | 3.6 | V |  | 88 |-| Recommended input voltage (VDD_BAT) |  | 2.5 | 3.3 | 3.6 | V |  | 88 |-| Recommended input voltage (VDD_IO_0, VDD_FLASHIO, VDD_IO_4, VDD_IO_5, VDD_IO_6) |  | 1.65 | 1.8 | 3.6 | V |  | 88 |-| Recommended input voltage (VDD_HP_0, VDD_HP_1, VDD_HP_2, VDD_HP_3) |  | 0.99 | 1.1 | 1.3 | V |  | 89 |-| Recommended input voltage (VDD_MIPI_DPHY) |  | 2.25 | 2.5 | 2.75 | V |  | 89 |-| Recommended input voltage (VDD_USBPHY) |  | 2.97 | 3.3 | 3.63 | V |  | 89 |-| Current supplied to core | IVDD | 0.5 |  |  | A |  | 89 |-| Ambient temperature | TA | -40 |  | 85 | °C |  | 89 |-| Low-level input voltage | VIL | -0.3 |  |  | V | 3.3 V, 25 °C | 89 |-| High-level input current | IIH |  |  | 50 | nA | 3.3 V, 25 °C | 89 |-| Low-level input current | IIL |  |  | 50 | nA | 3.3 V, 25 °C | 89 |-| Chip reset voltage | VIL_nRST | -0.3 |  |  | V | CHIP_PU voltage is within the specified range | 90 |-| Differential nonlinearity (DNL) | DNL | -1 |  | 3 | LSB | external 100 nF capacitor on ADC, DC input, 25 °C | 90 |-| Integral nonlinearity (INL) | INL | -5 |  | 3 | LSB | external 100 nF capacitor on ADC, DC input, 25 °C | 90 |-| Sampling rate |  |  |  | 100 | kSPS | external 100 nF capacitor on ADC, DC input, 25 °C | 90 |-| Total error |  | -12 |  | 12 | mV | ATTEN0, effective measurement range of 0-1000 | 90 |-| Total error |  | -15 |  | 15 | mV | ATTEN3, effective measurement range of 0-3300 | 90 |-| Power supply voltage (1.8 V) | VCC | 1.62 | 1.8 | 1.98 | V | PSRAM 1.8 V variant | 92 |-| Power supply voltage (3.3 V) | VCC | 2.7 | 3.3 | 3.6 | V | PSRAM 3.3 V variant | 92 |-| Maximum clock frequency | FC | 80 |  |  | MHz | PSRAM | 92 |+| Recommended input voltage (VDD_LDO, VDD_DCDCC, VDD_ANA, VDD_LP) |  | 3 | 3.3 | 3.6 | V |  | 79 |+| Recommended input voltage (VDD_BAT) |  | 2.5 | 3.3 | 3.6 | V |  | 79 |+| Recommended input voltage (VDD_IO_0, VDD_FLASHIO, VDD_IO_4, VDD_IO_5, VDD_IO_6) |  | 1.65 | 3.3 | 3.6 | V |  | 79 |+| Recommended input voltage (VDD_PSRAM_0, VDD_PSRAM_1) |  | 1.65 | 1.8 | 1.95 | V |  | 79 |+| Recommended input voltage (VDD_HP_0, VDD_HP_2, VDD_HP_3) |  | 0.99 | 1.1 | 1.3 | V |  | 79 |+| Recommended input voltage (VDD_MIPI_DPHY) |  | 2.25 | 2.5 | 2.75 | V |  | 79 |+| Recommended input voltage (VDD_USBPHY) |  | 2.97 | 3.3 | 3.63 | V |  | 79 |+| Current supplied to core | IVDD | 0.5 |  |  | A |  | 79 |+| Ambient temperature | TA | -40 |  | 85 | °C |  | 79 |+| Allowed input voltage (VDD_LDO, VDD_DCDCC, VDD_ANA, VDD_BAT, VDD_LP) |  | -0.3 |  | 3.6 | V |  | 79 |+| Allowed input voltage (VDD_IO_0, VDD_FLASHIO, VDD_IO_4, VDD_IO_5, VDD_IO_6) |  | -0.3 |  | 3.6 | V |  | 79 |+| Allowed input voltage (VDD_PSRAM_0, VDD_PSRAM_1) |  | 1.62 |  | 1.98 | V |  | 79 |+| Allowed input voltage (VDD_HP_0, VDD_HP_2, VDD_HP_3) |  | 0 |  | 1.3 | V |  | 79 |+| Allowed input voltage (VDD_MIPI_DPHY) |  | 0 |  | 2.75 | V |  | 79 |+| Allowed input voltage (VDD_USBPHY) |  | -0.66 |  | 3.96 | V |  | 79 |+| Cumulative IO output current | Ioutput |  |  | 1500 | mA |  | 79 |+| Storage temperature | TSTORE | -40 |  | 150 | °C |  | 79 |+| High-level input current | IIH |  |  | 50 | nA |  | 80 |+| Low-level input current | IIL |  |  | 50 | nA |  | 80 |+| Differential nonlinearity | DNL | -1 |  | 3 | LSB |  | 81 |+| Integral nonlinearity | INL | -5 |  | 3 | LSB |  | 81 |+| Sampling rate |  |  |  | 100 | kSPS |  | 81 |+| Total error |  | -12 |  | 12 | mV | ATTEN0, effective measurement range of 0-1000 | 81 |+| Total error |  | -15 |  | 15 | mV | ATTEN3, effective measurement range of 0-3300 | 81 |+| Power supply voltage (1.8 V PSRAM) | VCC | 1.62 | 1.8 | 1.98 | V |  | 82 |+| Power supply voltage (3.3 V PSRAM) | VCC | 2.7 | 3.3 | 3.6 | V |  | 82 |+| Maximum clock frequency | FC | 80 |  |  | MHz |  | 82 |  ## CAD (KiCad official)  - Symbol: `ESP32-P4NRW32` - Footprint: `PCM_Espressif:ESP32-P4` - 3D model: QFN-104(10x10), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.85 mm nominal QFN height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)-- 3D model files: `esp32-p4nrw32-etched.step` / `esp32-p4nrw32-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `esp32-p4nrw32.step` / `esp32-p4nrw32.glb` are the bare package body.  ## Provenance  Data extracted from the manufacturer datasheet, not a distributor listing: -- **Datasheet:** [ESPRESSIF datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-p4_datasheet_en.pdf) (102 pp, sha256 `fb4f3e91cc2ac519`, retrieved 2026-10-27, tier: manufacturer)+- **Datasheet:** [ESPRESSIF datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-p4-chip-revision-v1.3_datasheet_en.pdf) (94 pp, sha256 `52ef629ec92510a6`, retrieved 2026-10-27, tier: manufacturer) - **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - **CAD:** KiCad official libraries (CC-BY-SA 4.0). 

@@ -1,6 +1,6 @@ {   "slug": "esp32-p4nrw32",-  "version": "0.1.0",+  "version": "0.1.1",   "type": "component",   "description": "ESPRESSIF Functional Modules, QFN-104(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",   "tags": [@@ -28,8 +28,7 @@     "viewers/symbol.html",     "viewers/footprint.html",     "esp32-p4nrw32-hero.glb",-    "esp32-p4nrw32-hero.overlay.json",-    "esp32-p4nrw32-etched.glb"+    "esp32-p4nrw32-hero.overlay.json"   ],   "component": {     "mpn": "ESP32-P4NRW32",@@ -38,21 +37,20 @@     "pin_count": 105,     "category": "Functional Modules",     "subcategory": "Functional Modules",-    "datasheet": "https://www.espressif.com/sites/default/files/documentation/esp32-p4_datasheet_en.pdf",+    "datasheet": "https://www.espressif.com/sites/default/files/documentation/esp32-p4-chip-revision-v1.3_datasheet_en.pdf",     "parts": {       "symbol": "esp32-p4nrw32.kicad_sym",       "footprint": "esp32-p4nrw32.kicad_mod",       "model_3d": "esp32-p4nrw32-hero.glb",-      "model_3d_plain": "esp32-p4nrw32-etched.glb",-      "model_3d_step": "esp32-p4nrw32-etched.step",-      "model_3d_step_plain": "esp32-p4nrw32.step",-      "lbr": "esp32-p4nrw32.lbr"+      "model_3d_step": "esp32-p4nrw32.step",+      "lbr": "esp32-p4nrw32.lbr",+      "model_3d_plain": "esp32-p4nrw32.glb"     },     "distributor_links": {       "lcsc": "C22387510"     },     "distributor_check": {-      "checked_at": "2026-10-27T22:16:13Z",+      "checked_at": "2026-10-27T22:22:52Z",       "source": "Component Ocean /api/assign-pns",       "digikey": {         "pn": null,@@ -68,625 +66,625 @@         "number": "1",         "name": "GPIO1",         "type": "bidirectional",-        "description": "IO pin powered by VDD_LP/VDD_BAT with IO MUX, LP IO MUX and XTAL_32K_P analog functions, default drive strength 20 mA."+        "description": "GPIO1 is powered by VDD_LP or VDD_BAT and also offers LP IO MUX and XTAL_32K_P analog functions."       },       {         "number": "2",         "name": "GPIO2",         "type": "bidirectional",-        "description": "IO pin powered by VDD_LP/VDD_BAT, input enabled with weak pull-up at reset, used as MTCK and TOUCH_CHANNEL1, default drive strength 20 mA."+        "description": "GPIO2 is powered by VDD_LP or VDD_BAT, has input enable and weak pull-up enabled at reset, and offers MTCK and touch channel 1."       },       {         "number": "3",         "name": "GPIO3",         "type": "bidirectional",-        "description": "IO pin powered by VDD_LP/VDD_BAT, input enabled at reset, used as MTDI (JTAG) and TOUCH_CHANNEL2, default drive strength 20 mA."+        "description": "GPIO3 is powered by VDD_LP or VDD_BAT, has input enable at reset, and offers MTDI and touch channel 2."       },       {         "number": "4",         "name": "GPIO4",         "type": "bidirectional",-        "description": "IO pin powered by VDD_LP, input enabled at reset, used as MTMS (JTAG) and TOUCH_CHANNEL3, default drive strength 20 mA."+        "description": "GPIO4 is powered by VDD_LP, has input enable at reset, and offers MTMS and touch channel 3."       },       {         "number": "5",         "name": "GPIO5",         "type": "bidirectional",-        "description": "IO pin powered by VDD_LP, used as MTDO (JTAG) and TOUCH_CHANNEL4, default drive strength 20 mA."+        "description": "GPIO5 is powered by VDD_LP and offers the MTDO JTAG output and touch channel 4."       },       {         "number": "6",         "name": "GPIO6",         "type": "bidirectional",-        "description": "IO pin powered by VDD_LP, with TOUCH_CHANNEL5 analog function and SPI2_HOLD_PAD on IO MUX F2, default drive strength 20 mA."+        "description": "GPIO6 is powered by VDD_LP and offers SPI2_HOLD and touch channel 5."       },       {         "number": "7",         "name": "GPIO7",         "type": "bidirectional",-        "description": "IO pin powered by VDD_LP, with TOUCH_CHANNEL6 analog function and SPI2_CS_PAD on IO MUX F2, default drive strength 20 mA."+        "description": "GPIO7 is powered by VDD_LP and offers SPI2_CS and touch channel 6."       },       {         "number": "8",         "name": "GPIO8",         "type": "bidirectional",-        "description": "IO pin powered by VDD_LP, with TOUCH_CHANNEL7, UART0_RTS_PAD and SPI2_D_PAD functions, default drive strength 20 mA."+        "description": "GPIO8 is powered by VDD_LP and offers SPI2_D and touch channel 7."       },       {         "number": "9",         "name": "VDD_LP",         "type": "power_in",-        "description": "LP power domain supply pin; recommended input voltage 3.0 to 3.6 V and allowed input voltage -0.3 to 3.6 V."+        "description": "LP power domain supply input, recommended 3.0 to 3.6 V (3.3 V typ) per Table 5-2."       },       {         "number": "10",         "name": "GPIO9",         "type": "bidirectional",-        "description": "IO pin powered by VDD_LP, with TOUCH_CHANNEL8, UART0_CTS_PAD and SPI2_CK_PAD functions, default drive strength 20 mA."+        "description": "GPIO9 is powered by VDD_LP and offers SPI2_CK and touch channel 8."       },       {         "number": "11",         "name": "GPIO10",         "type": "bidirectional",-        "description": "IO pin powered by VDD_LP, with TOUCH_CHANNEL9, UART1_TXD_PAD and SPI2_Q_PAD functions, default drive strength 20 mA."+        "description": "GPIO10 is powered by VDD_LP and offers SPI2_Q and touch channel 9."       },       {         "number": "12",         "name": "GPIO11",         "type": "bidirectional",-        "description": "IO pin powered by VDD_LP, with TOUCH_CHANNEL10, UART1_RXD_PAD and SPI2_WP_PAD functions, default drive strength 20 mA."+        "description": "GPIO11 is powered by VDD_LP and offers SPI2_WP and touch channel 10."       },       {         "number": "13",         "name": "GPIO12",         "type": "bidirectional",-        "description": "IO pin powered by VDD_LP, with TOUCH_CHANNEL11 and UART1_RTS_PAD functions, default drive strength 20 mA."+        "description": "GPIO12 is powered by VDD_LP and offers touch channel 11."       },       {         "number": "14",         "name": "GPIO13",         "type": "bidirectional",-        "description": "IO pin powered by VDD_LP, with TOUCH_CHANNEL12 and UART1_CTS_PAD functions, default drive strength 20 mA."+        "description": "GPIO13 is powered by VDD_LP and offers touch channel 12."       },       {         "number": "15",         "name": "GPIO14",         "type": "bidirectional",-        "description": "IO pin powered by VDD_LP, with TOUCH_CHANNEL13 and LP_UART_TXD_PAD functions, default drive strength 20 mA."+        "description": "GPIO14 is powered by VDD_LP and offers LP_UART_TXD and touch channel 13."       },       {         "number": "16",         "name": "GPIO15",         "type": "bidirectional",-        "description": "IO pin powered by VDD_LP, with TOUCH_CHANNEL14 and LP_UART_RXD_PAD functions, default drive strength 20 mA."+        "description": "GPIO15 is powered by VDD_LP and offers LP_UART_RXD and touch channel 14."       },       {         "number": "17",         "name": "GPIO16",         "type": "bidirectional",-        "description": "IO pin powered by VDD_IO_0, with ADC1_CHANNEL0 analog function, default drive strength 20 mA."+        "description": "GPIO16 is powered by VDD_IO_0 and offers ADC1_CHANNEL0 as an analog function."       },       {         "number": "18",         "name": "GPIO17",         "type": "bidirectional",-        "description": "IO pin powered by VDD_IO_0, with ADC1_CHANNEL1 analog function, default drive strength 20 mA."+        "description": "GPIO17 is powered by VDD_IO_0 and offers ADC1_CHANNEL1 as an analog function."       },       {         "number": "19",         "name": "GPIO18",         "type": "bidirectional",-        "description": "IO pin powered by VDD_IO_0, with ADC1_CHANNEL2 analog function, default drive strength 20 mA."+        "description": "GPIO18 is powered by VDD_IO_0 and offers ADC1_CHANNEL2 as an analog function."       },       {         "number": "20",         "name": "GPIO19",         "type": "bidirectional",-        "description": "IO pin powered by VDD_IO_0, with ADC1_CHANNEL3 analog function, default drive strength 20 mA."+        "description": "GPIO19 is powered by VDD_IO_0 and offers ADC1_CHANNEL3 as an analog function."       },       {         "number": "21",         "name": "VDD_IO_0",         "type": "power_in",-        "description": "Digital power domain supply for HP IO pins GPIO16 to GPIO23; recommended input voltage 1.65 to 3.6 V."+        "description": "Digital HP IO supply for GPIO16 to GPIO23, recommended 1.65 to 3.6 V (3.3 V typ) per Table 5-2."       },       {         "number": "22",         "name": "GPIO20",         "type": "bidirectional",-        "description": "IO pin powered by VDD_IO_0, with ADC1_CHANNEL4 analog function, default drive strength 20 mA."+        "description": "GPIO20 is powered by VDD_IO_0 and offers ADC1_CHANNEL4 as an analog function."       },       {         "number": "23",         "name": "GPIO21",         "type": "bidirectional",-        "description": "IO pin powered by VDD_IO_0, with ADC1_CHANNEL5 analog function, default drive strength 20 mA."+        "description": "GPIO21 is powered by VDD_IO_0 and offers ADC1_CHANNEL5 as an analog function."       },       {         "number": "24",         "name": "GPIO22",         "type": "bidirectional",-        "description": "IO pin powered by VDD_IO_0, with ADC1_CHANNEL6 analog function, default drive strength 20 mA."+        "description": "GPIO22 is powered by VDD_IO_0 and offers ADC1_CHANNEL6 as an analog function."       },       {         "number": "25",         "name": "GPIO23",         "type": "bidirectional",-        "description": "IO pin powered by VDD_IO_0, with ADC1_CHANNEL7 analog function and REF_50M_CLK_PAD output on IO MUX F2, default drive strength 20 mA."+        "description": "GPIO23 is powered by VDD_IO_0 and offers ADC1_CHANNEL7 and the REF_50M_CLK output."       },       {         "number": "26",         "name": "VDD_HP_0",         "type": "power_in",-        "description": "Digital power domain supply pin regulated by the external DC/DC via FB_DCDC; allowed input voltage 0 to 1.3 V."+        "description": "HP digital core supply, recommended 0.99 to 1.3 V (1.1 V typ) per Table 5-2."       },       {         "number": "27",         "name": "FLASH_CS",         "type": "output",-        "description": "Dedicated chip-select output to off-package flash, powered by VDD_FLASHIO."+        "description": "Dedicated chip-select output to the off-package flash, powered by VDD_FLASHIO."       },       {         "number": "28",         "name": "FLASH_Q",         "type": "bidirectional",-        "description": "Dedicated flash data-output (DO) pin to off-package flash, powered by VDD_FLASHIO."+        "description": "Dedicated flash data output line (DO) for off-package flash, powered by VDD_FLASHIO."       },       {         "number": "29",         "name": "FLASH_WP",         "type": "bidirectional",-        "description": "Dedicated flash write-protect (WP#) pin to off-package flash, powered by VDD_FLASHIO."+        "description": "Dedicated flash write-protect line (WP#) for off-package flash, powered by VDD_FLASHIO."       },       {         "number": "30",         "name": "VDD_FLASHIO",         "type": "power_in",-        "description": "Power supply for flash IO pins; the voltage should be adjusted to the flash model, with 3.3 V flash used as the example in the datasheet."+        "description": "Power supply for flash IO, which should be adjusted to the flash model (3.3 V flash used as the example)."       },       {         "number": "31",         "name": "FLASH_HOLD",         "type": "bidirectional",-        "description": "Dedicated flash HOLD# pin to off-package flash, powered by VDD_FLASHIO."+        "description": "Dedicated flash HOLD# line for off-package flash, powered by VDD_FLASHIO."       },       {         "number": "32",         "name": "FLASH_CK",         "type": "output",-        "description": "Dedicated flash clock output to off-package flash, powered by VDD_FLASHIO."+        "description": "Dedicated flash clock output for off-package flash, powered by VDD_FLASHIO."       },       {         "number": "33",         "name": "FLASH_D",         "type": "bidirectional",-        "description": "Dedicated flash data-input (DI) pin to off-package flash, powered by VDD_FLASHIO."+        "description": "Dedicated flash data input line (DI) for off-package flash, powered by VDD_FLASHIO."       },       {         "number": "34",         "name": "DSI_REXT",         "type": "bidirectional",-        "description": "MIPI DSI PHY external 4.02 kΩ reference resistor pin, powered by VDD_MIPI_DPHY."+        "description": "Connects the external 4.02 kΩ reference resistor for the MIPI DSI PHY."       },       {         "number": "35",         "name": "DSI_DATAP1",         "type": "bidirectional",-        "description": "MIPI DSI PHY data positive channel 1 pin, powered by VDD_MIPI_DPHY."+        "description": "MIPI DSI PHY positive data channel 1, powered by VDD_MIPI_DPHY."       },       {         "number": "36",         "name": "DSI_DATAN1",         "type": "bidirectional",-        "description": "MIPI DSI PHY data negative channel 1 pin, powered by VDD_MIPI_DPHY."+        "description": "MIPI DSI PHY negative data channel 1, powered by VDD_MIPI_DPHY."       },       {         "number": "37",         "name": "DSI_CLKN",         "type": "bidirectional",-        "description": "MIPI DSI PHY clock negative pin, powered by VDD_MIPI_DPHY."+        "description": "MIPI DSI PHY negative clock channel, powered by VDD_MIPI_DPHY."       },       {         "number": "38",         "name": "DSI_CLKP",         "type": "bidirectional",-        "description": "MIPI DSI PHY clock positive pin, powered by VDD_MIPI_DPHY."+        "description": "MIPI DSI PHY positive clock channel, powered by VDD_MIPI_DPHY."       },       {         "number": "39",         "name": "DSI_DATAP0",         "type": "bidirectional",-        "description": "MIPI DSI PHY data positive channel 0 pin, powered by VDD_MIPI_DPHY."+        "description": "MIPI DSI PHY positive data channel 0, powered by VDD_MIPI_DPHY."       },       {         "number": "40",         "name": "DSI_DATAN0",         "type": "bidirectional",-        "description": "MIPI DSI PHY data negative channel 0 pin, powered by VDD_MIPI_DPHY."+        "description": "MIPI DSI PHY negative data channel 0, powered by VDD_MIPI_DPHY."       },       {         "number": "41",         "name": "VDD_MIPI_DPHY",         "type": "power_in",-        "description": "Supply for the MIPI PHY pins; allowed input voltage 0 to 2.75 V."+        "description": "MIPI PHY supply, recommended 2.25 to 2.75 V (2.5 V typ) per Table 5-2."       },       {         "number": "42",         "name": "CSI_DATAN0",         "type": "bidirectional",-        "description": "MIPI CSI PHY data negative channel 0 pin, powered by VDD_MIPI_DPHY."+        "description": "MIPI CSI PHY negative data channel 0, powered by VDD_MIPI_DPHY."       },       {         "number": "43",         "name": "CSI_DATAP0",         "type": "bidirectional",-        "description": "MIPI CSI PHY data positive channel 0 pin, powered by VDD_MIPI_DPHY."+        "description": "MIPI CSI PHY positive data channel 0, powered by VDD_MIPI_DPHY."       },       {         "number": "44",         "name": "CSI_CLKP",         "type": "bidirectional",-        "description": "MIPI CSI PHY clock positive pin, powered by VDD_MIPI_DPHY."+        "description": "MIPI CSI PHY positive clock channel, powered by VDD_MIPI_DPHY."       },       {         "number": "45",         "name": "CSI_CLKN",         "type": "bidirectional",-        "description": "MIPI CSI PHY clock negative pin, powered by VDD_MIPI_DPHY."+        "description": "MIPI CSI PHY negative clock channel, powered by VDD_MIPI_DPHY."       },       {         "number": "46",         "name": "CSI_DATAN1",         "type": "bidirectional",-        "description": "MIPI CSI PHY data negative channel 1 pin, powered by VDD_MIPI_DPHY."+        "description": "MIPI CSI PHY negative data channel 1, powered by VDD_MIPI_DPHY."       },       {         "number": "47",         "name": "CSI_DATAP1",         "type": "bidirectional",-        "description": "MIPI CSI PHY data positive channel 1 pin, powered by VDD_MIPI_DPHY."+        "description": "MIPI CSI PHY positive data channel 1, powered by VDD_MIPI_DPHY."       },       {         "number": "48",         "name": "CSI_REXT",         "type": "bidirectional",-        "description": "MIPI CSI PHY external 4.02 kΩ reference resistor pin, powered by VDD_MIPI_DPHY."+        "description": "Connects the external 4.02 kΩ reference resistor for the MIPI CSI PHY."       },       {         "number": "49",         "name": "USB_DM",         "type": "bidirectional",-        "description": "USB 2.0 High-Speed OTG PHY D- pin, powered by VDD_USBPHY."+        "description": "USB 2.0 OTG high-speed PHY D- signal, powered by VDD_USBPHY (2.97 to 3.63 V)."       },       {         "number": "50",         "name": "USB_DP",         "type": "bidirectional",-        "description": "USB 2.0 High-Speed OTG PHY D+ pin, powered by VDD_USBPHY."+        "description": "USB 2.0 OTG high-speed PHY D+ signal, powered by VDD_USBPHY (2.97 to 3.63 V)."       },       {         "number": "51",         "name": "VDD_USBPHY",         "type": "power_in",-        "description": "Supply for the USB PHY pins; allowed input voltage -0.66 to 3.96 V."+        "description": "USB PHY supply, recommended 2.97 to 3.63 V (3.3 V typ) per Table 5-2."       },       {         "number": "52",         "name": "GPIO24",         "type": "bidirectional",-        "description": "IO pin powered by VDD_IO_4 with USB1P1_N0 analog function, default drive strength 40 mA."+        "description": "GPIO24 is powered by VDD_IO_4 with a default drive strength of 40 mA and offers USB1P1_N0."       },       {         "number": "53",         "name": "GPIO25",         "type": "bidirectional",-        "description": "IO pin powered by VDD_IO_4 with USB1P1_P0 analog function, default drive strength 40 mA."+        "description": "GPIO25 is powered by VDD_IO_4 with a default drive strength of 40 mA, USB pull-up enabled at reset, and offers USB1P1_P0."       },       {         "number": "54",-        "name": "VDD_HP_1",-        "type": "power_in",-        "description": "Digital power domain supply pin regulated by the external DC/DC via FB_DCDC; allowed input voltage 0 to 1.3 V."+        "name": "NC",+        "type": "unconnected",+        "description": "Pin is not connected (NC) in the package."       },       {         "number": "55",         "name": "GPIO26",         "type": "bidirectional",-        "description": "IO pin powered by VDD_IO_4 with USB1P1_N1 analog function, default drive strength 20 mA."+        "description": "GPIO26 is powered by VDD_IO_4 with a default drive strength of 20 mA and offers USB1P1_N1."       },       {         "number": "56",         "name": "GPIO27",         "type": "bidirectional",-        "description": "IO pin powered by VDD_IO_4 with USB1P1_P1 analog function, default drive strength 20 mA."+        "description": "GPIO27 is powered by VDD_IO_4 with a default drive strength of 20 mA and offers USB1P1_P1."       },       {         "number": "57",         "name": "GPIO28",         "type": "bidirectional",-        "description": "IO pin powered by VDD_IO_4 with SPI2_CS_PAD and GMAC_PHY_RXDV_PAD functions, default drive strength 20 mA."+        "description": "GPIO28 is powered by VDD_IO_4 and offers SPI2_CS and the GMAC_PHY_RXDV input."       },       {         "number": "58",         "name": "GPIO29",         "type": "bidirectional",-        "description": "IO pin powered by VDD_IO_4 with SPI2_D_PAD and GMAC_PHY_RXD0_PAD functions, default drive strength 20 mA."+        "description": "GPIO29 is powered by VDD_IO_4 and offers SPI2_D and the GMAC_PHY_RXD0 input."       },       {         "number": "59",         "name": "VDD_PSRAM_0",         "type": "power_in",-        "description": "PSRAM power supply pin; recommended input voltage 1.65 to 1.95 V for the 1.8 V PSRAM."+        "description": "In-package PSRAM supply, recommended 1.65 to 1.95 V (1.8 V typ) per Table 5-2."       },       {         "number": "60",         "name": "GPIO30",         "type": "bidirectional",-        "description": "IO pin powered by VDD_IO_4 with SPI2_CK_PAD and GMAC_PHY_RXD1_PAD functions, default drive strength 20 mA."+        "description": "GPIO30 is powered by VDD_IO_4 and offers SPI2_CK and the GMAC_PHY_RXD1 input."       },       {         "number": "61",         "name": "GPIO31",         "type": "bidirectional",-        "description": "IO pin powered by VDD_IO_4 with SPI2_Q_PAD and GMAC_PHY_RXER_PAD functions, default drive strength 20 mA."+        "description": "GPIO31 is powered by VDD_IO_4 and offers SPI2_Q and the GMAC_PHY_RXER input."       },       {         "number": "62",         "name": "VDD_IO_4",         "type": "power_in",-        "description": "Digital power domain supply for HP IO pins GPIO24 to GPIO38; recommended input voltage 1.65 to 3.6 V."+        "description": "Digital HP IO supply for GPIO24 to GPIO38, recommended 1.65 to 3.6 V (3.3 V typ) per Table 5-2."       },       {         "number": "63",         "name": "GPIO32",         "type": "bidirectional",-        "description": "IO pin powered by VDD_IO_4, input enabled at reset, with SPI2_HOLD_PAD, I3C_MST_SCL_PAD (configurable pull-up) and GMAC_RMII_CLK_PAD functions."+        "description": "GPIO32 is powered by VDD_IO_4, has input enable at reset, and offers SPI2_HOLD and the GMAC_RMII_CLK input."       },       {         "number": "64",         "name": "GPIO33",         "type": "bidirectional",-        "description": "IO pin powered by VDD_IO_4, input enabled at reset, with SPI2_WP_PAD, I3C_MST_SDA_PAD (configurable pull-up) and GMAC_PHY_TXEN_PAD functions."+        "description": "GPIO33 is powered by VDD_IO_4, has input enable at reset, and offers SPI2_WP and the GMAC_PHY_TXEN output."       },       {         "number": "65",         "name": "GPIO34",         "type": "bidirectional",-        "description": "IO pin powered by VDD_IO_4, input enabled at reset, a strapping pin for JTAG signal source control, with SPI2_IO4_PAD and GMAC_PHY_TXD0_PAD functions."+        "description": "GPIO34 is powered by VDD_IO_4 with input enable at reset, and is the strapping pin for the JTAG signal source control."       },       {         "number": "66",         "name": "GPIO35",         "type": "bidirectional",-        "description": "IO pin powered by VDD_IO_4, input enabled with weak pull-up at reset, a strapping pin for chip boot mode, with SPI2_IO5_PAD and GMAC_PHY_TXD1_PAD functions."+        "description": "GPIO35 is powered by VDD_IO_4 with input enable and weak pull-up at reset, and is the default-high strapping pin for boot mode control."       },       {         "number": "67",         "name": "VDD_PSRAM_1",         "type": "power_in",-        "description": "PSRAM power supply pin; recommended input voltage 1.65 to 1.95 V for the 1.8 V PSRAM."+        "description": "In-package PSRAM supply, recommended 1.65 to 1.95 V (1.8 V typ) per Table 5-2."       },       {         "number": "68",         "name": "GPIO36",         "type": "bidirectional",-        "description": "IO pin powered by VDD_IO_4, input enabled at reset, a strapping pin for ROM message printing control, with SPI2_IO6_PAD and GMAC_PHY_TXER_PAD functions."+        "description": "GPIO36 is powered by VDD_IO_4 with input enable at reset, and is the strapping pin for ROM message printing control."       },       {         "number": "69",         "name": "GPIO37",         "type": "bidirectional",-        "description": "IO pin powered by VDD_IO_4, a strapping pin for chip boot mode, with UART0_TXD_PAD and SPI2_IO7_PAD functions."+        "description": "GPIO37 is powered by VDD_IO_4 with input enable at reset, a boot mode strapping pin, and offers the UART0_TXD output."       },       {         "number": "70",         "name": "GPIO38",         "type": "bidirectional",-        "description": "IO pin powered by VDD_IO_4, input enabled at reset, a strapping pin for chip boot mode, with UART0_RXD_PAD and SPI2_DQS_PAD functions."+        "description": "GPIO38 is powered by VDD_IO_4 with input enable at reset, a boot mode strapping pin, and offers the UART0_RXD input."       },       {         "number": "71",         "name": "VDDO_FLASH",         "type": "power_out",-        "description": "Output supply for off-package flash, delivering up to 50 mA at maximum."+        "description": "Flash power output, 3.3 V by default or 1.8 V after EFUSE_0PXA_TIEH_SEL_0 is burnt, supplying up to 50 mA."       },       {         "number": "72",         "name": "VDDO_PSRAM",         "type": "power_out",-        "description": "Output supply for in-package and off-package PSRAM, delivering up to 50 mA at maximum."+        "description": "Output rail for in-package and off-package PSRAM, supplying up to 50 mA."       },       {         "number": "73",         "name": "VDDO_3",         "type": "power_out",-        "description": "Output supply from a voltage regulator, delivering up to 50 mA at maximum."+        "description": "VO3 LDO output rail for external devices, configurable 0.5 to 2.7 V or 3.3 V, supplying up to 50 mA."       },       {         "number": "74",         "name": "VDDO_4",         "type": "power_out",-        "description": "Output supply from a voltage regulator, delivering up to 50 mA at maximum."+        "description": "VO4 LDO output rail for external devices, configurable 0.5 to 2.7 V or 3.3 V, supplying up to 50 mA."       },       {         "number": "75",         "name": "VDD_LDO",         "type": "power_in",-        "description": "Analog power domain supply providing power for LDOs; recommended input voltage 3.0 to 3.6 V."+        "description": "Analog power domain input that provides power for the LDOs, recommended 3.0 to 3.6 V."       },       {         "number": "76",         "name": "VDD_HP_2",         "type": "power_in",-        "description": "Digital power domain supply pin regulated by the external DC/DC via FB_DCDC; allowed input voltage 0 to 1.3 V."+        "description": "HP digital core supply, recommended 0.99 to 1.3 V (1.1 V typ) per Table 5-2."       },       {         "number": "77",         "name": "VDD_DCDCC",         "type": "power_in",-        "description": "Analog power domain supply for DC/DC control; recommended input voltage 3.0 to 3.6 V."+        "description": "Analog power domain input for DC/DC control, recommended 3.0 to 3.6 V."       },       {         "number": "78",         "name": "FB_DCDC",         "type": "passive",-        "description": "Feedback pin of the external DC/DC supply, which regulates VDD_HP_0/1/2/3 together with feedback resistors."+        "description": "Feedback pin of the external DC/DC supply, which regulates VDD_HP_0/2/3 together with feedback resistors."       },       {         "number": "79",         "name": "EN_DCDC",         "type": "output",-        "description": "Enable output pin for the external DC/DC converter."+        "description": "Enable output for the external DC/DC converter."       },       {         "number": "80",         "name": "GPIO39",         "type": "bidirectional",-        "description": "IO pin powered by VDD_IO_5 with SD1_CDATA0_PAD and REF_50M_CLK_PAD output functions."+        "description": "GPIO39 is powered by VDD_IO_5 and offers SD1_CDATA0 and the REF_50M_CLK output."       },       {         "number": "81",         "name": "GPIO40",         "type": "bidirectional",-        "description": "IO pin powered by VDD_IO_5 with SD1_CDATA1_PAD and GMAC_PHY_TXEN_PAD output functions."+        "description": "GPIO40 is powered by VDD_IO_5 and offers SD1_CDATA1 and the GMAC_PHY_TXEN output."       },       {         "number": "82",         "name": "GPIO41",         "type": "bidirectional",-        "description": "IO pin powered by VDD_IO_5 with SD1_CDATA2_PAD and GMAC_PHY_TXD0_PAD output functions."+        "description": "GPIO41 is powered by VDD_IO_5 and offers SD1_CDATA2 and the GMAC_PHY_TXD0 output."       },       {         "number": "83",         "name": "GPIO42",         "type": "bidirectional",-        "description": "IO pin powered by VDD_IO_5 with SD1_CDATA3_PAD and GMAC_PHY_TXD1_PAD output functions."+        "description": "GPIO42 is powered by VDD_IO_5 and offers SD1_CDATA3 and the GMAC_PHY_TXD1 output."       },       {         "number": "84",         "name": "GPIO43",         "type": "bidirectional",-        "description": "IO pin powered by VDD_IO_5 with SD1_CCLK_PAD and GMAC_PHY_TXER_PAD output functions."+        "description": "GPIO43 is powered by VDD_IO_5 and offers the SD1_CCLK output and the GMAC_PHY_TXER output."       },       {         "number": "85",         "name": "VDD_IO_5",         "type": "power_in",-        "description": "Digital power domain supply for HP IO pins GPIO39 to GPIO48; recommended input voltage 1.65 to 3.6 V."+        "description": "Digital HP IO supply for GPIO39 to GPIO48, recommended 1.65 to 3.6 V (3.3 V typ) per Table 5-2."       },       {         "number": "86",         "name": "GPIO44",         "type": "bidirectional",-        "description": "IO pin powered by VDD_IO_5 with SD1_CCMD_PAD and GMAC_RMII_CLK_PAD functions."+        "description": "GPIO44 is powered by VDD_IO_5 and offers SD1_CCMD and the GMAC_RMII_CLK input."       },       {         "number": "87",         "name": "GPIO45",         "type": "bidirectional",-        "description": "IO pin powered by VDD_IO_5 with SD1_CDATA4_PAD and GMAC_PHY_RXDV_PAD functions."+        "description": "GPIO45 is powered by VDD_IO_5 and offers SD1_CDATA4 and the GMAC_PHY_RXDV input."       },       {         "number": "88",         "name": "GPIO46",         "type": "bidirectional",-        "description": "IO pin powered by VDD_IO_5 with SD1_CDATA5_PAD and GMAC_PHY_RXD0_PAD functions."+        "description": "GPIO46 is powered by VDD_IO_5 and offers SD1_CDATA5 and the GMAC_PHY_RXD0 input."       },       {         "number": "89",         "name": "GPIO47",         "type": "bidirectional",-        "description": "IO pin powered by VDD_IO_5 with SD1_CDATA6_PAD and GMAC_PHY_RXD1_PAD functions."+        "description": "GPIO47 is powered by VDD_IO_5 and offers SD1_CDATA6 and the GMAC_PHY_RXD1 input."       },       {         "number": "90",         "name": "GPIO48",         "type": "bidirectional",-        "description": "IO pin powered by VDD_IO_5 with SD1_CDATA7_PAD and GMAC_PHY_RXER_PAD functions."+        "description": "GPIO48 is powered by VDD_IO_5 and offers SD1_CDATA7 and the GMAC_PHY_RXER input."       },       {         "number": "91",         "name": "VDD_HP_3",         "type": "power_in",-        "description": "Digital power domain supply pin regulated by the external DC/DC via FB_DCDC; allowed input voltage 0 to 1.3 V."+        "description": "HP digital core supply, recommended 0.99 to 1.3 V (1.1 V typ) per Table 5-2."       },       {         "number": "92",         "name": "GPIO49",         "type": "bidirectional",-        "description": "IO pin powered by VDD_IO_6 with ADC2_CHANNEL0 analog function and GMAC_PHY_TXEN_PAD output on IO MUX F2."+        "description": "GPIO49 is powered by VDD_IO_6, offers ADC2_CHANNEL0, and offers the GMAC_PHY_TXEN output."       },       {         "number": "93",         "name": "GPIO50",         "type": "bidirectional",-        "description": "IO pin powered by VDD_IO_6 with ADC2_CHANNEL1 analog function and GMAC_RMII_CLK_PAD on IO MUX F2."+        "description": "GPIO50 is powered by VDD_IO_6, offers ADC2_CHANNEL1, and offers the GMAC_RMII_CLK input."       },       {         "number": "94",         "name": "GPIO51",         "type": "bidirectional",-        "description": "IO pin powered by VDD_IO_6 with ADC2_CHANNEL2, ANA_COMP0 analog function and GMAC_PHY_RXDV_PAD on IO MUX F2."+        "description": "GPIO51 is powered by VDD_IO_6, offers ADC2_CHANNEL2, and offers ANA_COMP0."       },       {         "number": "95",         "name": "GPIO52",         "type": "bidirectional",-        "description": "IO pin powered by VDD_IO_6 with ADC2_CHANNEL3, ANA_COMP0 analog function and GMAC_PHY_RXD0_PAD on IO MUX F2."+        "description": "GPIO52 is powered by VDD_IO_6, offers ADC2_CHANNEL3, and offers ANA_COMP0."       },       {         "number": "96",         "name": "VDD_IO_6",         "type": "power_in",-        "description": "Digital power domain supply for HP IO pins GPIO49 to GPIO54; recommended input voltage 1.65 to 3.6 V."+        "description": "Digital HP IO supply for GPIO49 to GPIO54, recommended 1.65 to 3.6 V (3.3 V typ) per Table 5-2."       },       {         "number": "97",         "name": "GPIO53",         "type": "bidirectional",-        "description": "IO pin powered by VDD_IO_6 with ADC2_CHANNEL4, ANA_COMP1 analog function and GMAC_PHY_RXD1_PAD on IO MUX F2."+        "description": "GPIO53 is powered by VDD_IO_6, offers ADC2_CHANNEL4, and offers ANA_COMP1."       },       {         "number": "98",         "name": "GPIO54",         "type": "bidirectional",-        "description": "IO pin powered by VDD_IO_6 with ADC2_CHANNEL5, ANA_COMP1 analog function and GMAC_PHY_RXER_PAD on IO MUX F2."+        "description": "GPIO54 is powered by VDD_IO_6, offers ADC2_CHANNEL5, and offers ANA_COMP1."       },       {         "number": "99",         "name": "XTAL_N",         "type": "passive",-        "description": "External clock input/output connected to the chip's crystal or oscillator, negative side of the differential clock."+        "description": "Negative side of the external clock input/output connected to the chip crystal or oscillator (40 MHz XTAL_CLK)."       },       {         "number": "100",         "name": "XTAL_P",         "type": "passive",-        "description": "External clock input/output connected to the chip's crystal or oscillator, positive side of the differential clock."+        "description": "Positive side of the external clock input/output connected to the chip crystal or oscillator (40 MHz XTAL_CLK)."       },       {         "number": "101",         "name": "VDD_ANA",         "type": "power_in",-        "description": "Analog power domain supply; recommended input voltage 3.0 to 3.6 V."+        "description": "Analog power domain supply, recommended 3.0 to 3.6 V."       },       {         "number": "102",         "name": "VDD_BAT",         "type": "power_in",-        "description": "Analog power domain supply, optionally connected to an external battery; recommended input voltage 2.5 to 3.6 V."+        "description": "Analog power domain input that can optionally connect to an external battery, recommended 2.5 to 3.6 V."       },       {         "number": "103",         "name": "CHIP_PU",         "type": "input",-        "description": "Chip enable: high enables the chip and low powers it down; the pin must not be left floating."+        "description": "Chip enable: high powers up and enables the chip, low powers it down, and it must not be left floating."       },       {         "number": "104",         "name": "GPIO0",         "type": "bidirectional",-        "description": "IO pin powered by VDD_LP/VDD_BAT with XTAL_32K_N analog function and LP_GPIO0, default drive strength 20 mA."+        "description": "GPIO0 is powered by VDD_LP or VDD_BAT and also offers LP_GPIO0 and XTAL_32K_N analog function."       },       {         "number": "105",@@ -706,16 +704,16 @@         "consensus": "agreed",         "guards": "pin_guards 0.1: passed",         "guard_notes": [-          "extractor flagged: The requested MPN ESP32-P4NRW32 matches the datasheet part ESP32-P4NRW32X (32 MB in-package PSRAM). ; The datasheet is a preliminary pre-release v0.7 and states its electrical values may change; Table 2"+          "extractor flagged: The MPN ESP32-P4NRW32 is marked End of Life in this datasheet (upgraded to ESP32-P4NRW32X). The pino; Table 2-11 lists VDD_FLASHIO2 with a footnote, while Table 2-1 and Figure 2-1 name the pin VDD_FLASH; Pin 54 is printed as NC and pin 105 is GND, which is the package ground pad. Pin 105 is typed power_"         ],-        "pages_sent": 65,-        "cost_usd": 0.2616,-        "at": "2026-10-27T22:15:29"+        "pages_sent": 94,+        "cost_usd": 0.2826,+        "at": "2026-10-27T22:22:15"       },       "datasheet": {-        "url": "https://www.espressif.com/sites/default/files/documentation/esp32-p4_datasheet_en.pdf",-        "pages": 102,-        "sha256": "fb4f3e91cc2ac519",+        "url": "https://www.espressif.com/sites/default/files/documentation/esp32-p4-chip-revision-v1.3_datasheet_en.pdf",+        "pages": 94,+        "sha256": "52ef629ec92510a6",         "source_tier": "mfr"       },       "cad": "KiCad official (CC-BY-SA 4.0)",@@ -746,26 +744,7 @@         "zmin_mm": 0.0,         "centre_offset_mm": 0.0,         "footprint_binding": "none",-        "sha256": "29d170305521a2d9435f9c70f5887fca9d93d9ab3cb1fbf2c26ae9f913506674",-        "checked": "2026-10-27",-        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"-      },-      {-        "file": "esp32-p4nrw32-etched.step",-        "role": "eda",-        "up": "Z",-        "units": "mm",-        "origin": "footprint origin = pad-pattern centre",-        "seat": "z = 0",-        "extents_mm": [-          10.02,-          10.02,-          0.85-        ],-        "zmin_mm": 0.0,-        "centre_offset_mm": 0.0,-        "footprint_binding": "none",-        "sha256": "c470ee02e3362bd96141e6f6a4f508ad11a9c045336f6bf77e47debd005a3ed3",+        "sha256": "4768606132501b6e08a104c25fd4482e49df118ce235014d13dd1b2ecba470ee",         "checked": "2026-10-27",         "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"       }

@@ -4,7 +4,7 @@   "slug": "esp32-p4nrw32",   "title": "ESP32-P4NRW32",   "brief": "ESPRESSIF Functional Modules, QFN-104(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",-  "version": "0.1.0",+  "version": "0.1.1",   "license": "CC-BY-SA-4.0",   "tags": [     "component",@@ -20,21 +20,20 @@     "pin_count": 105,     "category": "Functional Modules",     "subcategory": "Functional Modules",-    "datasheet": "https://www.espressif.com/sites/default/files/documentation/esp32-p4_datasheet_en.pdf",+    "datasheet": "https://www.espressif.com/sites/default/files/documentation/esp32-p4-chip-revision-v1.3_datasheet_en.pdf",     "parts": {       "symbol": "esp32-p4nrw32.kicad_sym",       "footprint": "esp32-p4nrw32.kicad_mod",       "model_3d": "esp32-p4nrw32-hero.glb",-      "model_3d_plain": "esp32-p4nrw32-etched.glb",-      "model_3d_step": "esp32-p4nrw32-etched.step",-      "model_3d_step_plain": "esp32-p4nrw32.step",-      "lbr": "esp32-p4nrw32.lbr"+      "model_3d_step": "esp32-p4nrw32.step",+      "lbr": "esp32-p4nrw32.lbr",+      "model_3d_plain": "esp32-p4nrw32.glb"     },     "distributor_links": {       "lcsc": "C22387510"     },     "distributor_check": {-      "checked_at": "2026-10-27T22:16:13Z",+      "checked_at": "2026-10-27T22:22:52Z",       "source": "Component Ocean /api/assign-pns",       "digikey": {         "pn": null,@@ -50,625 +49,625 @@         "number": "1",         "name": "GPIO1",         "type": "bidirectional",-        "description": "IO pin powered by VDD_LP/VDD_BAT with IO MUX, LP IO MUX and XTAL_32K_P analog functions, default drive strength 20 mA."+        "description": "GPIO1 is powered by VDD_LP or VDD_BAT and also offers LP IO MUX and XTAL_32K_P analog functions."       },       {         "number": "2",         "name": "GPIO2",         "type": "bidirectional",-        "description": "IO pin powered by VDD_LP/VDD_BAT, input enabled with weak pull-up at reset, used as MTCK and TOUCH_CHANNEL1, default drive strength 20 mA."+        "description": "GPIO2 is powered by VDD_LP or VDD_BAT, has input enable and weak pull-up enabled at reset, and offers MTCK and touch channel 1."       },       {         "number": "3",         "name": "GPIO3",         "type": "bidirectional",-        "description": "IO pin powered by VDD_LP/VDD_BAT, input enabled at reset, used as MTDI (JTAG) and TOUCH_CHANNEL2, default drive strength 20 mA."+        "description": "GPIO3 is powered by VDD_LP or VDD_BAT, has input enable at reset, and offers MTDI and touch channel 2."       },       {         "number": "4",         "name": "GPIO4",         "type": "bidirectional",-        "description": "IO pin powered by VDD_LP, input enabled at reset, used as MTMS (JTAG) and TOUCH_CHANNEL3, default drive strength 20 mA."+        "description": "GPIO4 is powered by VDD_LP, has input enable at reset, and offers MTMS and touch channel 3."       },       {         "number": "5",         "name": "GPIO5",         "type": "bidirectional",-        "description": "IO pin powered by VDD_LP, used as MTDO (JTAG) and TOUCH_CHANNEL4, default drive strength 20 mA."+        "description": "GPIO5 is powered by VDD_LP and offers the MTDO JTAG output and touch channel 4."       },       {         "number": "6",         "name": "GPIO6",         "type": "bidirectional",-        "description": "IO pin powered by VDD_LP, with TOUCH_CHANNEL5 analog function and SPI2_HOLD_PAD on IO MUX F2, default drive strength 20 mA."+        "description": "GPIO6 is powered by VDD_LP and offers SPI2_HOLD and touch channel 5."       },       {         "number": "7",         "name": "GPIO7",         "type": "bidirectional",-        "description": "IO pin powered by VDD_LP, with TOUCH_CHANNEL6 analog function and SPI2_CS_PAD on IO MUX F2, default drive strength 20 mA."+        "description": "GPIO7 is powered by VDD_LP and offers SPI2_CS and touch channel 6."       },       {         "number": "8",         "name": "GPIO8",         "type": "bidirectional",-        "description": "IO pin powered by VDD_LP, with TOUCH_CHANNEL7, UART0_RTS_PAD and SPI2_D_PAD functions, default drive strength 20 mA."+        "description": "GPIO8 is powered by VDD_LP and offers SPI2_D and touch channel 7."       },       {         "number": "9",         "name": "VDD_LP",         "type": "power_in",-        "description": "LP power domain supply pin; recommended input voltage 3.0 to 3.6 V and allowed input voltage -0.3 to 3.6 V."+        "description": "LP power domain supply input, recommended 3.0 to 3.6 V (3.3 V typ) per Table 5-2."       },       {         "number": "10",         "name": "GPIO9",         "type": "bidirectional",-        "description": "IO pin powered by VDD_LP, with TOUCH_CHANNEL8, UART0_CTS_PAD and SPI2_CK_PAD functions, default drive strength 20 mA."+        "description": "GPIO9 is powered by VDD_LP and offers SPI2_CK and touch channel 8."       },       {         "number": "11",         "name": "GPIO10",         "type": "bidirectional",-        "description": "IO pin powered by VDD_LP, with TOUCH_CHANNEL9, UART1_TXD_PAD and SPI2_Q_PAD functions, default drive strength 20 mA."+        "description": "GPIO10 is powered by VDD_LP and offers SPI2_Q and touch channel 9."       },       {         "number": "12",         "name": "GPIO11",         "type": "bidirectional",-        "description": "IO pin powered by VDD_LP, with TOUCH_CHANNEL10, UART1_RXD_PAD and SPI2_WP_PAD functions, default drive strength 20 mA."+        "description": "GPIO11 is powered by VDD_LP and offers SPI2_WP and touch channel 10."       },       {         "number": "13",         "name": "GPIO12",         "type": "bidirectional",-        "description": "IO pin powered by VDD_LP, with TOUCH_CHANNEL11 and UART1_RTS_PAD functions, default drive strength 20 mA."+        "description": "GPIO12 is powered by VDD_LP and offers touch channel 11."       },       {         "number": "14",         "name": "GPIO13",         "type": "bidirectional",-        "description": "IO pin powered by VDD_LP, with TOUCH_CHANNEL12 and UART1_CTS_PAD functions, default drive strength 20 mA."+        "description": "GPIO13 is powered by VDD_LP and offers touch channel 12."       },       {         "number": "15",         "name": "GPIO14",         "type": "bidirectional",-        "description": "IO pin powered by VDD_LP, with TOUCH_CHANNEL13 and LP_UART_TXD_PAD functions, default drive strength 20 mA."+        "description": "GPIO14 is powered by VDD_LP and offers LP_UART_TXD and touch channel 13."       },       {         "number": "16",         "name": "GPIO15",         "type": "bidirectional",-        "description": "IO pin powered by VDD_LP, with TOUCH_CHANNEL14 and LP_UART_RXD_PAD functions, default drive strength 20 mA."+        "description": "GPIO15 is powered by VDD_LP and offers LP_UART_RXD and touch channel 14."       },       {         "number": "17",         "name": "GPIO16",         "type": "bidirectional",-        "description": "IO pin powered by VDD_IO_0, with ADC1_CHANNEL0 analog function, default drive strength 20 mA."+        "description": "GPIO16 is powered by VDD_IO_0 and offers ADC1_CHANNEL0 as an analog function."       },       {         "number": "18",         "name": "GPIO17",         "type": "bidirectional",-        "description": "IO pin powered by VDD_IO_0, with ADC1_CHANNEL1 analog function, default drive strength 20 mA."+        "description": "GPIO17 is powered by VDD_IO_0 and offers ADC1_CHANNEL1 as an analog function."       },       {         "number": "19",         "name": "GPIO18",         "type": "bidirectional",-        "description": "IO pin powered by VDD_IO_0, with ADC1_CHANNEL2 analog function, default drive strength 20 mA."+        "description": "GPIO18 is powered by VDD_IO_0 and offers ADC1_CHANNEL2 as an analog function."       },       {         "number": "20",         "name": "GPIO19",         "type": "bidirectional",-        "description": "IO pin powered by VDD_IO_0, with ADC1_CHANNEL3 analog function, default drive strength 20 mA."+        "description": "GPIO19 is powered by VDD_IO_0 and offers ADC1_CHANNEL3 as an analog function."       },       {         "number": "21",         "name": "VDD_IO_0",         "type": "power_in",-        "description": "Digital power domain supply for HP IO pins GPIO16 to GPIO23; recommended input voltage 1.65 to 3.6 V."+        "description": "Digital HP IO supply for GPIO16 to GPIO23, recommended 1.65 to 3.6 V (3.3 V typ) per Table 5-2."       },       {         "number": "22",         "name": "GPIO20",         "type": "bidirectional",-        "description": "IO pin powered by VDD_IO_0, with ADC1_CHANNEL4 analog function, default drive strength 20 mA."+        "description": "GPIO20 is powered by VDD_IO_0 and offers ADC1_CHANNEL4 as an analog function."       },       {         "number": "23",         "name": "GPIO21",         "type": "bidirectional",-        "description": "IO pin powered by VDD_IO_0, with ADC1_CHANNEL5 analog function, default drive strength 20 mA."+        "description": "GPIO21 is powered by VDD_IO_0 and offers ADC1_CHANNEL5 as an analog function."       },       {         "number": "24",         "name": "GPIO22",         "type": "bidirectional",-        "description": "IO pin powered by VDD_IO_0, with ADC1_CHANNEL6 analog function, default drive strength 20 mA."+        "description": "GPIO22 is powered by VDD_IO_0 and offers ADC1_CHANNEL6 as an analog function."       },       {         "number": "25",         "name": "GPIO23",         "type": "bidirectional",-        "description": "IO pin powered by VDD_IO_0, with ADC1_CHANNEL7 analog function and REF_50M_CLK_PAD output on IO MUX F2, default drive strength 20 mA."+        "description": "GPIO23 is powered by VDD_IO_0 and offers ADC1_CHANNEL7 and the REF_50M_CLK output."       },       {         "number": "26",         "name": "VDD_HP_0",         "type": "power_in",-        "description": "Digital power domain supply pin regulated by the external DC/DC via FB_DCDC; allowed input voltage 0 to 1.3 V."+        "description": "HP digital core supply, recommended 0.99 to 1.3 V (1.1 V typ) per Table 5-2."       },       {         "number": "27",         "name": "FLASH_CS",         "type": "output",-        "description": "Dedicated chip-select output to off-package flash, powered by VDD_FLASHIO."+        "description": "Dedicated chip-select output to the off-package flash, powered by VDD_FLASHIO."       },       {         "number": "28",         "name": "FLASH_Q",         "type": "bidirectional",-        "description": "Dedicated flash data-output (DO) pin to off-package flash, powered by VDD_FLASHIO."+        "description": "Dedicated flash data output line (DO) for off-package flash, powered by VDD_FLASHIO."       },       {         "number": "29",         "name": "FLASH_WP",         "type": "bidirectional",-        "description": "Dedicated flash write-protect (WP#) pin to off-package flash, powered by VDD_FLASHIO."+        "description": "Dedicated flash write-protect line (WP#) for off-package flash, powered by VDD_FLASHIO."       },       {         "number": "30",         "name": "VDD_FLASHIO",         "type": "power_in",-        "description": "Power supply for flash IO pins; the voltage should be adjusted to the flash model, with 3.3 V flash used as the example in the datasheet."+        "description": "Power supply for flash IO, which should be adjusted to the flash model (3.3 V flash used as the example)."       },       {         "number": "31",         "name": "FLASH_HOLD",         "type": "bidirectional",-        "description": "Dedicated flash HOLD# pin to off-package flash, powered by VDD_FLASHIO."+        "description": "Dedicated flash HOLD# line for off-package flash, powered by VDD_FLASHIO."       },       {         "number": "32",         "name": "FLASH_CK",         "type": "output",-        "description": "Dedicated flash clock output to off-package flash, powered by VDD_FLASHIO."+        "description": "Dedicated flash clock output for off-package flash, powered by VDD_FLASHIO."       },       {         "number": "33",         "name": "FLASH_D",         "type": "bidirectional",-        "description": "Dedicated flash data-input (DI) pin to off-package flash, powered by VDD_FLASHIO."+        "description": "Dedicated flash data input line (DI) for off-package flash, powered by VDD_FLASHIO."       },       {         "number": "34",         "name": "DSI_REXT",         "type": "bidirectional",-        "description": "MIPI DSI PHY external 4.02 kΩ reference resistor pin, powered by VDD_MIPI_DPHY."+        "description": "Connects the external 4.02 kΩ reference resistor for the MIPI DSI PHY."       },       {         "number": "35",         "name": "DSI_DATAP1",         "type": "bidirectional",-        "description": "MIPI DSI PHY data positive channel 1 pin, powered by VDD_MIPI_DPHY."+        "description": "MIPI DSI PHY positive data channel 1, powered by VDD_MIPI_DPHY."       },       {         "number": "36",         "name": "DSI_DATAN1",         "type": "bidirectional",-        "description": "MIPI DSI PHY data negative channel 1 pin, powered by VDD_MIPI_DPHY."+        "description": "MIPI DSI PHY negative data channel 1, powered by VDD_MIPI_DPHY."       },       {         "number": "37",         "name": "DSI_CLKN",         "type": "bidirectional",-        "description": "MIPI DSI PHY clock negative pin, powered by VDD_MIPI_DPHY."+        "description": "MIPI DSI PHY negative clock channel, powered by VDD_MIPI_DPHY."       },       {         "number": "38",         "name": "DSI_CLKP",         "type": "bidirectional",-        "description": "MIPI DSI PHY clock positive pin, powered by VDD_MIPI_DPHY."+        "description": "MIPI DSI PHY positive clock channel, powered by VDD_MIPI_DPHY."       },       {         "number": "39",         "name": "DSI_DATAP0",         "type": "bidirectional",-        "description": "MIPI DSI PHY data positive channel 0 pin, powered by VDD_MIPI_DPHY."+        "description": "MIPI DSI PHY positive data channel 0, powered by VDD_MIPI_DPHY."       },       {         "number": "40",         "name": "DSI_DATAN0",         "type": "bidirectional",-        "description": "MIPI DSI PHY data negative channel 0 pin, powered by VDD_MIPI_DPHY."+        "description": "MIPI DSI PHY negative data channel 0, powered by VDD_MIPI_DPHY."       },       {         "number": "41",         "name": "VDD_MIPI_DPHY",         "type": "power_in",-        "description": "Supply for the MIPI PHY pins; allowed input voltage 0 to 2.75 V."+        "description": "MIPI PHY supply, recommended 2.25 to 2.75 V (2.5 V typ) per Table 5-2."       },       {         "number": "42",         "name": "CSI_DATAN0",         "type": "bidirectional",-        "description": "MIPI CSI PHY data negative channel 0 pin, powered by VDD_MIPI_DPHY."+        "description": "MIPI CSI PHY negative data channel 0, powered by VDD_MIPI_DPHY."       },       {         "number": "43",         "name": "CSI_DATAP0",         "type": "bidirectional",-        "description": "MIPI CSI PHY data positive channel 0 pin, powered by VDD_MIPI_DPHY."+        "description": "MIPI CSI PHY positive data channel 0, powered by VDD_MIPI_DPHY."       },       {         "number": "44",         "name": "CSI_CLKP",         "type": "bidirectional",-        "description": "MIPI CSI PHY clock positive pin, powered by VDD_MIPI_DPHY."+        "description": "MIPI CSI PHY positive clock channel, powered by VDD_MIPI_DPHY."       },       {         "number": "45",         "name": "CSI_CLKN",         "type": "bidirectional",-        "description": "MIPI CSI PHY clock negative pin, powered by VDD_MIPI_DPHY."+        "description": "MIPI CSI PHY negative clock channel, powered by VDD_MIPI_DPHY."       },       {         "number": "46",         "name": "CSI_DATAN1",         "type": "bidirectional",-        "description": "MIPI CSI PHY data negative channel 1 pin, powered by VDD_MIPI_DPHY."+        "description": "MIPI CSI PHY negative data channel 1, powered by VDD_MIPI_DPHY."       },       {         "number": "47",         "name": "CSI_DATAP1",         "type": "bidirectional",-        "description": "MIPI CSI PHY data positive channel 1 pin, powered by VDD_MIPI_DPHY."+        "description": "MIPI CSI PHY positive data channel 1, powered by VDD_MIPI_DPHY."       },       {         "number": "48",         "name": "CSI_REXT",         "type": "bidirectional",-        "description": "MIPI CSI PHY external 4.02 kΩ reference resistor pin, powered by VDD_MIPI_DPHY."+        "description": "Connects the external 4.02 kΩ reference resistor for the MIPI CSI PHY."       },       {         "number": "49",         "name": "USB_DM",         "type": "bidirectional",-        "description": "USB 2.0 High-Speed OTG PHY D- pin, powered by VDD_USBPHY."+        "description": "USB 2.0 OTG high-speed PHY D- signal, powered by VDD_USBPHY (2.97 to 3.63 V)."       },       {         "number": "50",         "name": "USB_DP",         "type": "bidirectional",-        "description": "USB 2.0 High-Speed OTG PHY D+ pin, powered by VDD_USBPHY."+        "description": "USB 2.0 OTG high-speed PHY D+ signal, powered by VDD_USBPHY (2.97 to 3.63 V)."       },       {         "number": "51",         "name": "VDD_USBPHY",         "type": "power_in",-        "description": "Supply for the USB PHY pins; allowed input voltage -0.66 to 3.96 V."+        "description": "USB PHY supply, recommended 2.97 to 3.63 V (3.3 V typ) per Table 5-2."       },       {         "number": "52",         "name": "GPIO24",         "type": "bidirectional",-        "description": "IO pin powered by VDD_IO_4 with USB1P1_N0 analog function, default drive strength 40 mA."+        "description": "GPIO24 is powered by VDD_IO_4 with a default drive strength of 40 mA and offers USB1P1_N0."       },       {         "number": "53",         "name": "GPIO25",         "type": "bidirectional",-        "description": "IO pin powered by VDD_IO_4 with USB1P1_P0 analog function, default drive strength 40 mA."+        "description": "GPIO25 is powered by VDD_IO_4 with a default drive strength of 40 mA, USB pull-up enabled at reset, and offers USB1P1_P0."       },       {         "number": "54",-        "name": "VDD_HP_1",-        "type": "power_in",-        "description": "Digital power domain supply pin regulated by the external DC/DC via FB_DCDC; allowed input voltage 0 to 1.3 V."+        "name": "NC",+        "type": "unconnected",+        "description": "Pin is not connected (NC) in the package."       },       {         "number": "55",         "name": "GPIO26",         "type": "bidirectional",-        "description": "IO pin powered by VDD_IO_4 with USB1P1_N1 analog function, default drive strength 20 mA."+        "description": "GPIO26 is powered by VDD_IO_4 with a default drive strength of 20 mA and offers USB1P1_N1."       },       {         "number": "56",         "name": "GPIO27",         "type": "bidirectional",-        "description": "IO pin powered by VDD_IO_4 with USB1P1_P1 analog function, default drive strength 20 mA."+        "description": "GPIO27 is powered by VDD_IO_4 with a default drive strength of 20 mA and offers USB1P1_P1."       },       {         "number": "57",         "name": "GPIO28",         "type": "bidirectional",-        "description": "IO pin powered by VDD_IO_4 with SPI2_CS_PAD and GMAC_PHY_RXDV_PAD functions, default drive strength 20 mA."+        "description": "GPIO28 is powered by VDD_IO_4 and offers SPI2_CS and the GMAC_PHY_RXDV input."       },       {         "number": "58",         "name": "GPIO29",         "type": "bidirectional",-        "description": "IO pin powered by VDD_IO_4 with SPI2_D_PAD and GMAC_PHY_RXD0_PAD functions, default drive strength 20 mA."+        "description": "GPIO29 is powered by VDD_IO_4 and offers SPI2_D and the GMAC_PHY_RXD0 input."       },       {         "number": "59",         "name": "VDD_PSRAM_0",         "type": "power_in",-        "description": "PSRAM power supply pin; recommended input voltage 1.65 to 1.95 V for the 1.8 V PSRAM."+        "description": "In-package PSRAM supply, recommended 1.65 to 1.95 V (1.8 V typ) per Table 5-2."       },       {         "number": "60",         "name": "GPIO30",         "type": "bidirectional",-        "description": "IO pin powered by VDD_IO_4 with SPI2_CK_PAD and GMAC_PHY_RXD1_PAD functions, default drive strength 20 mA."+        "description": "GPIO30 is powered by VDD_IO_4 and offers SPI2_CK and the GMAC_PHY_RXD1 input."       },       {         "number": "61",         "name": "GPIO31",         "type": "bidirectional",-        "description": "IO pin powered by VDD_IO_4 with SPI2_Q_PAD and GMAC_PHY_RXER_PAD functions, default drive strength 20 mA."+        "description": "GPIO31 is powered by VDD_IO_4 and offers SPI2_Q and the GMAC_PHY_RXER input."       },       {         "number": "62",         "name": "VDD_IO_4",         "type": "power_in",-        "description": "Digital power domain supply for HP IO pins GPIO24 to GPIO38; recommended input voltage 1.65 to 3.6 V."+        "description": "Digital HP IO supply for GPIO24 to GPIO38, recommended 1.65 to 3.6 V (3.3 V typ) per Table 5-2."       },       {         "number": "63",         "name": "GPIO32",         "type": "bidirectional",-        "description": "IO pin powered by VDD_IO_4, input enabled at reset, with SPI2_HOLD_PAD, I3C_MST_SCL_PAD (configurable pull-up) and GMAC_RMII_CLK_PAD functions."+        "description": "GPIO32 is powered by VDD_IO_4, has input enable at reset, and offers SPI2_HOLD and the GMAC_RMII_CLK input."       },       {         "number": "64",         "name": "GPIO33",         "type": "bidirectional",-        "description": "IO pin powered by VDD_IO_4, input enabled at reset, with SPI2_WP_PAD, I3C_MST_SDA_PAD (configurable pull-up) and GMAC_PHY_TXEN_PAD functions."+        "description": "GPIO33 is powered by VDD_IO_4, has input enable at reset, and offers SPI2_WP and the GMAC_PHY_TXEN output."       },       {         "number": "65",         "name": "GPIO34",         "type": "bidirectional",-        "description": "IO pin powered by VDD_IO_4, input enabled at reset, a strapping pin for JTAG signal source control, with SPI2_IO4_PAD and GMAC_PHY_TXD0_PAD functions."+        "description": "GPIO34 is powered by VDD_IO_4 with input enable at reset, and is the strapping pin for the JTAG signal source control."       },       {         "number": "66",         "name": "GPIO35",         "type": "bidirectional",-        "description": "IO pin powered by VDD_IO_4, input enabled with weak pull-up at reset, a strapping pin for chip boot mode, with SPI2_IO5_PAD and GMAC_PHY_TXD1_PAD functions."+        "description": "GPIO35 is powered by VDD_IO_4 with input enable and weak pull-up at reset, and is the default-high strapping pin for boot mode control."       },       {         "number": "67",         "name": "VDD_PSRAM_1",         "type": "power_in",-        "description": "PSRAM power supply pin; recommended input voltage 1.65 to 1.95 V for the 1.8 V PSRAM."+        "description": "In-package PSRAM supply, recommended 1.65 to 1.95 V (1.8 V typ) per Table 5-2."       },       {         "number": "68",         "name": "GPIO36",         "type": "bidirectional",-        "description": "IO pin powered by VDD_IO_4, input enabled at reset, a strapping pin for ROM message printing control, with SPI2_IO6_PAD and GMAC_PHY_TXER_PAD functions."+        "description": "GPIO36 is powered by VDD_IO_4 with input enable at reset, and is the strapping pin for ROM message printing control."       },       {         "number": "69",         "name": "GPIO37",         "type": "bidirectional",-        "description": "IO pin powered by VDD_IO_4, a strapping pin for chip boot mode, with UART0_TXD_PAD and SPI2_IO7_PAD functions."+        "description": "GPIO37 is powered by VDD_IO_4 with input enable at reset, a boot mode strapping pin, and offers the UART0_TXD output."       },       {         "number": "70",         "name": "GPIO38",         "type": "bidirectional",-        "description": "IO pin powered by VDD_IO_4, input enabled at reset, a strapping pin for chip boot mode, with UART0_RXD_PAD and SPI2_DQS_PAD functions."+        "description": "GPIO38 is powered by VDD_IO_4 with input enable at reset, a boot mode strapping pin, and offers the UART0_RXD input."       },       {         "number": "71",         "name": "VDDO_FLASH",         "type": "power_out",-        "description": "Output supply for off-package flash, delivering up to 50 mA at maximum."+        "description": "Flash power output, 3.3 V by default or 1.8 V after EFUSE_0PXA_TIEH_SEL_0 is burnt, supplying up to 50 mA."       },       {         "number": "72",         "name": "VDDO_PSRAM",         "type": "power_out",-        "description": "Output supply for in-package and off-package PSRAM, delivering up to 50 mA at maximum."+        "description": "Output rail for in-package and off-package PSRAM, supplying up to 50 mA."       },       {         "number": "73",         "name": "VDDO_3",         "type": "power_out",-        "description": "Output supply from a voltage regulator, delivering up to 50 mA at maximum."+        "description": "VO3 LDO output rail for external devices, configurable 0.5 to 2.7 V or 3.3 V, supplying up to 50 mA."       },       {         "number": "74",         "name": "VDDO_4",         "type": "power_out",-        "description": "Output supply from a voltage regulator, delivering up to 50 mA at maximum."+        "description": "VO4 LDO output rail for external devices, configurable 0.5 to 2.7 V or 3.3 V, supplying up to 50 mA."       },       {         "number": "75",         "name": "VDD_LDO",         "type": "power_in",-        "description": "Analog power domain supply providing power for LDOs; recommended input voltage 3.0 to 3.6 V."+        "description": "Analog power domain input that provides power for the LDOs, recommended 3.0 to 3.6 V."       },       {         "number": "76",         "name": "VDD_HP_2",         "type": "power_in",-        "description": "Digital power domain supply pin regulated by the external DC/DC via FB_DCDC; allowed input voltage 0 to 1.3 V."+        "description": "HP digital core supply, recommended 0.99 to 1.3 V (1.1 V typ) per Table 5-2."       },       {         "number": "77",         "name": "VDD_DCDCC",         "type": "power_in",-        "description": "Analog power domain supply for DC/DC control; recommended input voltage 3.0 to 3.6 V."+        "description": "Analog power domain input for DC/DC control, recommended 3.0 to 3.6 V."       },       {         "number": "78",         "name": "FB_DCDC",         "type": "passive",-        "description": "Feedback pin of the external DC/DC supply, which regulates VDD_HP_0/1/2/3 together with feedback resistors."+        "description": "Feedback pin of the external DC/DC supply, which regulates VDD_HP_0/2/3 together with feedback resistors."       },       {         "number": "79",         "name": "EN_DCDC",         "type": "output",-        "description": "Enable output pin for the external DC/DC converter."+        "description": "Enable output for the external DC/DC converter."       },       {         "number": "80",         "name": "GPIO39",         "type": "bidirectional",-        "description": "IO pin powered by VDD_IO_5 with SD1_CDATA0_PAD and REF_50M_CLK_PAD output functions."+        "description": "GPIO39 is powered by VDD_IO_5 and offers SD1_CDATA0 and the REF_50M_CLK output."       },       {         "number": "81",         "name": "GPIO40",         "type": "bidirectional",-        "description": "IO pin powered by VDD_IO_5 with SD1_CDATA1_PAD and GMAC_PHY_TXEN_PAD output functions."+        "description": "GPIO40 is powered by VDD_IO_5 and offers SD1_CDATA1 and the GMAC_PHY_TXEN output."       },       {         "number": "82",         "name": "GPIO41",         "type": "bidirectional",-        "description": "IO pin powered by VDD_IO_5 with SD1_CDATA2_PAD and GMAC_PHY_TXD0_PAD output functions."+        "description": "GPIO41 is powered by VDD_IO_5 and offers SD1_CDATA2 and the GMAC_PHY_TXD0 output."       },       {         "number": "83",         "name": "GPIO42",         "type": "bidirectional",-        "description": "IO pin powered by VDD_IO_5 with SD1_CDATA3_PAD and GMAC_PHY_TXD1_PAD output functions."+        "description": "GPIO42 is powered by VDD_IO_5 and offers SD1_CDATA3 and the GMAC_PHY_TXD1 output."       },       {         "number": "84",         "name": "GPIO43",         "type": "bidirectional",-        "description": "IO pin powered by VDD_IO_5 with SD1_CCLK_PAD and GMAC_PHY_TXER_PAD output functions."+        "description": "GPIO43 is powered by VDD_IO_5 and offers the SD1_CCLK output and the GMAC_PHY_TXER output."       },       {         "number": "85",         "name": "VDD_IO_5",         "type": "power_in",-        "description": "Digital power domain supply for HP IO pins GPIO39 to GPIO48; recommended input voltage 1.65 to 3.6 V."+        "description": "Digital HP IO supply for GPIO39 to GPIO48, recommended 1.65 to 3.6 V (3.3 V typ) per Table 5-2."       },       {         "number": "86",         "name": "GPIO44",         "type": "bidirectional",-        "description": "IO pin powered by VDD_IO_5 with SD1_CCMD_PAD and GMAC_RMII_CLK_PAD functions."+        "description": "GPIO44 is powered by VDD_IO_5 and offers SD1_CCMD and the GMAC_RMII_CLK input."       },       {         "number": "87",         "name": "GPIO45",         "type": "bidirectional",-        "description": "IO pin powered by VDD_IO_5 with SD1_CDATA4_PAD and GMAC_PHY_RXDV_PAD functions."+        "description": "GPIO45 is powered by VDD_IO_5 and offers SD1_CDATA4 and the GMAC_PHY_RXDV input."       },       {         "number": "88",         "name": "GPIO46",         "type": "bidirectional",-        "description": "IO pin powered by VDD_IO_5 with SD1_CDATA5_PAD and GMAC_PHY_RXD0_PAD functions."+        "description": "GPIO46 is powered by VDD_IO_5 and offers SD1_CDATA5 and the GMAC_PHY_RXD0 input."       },       {         "number": "89",         "name": "GPIO47",         "type": "bidirectional",-        "description": "IO pin powered by VDD_IO_5 with SD1_CDATA6_PAD and GMAC_PHY_RXD1_PAD functions."+        "description": "GPIO47 is powered by VDD_IO_5 and offers SD1_CDATA6 and the GMAC_PHY_RXD1 input."       },       {         "number": "90",         "name": "GPIO48",         "type": "bidirectional",-        "description": "IO pin powered by VDD_IO_5 with SD1_CDATA7_PAD and GMAC_PHY_RXER_PAD functions."+        "description": "GPIO48 is powered by VDD_IO_5 and offers SD1_CDATA7 and the GMAC_PHY_RXER input."       },       {         "number": "91",         "name": "VDD_HP_3",         "type": "power_in",-        "description": "Digital power domain supply pin regulated by the external DC/DC via FB_DCDC; allowed input voltage 0 to 1.3 V."+        "description": "HP digital core supply, recommended 0.99 to 1.3 V (1.1 V typ) per Table 5-2."       },       {         "number": "92",         "name": "GPIO49",         "type": "bidirectional",-        "description": "IO pin powered by VDD_IO_6 with ADC2_CHANNEL0 analog function and GMAC_PHY_TXEN_PAD output on IO MUX F2."+        "description": "GPIO49 is powered by VDD_IO_6, offers ADC2_CHANNEL0, and offers the GMAC_PHY_TXEN output."       },       {         "number": "93",         "name": "GPIO50",         "type": "bidirectional",-        "description": "IO pin powered by VDD_IO_6 with ADC2_CHANNEL1 analog function and GMAC_RMII_CLK_PAD on IO MUX F2."+        "description": "GPIO50 is powered by VDD_IO_6, offers ADC2_CHANNEL1, and offers the GMAC_RMII_CLK input."       },       {         "number": "94",         "name": "GPIO51",         "type": "bidirectional",-        "description": "IO pin powered by VDD_IO_6 with ADC2_CHANNEL2, ANA_COMP0 analog function and GMAC_PHY_RXDV_PAD on IO MUX F2."+        "description": "GPIO51 is powered by VDD_IO_6, offers ADC2_CHANNEL2, and offers ANA_COMP0."       },       {         "number": "95",         "name": "GPIO52",         "type": "bidirectional",-        "description": "IO pin powered by VDD_IO_6 with ADC2_CHANNEL3, ANA_COMP0 analog function and GMAC_PHY_RXD0_PAD on IO MUX F2."+        "description": "GPIO52 is powered by VDD_IO_6, offers ADC2_CHANNEL3, and offers ANA_COMP0."       },       {         "number": "96",         "name": "VDD_IO_6",         "type": "power_in",-        "description": "Digital power domain supply for HP IO pins GPIO49 to GPIO54; recommended input voltage 1.65 to 3.6 V."+        "description": "Digital HP IO supply for GPIO49 to GPIO54, recommended 1.65 to 3.6 V (3.3 V typ) per Table 5-2."       },       {         "number": "97",         "name": "GPIO53",         "type": "bidirectional",-        "description": "IO pin powered by VDD_IO_6 with ADC2_CHANNEL4, ANA_COMP1 analog function and GMAC_PHY_RXD1_PAD on IO MUX F2."+        "description": "GPIO53 is powered by VDD_IO_6, offers ADC2_CHANNEL4, and offers ANA_COMP1."       },       {         "number": "98",         "name": "GPIO54",         "type": "bidirectional",-        "description": "IO pin powered by VDD_IO_6 with ADC2_CHANNEL5, ANA_COMP1 analog function and GMAC_PHY_RXER_PAD on IO MUX F2."+        "description": "GPIO54 is powered by VDD_IO_6, offers ADC2_CHANNEL5, and offers ANA_COMP1."       },       {         "number": "99",         "name": "XTAL_N",         "type": "passive",-        "description": "External clock input/output connected to the chip's crystal or oscillator, negative side of the differential clock."+        "description": "Negative side of the external clock input/output connected to the chip crystal or oscillator (40 MHz XTAL_CLK)."       },       {         "number": "100",         "name": "XTAL_P",         "type": "passive",-        "description": "External clock input/output connected to the chip's crystal or oscillator, positive side of the differential clock."+        "description": "Positive side of the external clock input/output connected to the chip crystal or oscillator (40 MHz XTAL_CLK)."       },       {         "number": "101",         "name": "VDD_ANA",         "type": "power_in",-        "description": "Analog power domain supply; recommended input voltage 3.0 to 3.6 V."+        "description": "Analog power domain supply, recommended 3.0 to 3.6 V."       },       {         "number": "102",         "name": "VDD_BAT",         "type": "power_in",-        "description": "Analog power domain supply, optionally connected to an external battery; recommended input voltage 2.5 to 3.6 V."+        "description": "Analog power domain input that can optionally connect to an external battery, recommended 2.5 to 3.6 V."       },       {         "number": "103",         "name": "CHIP_PU",         "type": "input",-        "description": "Chip enable: high enables the chip and low powers it down; the pin must not be left floating."+        "description": "Chip enable: high powers up and enables the chip, low powers it down, and it must not be left floating."       },       {         "number": "104",         "name": "GPIO0",         "type": "bidirectional",-        "description": "IO pin powered by VDD_LP/VDD_BAT with XTAL_32K_N analog function and LP_GPIO0, default drive strength 20 mA."+        "description": "GPIO0 is powered by VDD_LP or VDD_BAT and also offers LP_GPIO0 and XTAL_32K_N analog function."       },       {         "number": "105",@@ -688,16 +687,16 @@         "consensus": "agreed",         "guards": "pin_guards 0.1: passed",         "guard_notes": [-          "extractor flagged: The requested MPN ESP32-P4NRW32 matches the datasheet part ESP32-P4NRW32X (32 MB in-package PSRAM). ; The datasheet is a preliminary pre-release v0.7 and states its electrical values may change; Table 2"+          "extractor flagged: The MPN ESP32-P4NRW32 is marked End of Life in this datasheet (upgraded to ESP32-P4NRW32X). The pino; Table 2-11 lists VDD_FLASHIO2 with a footnote, while Table 2-1 and Figure 2-1 name the pin VDD_FLASH; Pin 54 is printed as NC and pin 105 is GND, which is the package ground pad. Pin 105 is typed power_"         ],-        "pages_sent": 65,-        "cost_usd": 0.2616,-        "at": "2026-10-27T22:15:29"+        "pages_sent": 94,+        "cost_usd": 0.2826,+        "at": "2026-10-27T22:22:15"       },       "datasheet": {-        "url": "https://www.espressif.com/sites/default/files/documentation/esp32-p4_datasheet_en.pdf",-        "pages": 102,-        "sha256": "fb4f3e91cc2ac519",+        "url": "https://www.espressif.com/sites/default/files/documentation/esp32-p4-chip-revision-v1.3_datasheet_en.pdf",+        "pages": 94,+        "sha256": "52ef629ec92510a6",         "source_tier": "mfr"       },       "cad": "KiCad official (CC-BY-SA 4.0)",@@ -728,26 +727,7 @@         "zmin_mm": 0,         "centre_offset_mm": 0,         "footprint_binding": "none",-        "sha256": "29d170305521a2d9435f9c70f5887fca9d93d9ab3cb1fbf2c26ae9f913506674",-        "checked": "2026-10-27",-        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"-      },-      {-        "file": "esp32-p4nrw32-etched.step",-        "role": "eda",-        "up": "Z",-        "units": "mm",-        "origin": "footprint origin = pad-pattern centre",-        "seat": "z = 0",-        "extents_mm": [-          10.02,-          10.02,-          0.85-        ],-        "zmin_mm": 0,-        "centre_offset_mm": 0,-        "footprint_binding": "none",-        "sha256": "c470ee02e3362bd96141e6f6a4f508ad11a9c045336f6bf77e47debd005a3ed3",+        "sha256": "4768606132501b6e08a104c25fd4482e49df118ce235014d13dd1b2ecba470ee",         "checked": "2026-10-27",         "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"       }@@ -1138,10 +1118,9 @@     "viewers/symbol.html",     "viewers/footprint.html",     "esp32-p4nrw32-hero.glb",-    "esp32-p4nrw32-hero.overlay.json",-    "esp32-p4nrw32-etched.glb"+    "esp32-p4nrw32-hero.overlay.json"   ],-  "visibility": {-    "public": true-  }+  "visibility": "public",+  "description": "ESPRESSIF Functional Modules, QFN-104(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+  "org": "adom" }\ No newline at end of file