ESP32-P4NRW32

@@ -8,111 +8,111 @@ ESP32-P4NRW32 from ESPRESSIF, in a QFN-104(10x10). Pinout and pin descriptions e  | Pin | Name | Type | Function | |---|---|---|---|-| 1 | GPIO1 | bidirectional | GPIO1 is powered by VDD_LP or VDD_BAT and also offers LP IO MUX and XTAL_32K_P analog functions. |-| 2 | GPIO2 | bidirectional | GPIO2 is powered by VDD_LP or VDD_BAT, has input enable and weak pull-up enabled at reset, and offers MTCK and touch channel 1. |-| 3 | GPIO3 | bidirectional | GPIO3 is powered by VDD_LP or VDD_BAT, has input enable at reset, and offers MTDI and touch channel 2. |-| 4 | GPIO4 | bidirectional | GPIO4 is powered by VDD_LP, has input enable at reset, and offers MTMS and touch channel 3. |-| 5 | GPIO5 | bidirectional | GPIO5 is powered by VDD_LP and offers the MTDO JTAG output and touch channel 4. |-| 6 | GPIO6 | bidirectional | GPIO6 is powered by VDD_LP and offers SPI2_HOLD and touch channel 5. |-| 7 | GPIO7 | bidirectional | GPIO7 is powered by VDD_LP and offers SPI2_CS and touch channel 6. |-| 8 | GPIO8 | bidirectional | GPIO8 is powered by VDD_LP and offers SPI2_D and touch channel 7. |-| 9 | VDD_LP | power_in | LP power domain supply input, recommended 3.0 to 3.6 V (3.3 V typ) per Table 5-2. |-| 10 | GPIO9 | bidirectional | GPIO9 is powered by VDD_LP and offers SPI2_CK and touch channel 8. |-| 11 | GPIO10 | bidirectional | GPIO10 is powered by VDD_LP and offers SPI2_Q and touch channel 9. |-| 12 | GPIO11 | bidirectional | GPIO11 is powered by VDD_LP and offers SPI2_WP and touch channel 10. |-| 13 | GPIO12 | bidirectional | GPIO12 is powered by VDD_LP and offers touch channel 11. |-| 14 | GPIO13 | bidirectional | GPIO13 is powered by VDD_LP and offers touch channel 12. |-| 15 | GPIO14 | bidirectional | GPIO14 is powered by VDD_LP and offers LP_UART_TXD and touch channel 13. |-| 16 | GPIO15 | bidirectional | GPIO15 is powered by VDD_LP and offers LP_UART_RXD and touch channel 14. |-| 17 | GPIO16 | bidirectional | GPIO16 is powered by VDD_IO_0 and offers ADC1_CHANNEL0 as an analog function. |-| 18 | GPIO17 | bidirectional | GPIO17 is powered by VDD_IO_0 and offers ADC1_CHANNEL1 as an analog function. |-| 19 | GPIO18 | bidirectional | GPIO18 is powered by VDD_IO_0 and offers ADC1_CHANNEL2 as an analog function. |-| 20 | GPIO19 | bidirectional | GPIO19 is powered by VDD_IO_0 and offers ADC1_CHANNEL3 as an analog function. |-| 21 | VDD_IO_0 | power_in | Digital HP IO supply for GPIO16 to GPIO23, recommended 1.65 to 3.6 V (3.3 V typ) per Table 5-2. |-| 22 | GPIO20 | bidirectional | GPIO20 is powered by VDD_IO_0 and offers ADC1_CHANNEL4 as an analog function. |-| 23 | GPIO21 | bidirectional | GPIO21 is powered by VDD_IO_0 and offers ADC1_CHANNEL5 as an analog function. |-| 24 | GPIO22 | bidirectional | GPIO22 is powered by VDD_IO_0 and offers ADC1_CHANNEL6 as an analog function. |-| 25 | GPIO23 | bidirectional | GPIO23 is powered by VDD_IO_0 and offers ADC1_CHANNEL7 and the REF_50M_CLK output. |-| 26 | VDD_HP_0 | power_in | HP digital core supply, recommended 0.99 to 1.3 V (1.1 V typ) per Table 5-2. |-| 27 | FLASH_CS | output | Dedicated chip-select output to the off-package flash, powered by VDD_FLASHIO. |-| 28 | FLASH_Q | bidirectional | Dedicated flash data output line (DO) for off-package flash, powered by VDD_FLASHIO. |-| 29 | FLASH_WP | bidirectional | Dedicated flash write-protect line (WP#) for off-package flash, powered by VDD_FLASHIO. |-| 30 | VDD_FLASHIO | power_in | Power supply for flash IO, which should be adjusted to the flash model (3.3 V flash used as the example). |-| 31 | FLASH_HOLD | bidirectional | Dedicated flash HOLD# line for off-package flash, powered by VDD_FLASHIO. |-| 32 | FLASH_CK | output | Dedicated flash clock output for off-package flash, powered by VDD_FLASHIO. |-| 33 | FLASH_D | bidirectional | Dedicated flash data input line (DI) for off-package flash, powered by VDD_FLASHIO. |-| 34 | DSI_REXT | bidirectional | Connects the external 4.02 kΩ reference resistor for the MIPI DSI PHY. |-| 35 | DSI_DATAP1 | bidirectional | MIPI DSI PHY positive data channel 1, powered by VDD_MIPI_DPHY. |-| 36 | DSI_DATAN1 | bidirectional | MIPI DSI PHY negative data channel 1, powered by VDD_MIPI_DPHY. |-| 37 | DSI_CLKN | bidirectional | MIPI DSI PHY negative clock channel, powered by VDD_MIPI_DPHY. |-| 38 | DSI_CLKP | bidirectional | MIPI DSI PHY positive clock channel, powered by VDD_MIPI_DPHY. |-| 39 | DSI_DATAP0 | bidirectional | MIPI DSI PHY positive data channel 0, powered by VDD_MIPI_DPHY. |-| 40 | DSI_DATAN0 | bidirectional | MIPI DSI PHY negative data channel 0, powered by VDD_MIPI_DPHY. |-| 41 | VDD_MIPI_DPHY | power_in | MIPI PHY supply, recommended 2.25 to 2.75 V (2.5 V typ) per Table 5-2. |-| 42 | CSI_DATAN0 | bidirectional | MIPI CSI PHY negative data channel 0, powered by VDD_MIPI_DPHY. |-| 43 | CSI_DATAP0 | bidirectional | MIPI CSI PHY positive data channel 0, powered by VDD_MIPI_DPHY. |-| 44 | CSI_CLKP | bidirectional | MIPI CSI PHY positive clock channel, powered by VDD_MIPI_DPHY. |-| 45 | CSI_CLKN | bidirectional | MIPI CSI PHY negative clock channel, powered by VDD_MIPI_DPHY. |-| 46 | CSI_DATAN1 | bidirectional | MIPI CSI PHY negative data channel 1, powered by VDD_MIPI_DPHY. |-| 47 | CSI_DATAP1 | bidirectional | MIPI CSI PHY positive data channel 1, powered by VDD_MIPI_DPHY. |-| 48 | CSI_REXT | bidirectional | Connects the external 4.02 kΩ reference resistor for the MIPI CSI PHY. |-| 49 | USB_DM | bidirectional | USB 2.0 OTG high-speed PHY D- signal, powered by VDD_USBPHY (2.97 to 3.63 V). |-| 50 | USB_DP | bidirectional | USB 2.0 OTG high-speed PHY D+ signal, powered by VDD_USBPHY (2.97 to 3.63 V). |-| 51 | VDD_USBPHY | power_in | USB PHY supply, recommended 2.97 to 3.63 V (3.3 V typ) per Table 5-2. |-| 52 | GPIO24 | bidirectional | GPIO24 is powered by VDD_IO_4 with a default drive strength of 40 mA and offers USB1P1_N0. |-| 53 | GPIO25 | bidirectional | GPIO25 is powered by VDD_IO_4 with a default drive strength of 40 mA, USB pull-up enabled at reset, and offers USB1P1_P0. |-| 54 | NC | unconnected | Pin is not connected (NC) in the package. |-| 55 | GPIO26 | bidirectional | GPIO26 is powered by VDD_IO_4 with a default drive strength of 20 mA and offers USB1P1_N1. |-| 56 | GPIO27 | bidirectional | GPIO27 is powered by VDD_IO_4 with a default drive strength of 20 mA and offers USB1P1_P1. |-| 57 | GPIO28 | bidirectional | GPIO28 is powered by VDD_IO_4 and offers SPI2_CS and the GMAC_PHY_RXDV input. |-| 58 | GPIO29 | bidirectional | GPIO29 is powered by VDD_IO_4 and offers SPI2_D and the GMAC_PHY_RXD0 input. |-| 59 | VDD_PSRAM_0 | power_in | In-package PSRAM supply, recommended 1.65 to 1.95 V (1.8 V typ) per Table 5-2. |-| 60 | GPIO30 | bidirectional | GPIO30 is powered by VDD_IO_4 and offers SPI2_CK and the GMAC_PHY_RXD1 input. |-| 61 | GPIO31 | bidirectional | GPIO31 is powered by VDD_IO_4 and offers SPI2_Q and the GMAC_PHY_RXER input. |-| 62 | VDD_IO_4 | power_in | Digital HP IO supply for GPIO24 to GPIO38, recommended 1.65 to 3.6 V (3.3 V typ) per Table 5-2. |-| 63 | GPIO32 | bidirectional | GPIO32 is powered by VDD_IO_4, has input enable at reset, and offers SPI2_HOLD and the GMAC_RMII_CLK input. |-| 64 | GPIO33 | bidirectional | GPIO33 is powered by VDD_IO_4, has input enable at reset, and offers SPI2_WP and the GMAC_PHY_TXEN output. |-| 65 | GPIO34 | bidirectional | GPIO34 is powered by VDD_IO_4 with input enable at reset, and is the strapping pin for the JTAG signal source control. |-| 66 | GPIO35 | bidirectional | GPIO35 is powered by VDD_IO_4 with input enable and weak pull-up at reset, and is the default-high strapping pin for boot mode control. |-| 67 | VDD_PSRAM_1 | power_in | In-package PSRAM supply, recommended 1.65 to 1.95 V (1.8 V typ) per Table 5-2. |-| 68 | GPIO36 | bidirectional | GPIO36 is powered by VDD_IO_4 with input enable at reset, and is the strapping pin for ROM message printing control. |-| 69 | GPIO37 | bidirectional | GPIO37 is powered by VDD_IO_4 with input enable at reset, a boot mode strapping pin, and offers the UART0_TXD output. |-| 70 | GPIO38 | bidirectional | GPIO38 is powered by VDD_IO_4 with input enable at reset, a boot mode strapping pin, and offers the UART0_RXD input. |-| 71 | VDDO_FLASH | power_out | Flash power output, 3.3 V by default or 1.8 V after EFUSE_0PXA_TIEH_SEL_0 is burnt, supplying up to 50 mA. |-| 72 | VDDO_PSRAM | power_out | Output rail for in-package and off-package PSRAM, supplying up to 50 mA. |-| 73 | VDDO_3 | power_out | VO3 LDO output rail for external devices, configurable 0.5 to 2.7 V or 3.3 V, supplying up to 50 mA. |-| 74 | VDDO_4 | power_out | VO4 LDO output rail for external devices, configurable 0.5 to 2.7 V or 3.3 V, supplying up to 50 mA. |-| 75 | VDD_LDO | power_in | Analog power domain input that provides power for the LDOs, recommended 3.0 to 3.6 V. |-| 76 | VDD_HP_2 | power_in | HP digital core supply, recommended 0.99 to 1.3 V (1.1 V typ) per Table 5-2. |-| 77 | VDD_DCDCC | power_in | Analog power domain input for DC/DC control, recommended 3.0 to 3.6 V. |-| 78 | FB_DCDC | passive | Feedback pin of the external DC/DC supply, which regulates VDD_HP_0/2/3 together with feedback resistors. |-| 79 | EN_DCDC | output | Enable output for the external DC/DC converter. |-| 80 | GPIO39 | bidirectional | GPIO39 is powered by VDD_IO_5 and offers SD1_CDATA0 and the REF_50M_CLK output. |-| 81 | GPIO40 | bidirectional | GPIO40 is powered by VDD_IO_5 and offers SD1_CDATA1 and the GMAC_PHY_TXEN output. |-| 82 | GPIO41 | bidirectional | GPIO41 is powered by VDD_IO_5 and offers SD1_CDATA2 and the GMAC_PHY_TXD0 output. |-| 83 | GPIO42 | bidirectional | GPIO42 is powered by VDD_IO_5 and offers SD1_CDATA3 and the GMAC_PHY_TXD1 output. |-| 84 | GPIO43 | bidirectional | GPIO43 is powered by VDD_IO_5 and offers the SD1_CCLK output and the GMAC_PHY_TXER output. |-| 85 | VDD_IO_5 | power_in | Digital HP IO supply for GPIO39 to GPIO48, recommended 1.65 to 3.6 V (3.3 V typ) per Table 5-2. |-| 86 | GPIO44 | bidirectional | GPIO44 is powered by VDD_IO_5 and offers SD1_CCMD and the GMAC_RMII_CLK input. |-| 87 | GPIO45 | bidirectional | GPIO45 is powered by VDD_IO_5 and offers SD1_CDATA4 and the GMAC_PHY_RXDV input. |-| 88 | GPIO46 | bidirectional | GPIO46 is powered by VDD_IO_5 and offers SD1_CDATA5 and the GMAC_PHY_RXD0 input. |-| 89 | GPIO47 | bidirectional | GPIO47 is powered by VDD_IO_5 and offers SD1_CDATA6 and the GMAC_PHY_RXD1 input. |-| 90 | GPIO48 | bidirectional | GPIO48 is powered by VDD_IO_5 and offers SD1_CDATA7 and the GMAC_PHY_RXER input. |-| 91 | VDD_HP_3 | power_in | HP digital core supply, recommended 0.99 to 1.3 V (1.1 V typ) per Table 5-2. |-| 92 | GPIO49 | bidirectional | GPIO49 is powered by VDD_IO_6, offers ADC2_CHANNEL0, and offers the GMAC_PHY_TXEN output. |-| 93 | GPIO50 | bidirectional | GPIO50 is powered by VDD_IO_6, offers ADC2_CHANNEL1, and offers the GMAC_RMII_CLK input. |-| 94 | GPIO51 | bidirectional | GPIO51 is powered by VDD_IO_6, offers ADC2_CHANNEL2, and offers ANA_COMP0. |-| 95 | GPIO52 | bidirectional | GPIO52 is powered by VDD_IO_6, offers ADC2_CHANNEL3, and offers ANA_COMP0. |-| 96 | VDD_IO_6 | power_in | Digital HP IO supply for GPIO49 to GPIO54, recommended 1.65 to 3.6 V (3.3 V typ) per Table 5-2. |-| 97 | GPIO53 | bidirectional | GPIO53 is powered by VDD_IO_6, offers ADC2_CHANNEL4, and offers ANA_COMP1. |-| 98 | GPIO54 | bidirectional | GPIO54 is powered by VDD_IO_6, offers ADC2_CHANNEL5, and offers ANA_COMP1. |-| 99 | XTAL_N | passive | Negative side of the external clock input/output connected to the chip crystal or oscillator (40 MHz XTAL_CLK). |-| 100 | XTAL_P | passive | Positive side of the external clock input/output connected to the chip crystal or oscillator (40 MHz XTAL_CLK). |-| 101 | VDD_ANA | power_in | Analog power domain supply, recommended 3.0 to 3.6 V. |-| 102 | VDD_BAT | power_in | Analog power domain input that can optionally connect to an external battery, recommended 2.5 to 3.6 V. |-| 103 | CHIP_PU | input | Chip enable: high powers up and enables the chip, low powers it down, and it must not be left floating. |-| 104 | GPIO0 | bidirectional | GPIO0 is powered by VDD_LP or VDD_BAT and also offers LP_GPIO0 and XTAL_32K_N analog function. |-| 105 | GND | power_in | External ground connection. |+| 1 | GPIO1 | bidirectional | GPIO1 is a general-purpose IO powered from VDD_LP/VDD_BAT that also carries the XTAL_32K_P analog function and LP_GPIO1 in Deep-sleep mode, with default drive strength 20 mA. |+| 2 | GPIO2 | bidirectional | GPIO2 is an LP IO powered from VDD_LP/VDD_BAT that carries the MTCK JTAG clock, TOUCH_CHANNEL1 and LP_GPIO2, and is input-enabled with weak pull-up at reset (EFUSE_DIS_PAD_JTAG dependent). |+| 3 | GPIO3 | bidirectional | GPIO3 is an LP IO powered from VDD_LP/VDD_BAT that carries the MTDI JTAG input, TOUCH_CHANNEL2 and LP_GPIO3, and is input-enabled at reset. |+| 4 | GPIO4 | bidirectional | GPIO4 is an LP IO powered from VDD_LP that carries the MTMS JTAG input, TOUCH_CHANNEL3 and LP_GPIO4, and is input-enabled at reset. |+| 5 | GPIO5 | bidirectional | GPIO5 is an LP IO powered from VDD_LP that carries the MTDO JTAG output (tri-state capable), TOUCH_CHANNEL4 and LP_GPIO5. |+| 6 | GPIO6 | bidirectional | GPIO6 is an LP IO powered from VDD_LP that carries the SPI2_HOLD_PAD (8-line/4-line SPI2 interface), TOUCH_CHANNEL5 and LP_GPIO6. |+| 7 | GPIO7 | bidirectional | GPIO7 is an LP IO powered from VDD_LP that carries the SPI2_CS_PAD chip select, TOUCH_CHANNEL6 and LP_GPIO7. |+| 8 | GPIO8 | bidirectional | GPIO8 is an LP IO powered from VDD_LP that carries the SPI2_D_PAD data input, TOUCH_CHANNEL7 and LP_GPIO8. |+| 9 | VDD_LP | power_in | VDD_LP is the LP power domain supply, recommended at 3.0 V to 3.6 V (typ. 3.3 V). |+| 10 | GPIO9 | bidirectional | GPIO9 is an LP IO powered from VDD_LP that carries the SPI2_CK_PAD clock, TOUCH_CHANNEL8 and LP_GPIO9. |+| 11 | GPIO10 | bidirectional | GPIO10 is an LP IO powered from VDD_LP that carries the SPI2_Q_PAD data output, TOUCH_CHANNEL9 and LP_GPIO10. |+| 12 | GPIO11 | bidirectional | GPIO11 is an LP IO powered from VDD_LP that carries the SPI2_WP_PAD write protect, TOUCH_CHANNEL10 and LP_GPIO11. |+| 13 | GPIO12 | bidirectional | GPIO12 is an LP IO powered from VDD_LP that carries TOUCH_CHANNEL11 and LP_GPIO12. |+| 14 | GPIO13 | bidirectional | GPIO13 is an LP IO powered from VDD_LP that carries TOUCH_CHANNEL12 and LP_GPIO13. |+| 15 | GPIO14 | bidirectional | GPIO14 is an LP IO powered from VDD_LP that carries the LP_UART_TXD_PAD transmit output, TOUCH_CHANNEL13 and LP_GPIO14. |+| 16 | GPIO15 | bidirectional | GPIO15 is an LP IO powered from VDD_LP that carries the LP_UART_RXD_PAD receive input, TOUCH_CHANNEL14 and LP_GPIO15. |+| 17 | GPIO16 | bidirectional | GPIO16 is an HP IO powered from VDD_IO_0 (1.65 V to 3.6 V) that carries the ADC1_CHANNEL0 analog input. |+| 18 | GPIO17 | bidirectional | GPIO17 is an HP IO powered from VDD_IO_0 (1.65 V to 3.6 V) that carries the ADC1_CHANNEL1 analog input. |+| 19 | GPIO18 | bidirectional | GPIO18 is an HP IO powered from VDD_IO_0 (1.65 V to 3.6 V) that carries the ADC1_CHANNEL2 analog input. |+| 20 | GPIO19 | bidirectional | GPIO19 is an HP IO powered from VDD_IO_0 (1.65 V to 3.6 V) that carries the ADC1_CHANNEL3 analog input. |+| 21 | VDD_IO_0 | power_in | VDD_IO_0 is the digital IO power supply for the HP IO group, recommended at 1.65 V to 3.6 V (typ. 3.3 V). |+| 22 | GPIO20 | bidirectional | GPIO20 is an HP IO powered from VDD_IO_0 (1.65 V to 3.6 V) that carries the ADC1_CHANNEL4 analog input. |+| 23 | GPIO21 | bidirectional | GPIO21 is an HP IO powered from VDD_IO_0 (1.65 V to 3.6 V) that carries the ADC1_CHANNEL5 analog input. |+| 24 | GPIO22 | bidirectional | GPIO22 is an HP IO powered from VDD_IO_0 (1.65 V to 3.6 V) that carries the ADC1_CHANNEL6 analog input. |+| 25 | GPIO23 | bidirectional | GPIO23 is an HP IO powered from VDD_IO_0 (1.65 V to 3.6 V) that carries the ADC1_CHANNEL7 analog input and the REF_50M_CLK_PAD 50 MHz reference clock output. |+| 26 | VDD_HP_0 | power_in | VDD_HP_0 is the digital core supply, recommended at 0.99 V to 1.3 V (typ. 1.1 V); the chip can adjust it automatically. |+| 27 | FLASH_CS | output | FLASH_CS is the dedicated off-package flash chip-select output, powered by VDD_FLASHIO. |+| 28 | FLASH_Q | bidirectional | FLASH_Q is the dedicated flash data-output line (DO) powered by VDD_FLASHIO. |+| 29 | FLASH_WP | bidirectional | FLASH_WP is the dedicated flash write-protect line (WP#) powered by VDD_FLASHIO. |+| 30 | VDD_FLASHIO | power_in | VDD_FLASHIO powers the flash IO and should be set according to the flash model; the datasheet uses 3.3 V flash as the example, with recommended input 1.65 V to 3.6 V. |+| 31 | FLASH_HOLD | bidirectional | FLASH_HOLD is the dedicated flash hold line (HOLD#) powered by VDD_FLASHIO. |+| 32 | FLASH_CK | output | FLASH_CK is the dedicated flash clock output (CLK) powered by VDD_FLASHIO. |+| 33 | FLASH_D | bidirectional | FLASH_D is the dedicated flash data-input line (DI) powered by VDD_FLASHIO. |+| 34 | DSI_REXT | bidirectional | DSI_REXT is the MIPI DSI PHY pin for the 4.02 kΩ external reference resistor, powered by VDD_MIPI_DPHY. |+| 35 | DSI_DATAP1 | bidirectional | DSI_DATAP1 is the positive data channel 1 of the MIPI DSI PHY (2-lane, 1.5 Gbps per lane), powered by VDD_MIPI_DPHY. |+| 36 | DSI_DATAN1 | bidirectional | DSI_DATAN1 is the negative data channel 1 of the MIPI DSI PHY, powered by VDD_MIPI_DPHY. |+| 37 | DSI_CLKN | bidirectional | DSI_CLKN is the negative clock channel of the MIPI DSI PHY, powered by VDD_MIPI_DPHY. |+| 38 | DSI_CLKP | bidirectional | DSI_CLKP is the positive clock channel of the MIPI DSI PHY, powered by VDD_MIPI_DPHY. |+| 39 | DSI_DATAP0 | bidirectional | DSI_DATAP0 is the positive data channel 0 of the MIPI DSI PHY, powered by VDD_MIPI_DPHY. |+| 40 | DSI_DATAN0 | bidirectional | DSI_DATAN0 is the negative data channel 0 of the MIPI DSI PHY, powered by VDD_MIPI_DPHY. |+| 41 | VDD_MIPI_DPHY | power_in | VDD_MIPI_DPHY is the MIPI PHY supply, recommended at 2.25 V to 2.75 V (typ. 2.5 V) with an absolute maximum of 2.75 V. |+| 42 | CSI_DATAN0 | bidirectional | CSI_DATAN0 is the negative data channel 0 of the MIPI CSI PHY, powered by VDD_MIPI_DPHY. |+| 43 | CSI_DATAP0 | bidirectional | CSI_DATAP0 is the positive data channel 0 of the MIPI CSI PHY, powered by VDD_MIPI_DPHY. |+| 44 | CSI_CLKP | bidirectional | CSI_CLKP is the positive clock channel of the MIPI CSI PHY, powered by VDD_MIPI_DPHY. |+| 45 | CSI_CLKN | bidirectional | CSI_CLKN is the negative clock channel of the MIPI CSI PHY, powered by VDD_MIPI_DPHY. |+| 46 | CSI_DATAN1 | bidirectional | CSI_DATAN1 is the negative data channel 1 of the MIPI CSI PHY, powered by VDD_MIPI_DPHY. |+| 47 | CSI_DATAP1 | bidirectional | CSI_DATAP1 is the positive data channel 1 of the MIPI CSI PHY, powered by VDD_MIPI_DPHY. |+| 48 | CSI_REXT | bidirectional | CSI_REXT is the MIPI CSI PHY pin for the 4.02 kΩ external reference resistor, powered by VDD_MIPI_DPHY. |+| 49 | USB_DM | bidirectional | USB_DM is the USB 2.0 High-Speed OTG PHY D- signal, powered by VDD_USBPHY. |+| 50 | USB_DP | bidirectional | USB_DP is the USB 2.0 High-Speed OTG PHY D+ signal, powered by VDD_USBPHY. |+| 51 | VDD_USBPHY | power_in | VDD_USBPHY is the USB PHY supply, recommended at 2.97 V to 3.63 V (typ. 3.3 V) with an absolute maximum of 3.96 V. |+| 52 | GPIO24 | bidirectional | GPIO24 is an HP IO powered from VDD_IO_4 with default drive strength 40 mA and the USB1P1_N0 analog function of the USB Full-Speed/Serial-JTAG pair. |+| 53 | GPIO25 | bidirectional | GPIO25 is an HP IO powered from VDD_IO_4 with default drive strength 40 mA, USB_PU pull-up enabled at reset, and the USB1P1_P0 analog function. |+| 54 | NC | unconnected | Pin 54 is listed as NC (no connection) in the datasheet pin table. |+| 55 | GPIO26 | bidirectional | GPIO26 is an HP IO powered from VDD_IO_4 that carries the USB1P1_N1 analog function of the second USB PHY pair, which is the default USB Full-Speed OTG pin pair. |+| 56 | GPIO27 | bidirectional | GPIO27 is an HP IO powered from VDD_IO_4 that carries the USB1P1_P1 analog function of the second USB PHY pair. |+| 57 | GPIO28 | bidirectional | GPIO28 is an HP IO powered from VDD_IO_4 that carries the SPI2_CS_PAD chip select (8-line SPI2) and the GMAC_PHY_RXDV_PAD RMII receive data valid input. |+| 58 | GPIO29 | bidirectional | GPIO29 is an HP IO powered from VDD_IO_4 that carries the SPI2_D_PAD data input and the GMAC_PHY_RXD0_PAD RMII receive data line 0. |+| 59 | VDD_PSRAM_0 | power_in | VDD_PSRAM_0 is the PSRAM IO supply, recommended at 1.65 V to 1.95 V (typ. 1.8 V). |+| 60 | GPIO30 | bidirectional | GPIO30 is an HP IO powered from VDD_IO_4 that carries the SPI2_CK_PAD clock and the GMAC_PHY_RXD1_PAD RMII receive data line 1. |+| 61 | GPIO31 | bidirectional | GPIO31 is an HP IO powered from VDD_IO_4 that carries the SPI2_Q_PAD data output and the GMAC_PHY_RXER_PAD receive error input. |+| 62 | VDD_IO_4 | power_in | VDD_IO_4 is the digital IO power supply for the HP IO group, recommended at 1.65 V to 3.6 V (typ. 3.3 V). |+| 63 | GPIO32 | bidirectional | GPIO32 is an HP IO powered from VDD_IO_4 with input enabled at reset, carrying the SPI2_HOLD_PAD signal, the GMAC_RMII_CLK_PAD RMII clock and the I3C clock/data routing option. |+| 64 | GPIO33 | bidirectional | GPIO33 is an HP IO powered from VDD_IO_4 with input enabled at reset, carrying the SPI2_WP_PAD write protect and the GMAC_PHY_TXEN_PAD transmit enable output. |+| 65 | GPIO34 | bidirectional | GPIO34 is an HP IO powered from VDD_IO_4 with input enabled at reset, carrying the SPI2_IO4_PAD signal and the GMAC_PHY_TXD0_PAD transmit data output, and is the JTAG-source strapping pin. |+| 66 | GPIO35 | bidirectional | GPIO35 is an HP IO powered from VDD_IO_4 with input enabled and weak pull-up at reset, carrying the SPI2_IO5_PAD signal and the GMAC_PHY_TXD1_PAD output, and is a chip boot-mode strapping pin. |+| 67 | VDD_PSRAM_1 | power_in | VDD_PSRAM_1 is the PSRAM IO supply, recommended at 1.65 V to 1.95 V (typ. 1.8 V). |+| 68 | GPIO36 | bidirectional | GPIO36 is an HP IO powered from VDD_IO_4 with input enabled at reset, carrying the SPI2_IO6_PAD signal and the GMAC_PHY_TXER_PAD output, and is a ROM message-printing strapping pin. |+| 69 | GPIO37 | bidirectional | GPIO37 is an HP IO powered from VDD_IO_4 that carries the UART0_TXD_PAD transmit output and the SPI2_IO7_PAD signal, and is a boot-mode strapping pin. |+| 70 | GPIO38 | bidirectional | GPIO38 is an HP IO powered from VDD_IO_4 with input enabled, carrying the UART0_RXD_PAD receive input and the SPI2_DQS_PAD data strobe, and is a boot-mode strapping pin. |+| 71 | VDDO_FLASH | power_out | VDDO_FLASH is a regulated output supply for the off-package flash, rated at 50 mA maximum. |+| 72 | VDDO_PSRAM | power_out | VDDO_PSRAM is a regulated output supply for in-package and off-package PSRAM, rated at 50 mA maximum. |+| 73 | VDDO_3 | power_out | VDDO_3 is a regulated output supply rated at 50 mA maximum. |+| 74 | VDDO_4 | power_out | VDDO_4 is a regulated output supply rated at 50 mA maximum. |+| 75 | VDD_LDO | power_in | VDD_LDO is the analog power domain supply for the internal LDOs, recommended at 3.0 V to 3.6 V (typ. 3.3 V). |+| 76 | VDD_HP_2 | power_in | VDD_HP_2 is a digital core supply, recommended at 0.99 V to 1.3 V (typ. 1.1 V). |+| 77 | VDD_DCDCC | power_in | VDD_DCDCC is the analog power supply for the DC/DC control circuit, recommended at 3.0 V to 3.6 V (typ. 3.3 V). |+| 78 | FB_DCDC | passive | FB_DCDC is the feedback pin of the external DC/DC supply, which regulates VDD_HP_0/2/3 together with external feedback resistors. |+| 79 | EN_DCDC | output | EN_DCDC is the enable output pin for the external DC/DC converter. |+| 80 | GPIO39 | bidirectional | GPIO39 is an HP IO powered from VDD_IO_5 that carries the SD1_CDATA0_PAD SDIO data line and the REF_50M_CLK_PAD 50 MHz clock output. |+| 81 | GPIO40 | bidirectional | GPIO40 is an HP IO powered from VDD_IO_5 that carries the SD1_CDATA1_PAD SDIO data line and the GMAC_PHY_TXEN_PAD transmit enable output. |+| 82 | GPIO41 | bidirectional | GPIO41 is an HP IO powered from VDD_IO_5 that carries the SD1_CDATA2_PAD SDIO data line and the GMAC_PHY_TXD0_PAD transmit data output. |+| 83 | GPIO42 | bidirectional | GPIO42 is an HP IO powered from VDD_IO_5 that carries the SD1_CDATA3_PAD SDIO data line and the GMAC_PHY_TXD1_PAD transmit data output. |+| 84 | GPIO43 | bidirectional | GPIO43 is an HP IO powered from VDD_IO_5 that carries the SD1_CCLK_PAD SDIO card clock output and the GMAC_PHY_TXER_PAD transmit error output. |+| 85 | VDD_IO_5 | power_in | VDD_IO_5 is the digital IO power supply for the HP IO group, recommended at 1.65 V to 3.6 V (typ. 3.3 V). |+| 86 | GPIO44 | bidirectional | GPIO44 is an HP IO powered from VDD_IO_5 that carries the SD1_CCMD_PAD SDIO command line and the GMAC_RMII_CLK_PAD RMII clock input. |+| 87 | GPIO45 | bidirectional | GPIO45 is an HP IO powered from VDD_IO_5 that carries the SD1_CDATA4_PAD SDIO data line and the GMAC_PHY_RXDV_PAD receive data valid input. |+| 88 | GPIO46 | bidirectional | GPIO46 is an HP IO powered from VDD_IO_5 that carries the SD1_CDATA5_PAD SDIO data line and the GMAC_PHY_RXD0_PAD receive data input. |+| 89 | GPIO47 | bidirectional | GPIO47 is an HP IO powered from VDD_IO_5 that carries the SD1_CDATA6_PAD SDIO data line and the GMAC_PHY_RXD1_PAD receive data input. |+| 90 | GPIO48 | bidirectional | GPIO48 is an HP IO powered from VDD_IO_5 that carries the SD1_CDATA7_PAD SDIO data line and the GMAC_PHY_RXER_PAD receive error input. |+| 91 | VDD_HP_3 | power_in | VDD_HP_3 is a digital core supply, recommended at 0.99 V to 1.3 V (typ. 1.1 V). |+| 92 | GPIO49 | bidirectional | GPIO49 is an HP IO powered from VDD_IO_6 that carries the ADC2_CHANNEL0 analog input and the GMAC_PHY_TXEN_PAD transmit enable output. |+| 93 | GPIO50 | bidirectional | GPIO50 is an HP IO powered from VDD_IO_6 that carries the ADC2_CHANNEL1 analog input and the GMAC_RMII_CLK_PAD RMII clock input. |+| 94 | GPIO51 | bidirectional | GPIO51 is an HP IO powered from VDD_IO_6 that carries the ADC2_CHANNEL2 and ANA_COMP0 analog functions and the GMAC_PHY_RXDV_PAD receive data valid input. |+| 95 | GPIO52 | bidirectional | GPIO52 is an HP IO powered from VDD_IO_6 that carries the ADC2_CHANNEL3 and ANA_COMP0 analog functions and the GMAC_PHY_RXD0_PAD receive data input. |+| 96 | VDD_IO_6 | power_in | VDD_IO_6 is the digital IO power supply for the HP IO group, recommended at 1.65 V to 3.6 V (typ. 3.3 V). |+| 97 | GPIO53 | bidirectional | GPIO53 is an HP IO powered from VDD_IO_6 that carries the ADC2_CHANNEL4 and ANA_COMP1 analog functions and the GMAC_PHY_RXD1_PAD receive data input. |+| 98 | GPIO54 | bidirectional | GPIO54 is an HP IO powered from VDD_IO_6 that carries the ADC2_CHANNEL5 and ANA_COMP1 analog functions and the GMAC_PHY_RXER_PAD receive error input. |+| 99 | XTAL_N | passive | XTAL_N is the negative side of the differential clock connection to the chip's crystal or oscillator. |+| 100 | XTAL_P | passive | XTAL_P is the positive side of the differential clock connection to the chip's crystal or oscillator. |+| 101 | VDD_ANA | power_in | VDD_ANA is the analog power domain supply, recommended at 3.0 V to 3.6 V (typ. 3.3 V). |+| 102 | VDD_BAT | power_in | VDD_BAT is the analog power domain supply that can optionally connect to an external battery, recommended at 2.5 V to 3.6 V (typ. 3.3 V). |+| 103 | CHIP_PU | input | CHIP_PU is the chip enable input: high enables the chip and low powers it down, and it must not be left floating. |+| 104 | GPIO0 | bidirectional | GPIO0 is an LP IO powered from VDD_LP/VDD_BAT that carries the XTAL_32K_N analog function and LP_GPIO0. |+| 105 | GND | power_in | GND is the external ground connection pin. |  ## Key specifications @@ -129,6 +129,14 @@ Limits as printed in the datasheet (page.json `metadata.characteristics` carries  | Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page | |---|---|---|---|---|---|---|---|+| Allowed input voltage (VDD_LDO, VDD_DCDCC, VDD_ANA, VDD_BAT, VDD_LP) |  | -0.3 |  | 3.6 | V |  | 79 |+| Allowed input voltage (VDD_IO_0, VDD_FLASHIO, VDD_IO_4, VDD_IO_5, VDD_IO_6) |  | -0.3 |  | 3.6 | V |  | 79 |+| Allowed input voltage (VDD_PSRAM_0, VDD_PSRAM_1) |  | 1.62 |  | 1.98 | V |  | 79 |+| Allowed input voltage (VDD_HP_0, VDD_HP_2, VDD_HP_3) |  | 0 |  | 1.3 | V |  | 79 |+| Allowed input voltage (VDD_MIPI_DPHY) |  | 0 |  | 2.75 | V |  | 79 |+| Allowed input voltage (VDD_USBPHY) |  | -0.66 |  | 3.96 | V |  | 79 |+| Cumulative IO output current | Ioutput |  |  | 1500 | mA |  | 79 |+| Storage temperature | TSTORE | -40 |  | 150 | °C |  | 79 | | Recommended input voltage (VDD_LDO, VDD_DCDCC, VDD_ANA, VDD_LP) |  | 3 | 3.3 | 3.6 | V |  | 79 | | Recommended input voltage (VDD_BAT) |  | 2.5 | 3.3 | 3.6 | V |  | 79 | | Recommended input voltage (VDD_IO_0, VDD_FLASHIO, VDD_IO_4, VDD_IO_5, VDD_IO_6) |  | 1.65 | 3.3 | 3.6 | V |  | 79 |@@ -138,36 +146,40 @@ Limits as printed in the datasheet (page.json `metadata.characteristics` carries | Recommended input voltage (VDD_USBPHY) |  | 2.97 | 3.3 | 3.63 | V |  | 79 | | Current supplied to core | IVDD | 0.5 |  |  | A |  | 79 | | Ambient temperature | TA | -40 |  | 85 | °C |  | 79 |-| Allowed input voltage (VDD_LDO, VDD_DCDCC, VDD_ANA, VDD_BAT, VDD_LP) |  | -0.3 |  | 3.6 | V |  | 79 |-| Allowed input voltage (VDD_IO_0, VDD_FLASHIO, VDD_IO_4, VDD_IO_5, VDD_IO_6) |  | -0.3 |  | 3.6 | V |  | 79 |-| Allowed input voltage (VDD_PSRAM_0, VDD_PSRAM_1) |  | 1.62 |  | 1.98 | V |  | 79 |-| Allowed input voltage (VDD_HP_0, VDD_HP_2, VDD_HP_3) |  | 0 |  | 1.3 | V |  | 79 |-| Allowed input voltage (VDD_MIPI_DPHY) |  | 0 |  | 2.75 | V |  | 79 |-| Allowed input voltage (VDD_USBPHY) |  | -0.66 |  | 3.96 | V |  | 79 |-| Cumulative IO output current | Ioutput |  |  | 1500 | mA |  | 79 |-| Storage temperature | TSTORE | -40 |  | 150 | °C |  | 79 |+| Low-level input voltage | VIL | -0.3 |  |  | V |  | 80 | | High-level input current | IIH |  |  | 50 | nA |  | 80 | | Low-level input current | IIL |  |  | 50 | nA |  | 80 |-| Differential nonlinearity | DNL | -1 |  | 3 | LSB |  | 81 |-| Integral nonlinearity | INL | -5 |  | 3 | LSB |  | 81 |+| Chip reset voltage (low level) | VIL_nRST | -0.3 |  |  | V | Chip reset voltage (CHIP_PU voltage is within the specified range) | 80 |+| Pin capacitance | CIN |  | 2 |  | pF |  | 80 |+| High-level source current | IOH |  | 40 |  | mA | VDD = 3.3 V, VOH >= 2.64 V, PAD_DRIVER = 3 | 80 |+| Low-level sink current | IOL |  | 28 |  | mA | VDD = 3.3 V, VOL = 0.495 V, PAD_DRIVER = 3 | 80 |+| Internal weak pull-up resistor | RPU |  | 45 |  | kΩ |  | 80 |+| Internal weak pull-down resistor | RPD |  | 45 |  | kΩ |  | 80 |+| Differential nonlinearity (DNL) | DNL | -1 |  | 3 | LSB |  | 81 |+| Integral nonlinearity (INL) | INL | -5 |  | 3 | LSB |  | 81 | | Sampling rate |  |  |  | 100 | kSPS |  | 81 |-| Total error |  | -12 |  | 12 | mV | ATTEN0, effective measurement range of 0-1000 | 81 |-| Total error |  | -15 |  | 15 | mV | ATTEN3, effective measurement range of 0-3300 | 81 |-| Power supply voltage (1.8 V PSRAM) | VCC | 1.62 | 1.8 | 1.98 | V |  | 82 |-| Power supply voltage (3.3 V PSRAM) | VCC | 2.7 | 3.3 | 3.6 | V |  | 82 |+| Total error (ATTEN0) |  | -12 |  | 12 | mV | ATTEN0, effective measurement range of 0-1000 | 81 |+| Total error (ATTEN1) |  | -12 |  | 12 | mV | ATTEN1, effective measurement range of 0-1300 | 81 |+| Total error (ATTEN2) |  | -12 |  | 12 | mV | ATTEN2, effective measurement range of 0-1900 | 81 |+| Total error (ATTEN3) |  | -15 |  | 15 | mV | ATTEN3, effective measurement range of 0-3300 | 81 |+| Power supply voltage (1.8 V) | VCC | 1.62 | 1.8 | 1.98 | V |  | 82 |+| Power supply voltage (3.3 V) | VCC | 2.7 | 3.3 | 3.6 | V |  | 82 | | Maximum clock frequency | FC | 80 |  |  | MHz |  | 82 |+| VDDO_FLASH powered by VDD_LDO via RVFB for 3.3 V flash | RVFB |  | 3 |  | Ω |  | 80 |+| Output current when VDDO_FLASH is powered by Flash Voltage Regulator for 1.8 V flash | IVFB |  | 50 |  | mA |  | 80 |  ## CAD (KiCad official)  - Symbol: `ESP32-P4NRW32` - Footprint: `PCM_Espressif:ESP32-P4` - 3D model: QFN-104(10x10), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.85 mm nominal QFN height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)+- 3D model files: `esp32-p4nrw32-etched.step` / `esp32-p4nrw32-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `esp32-p4nrw32.step` / `esp32-p4nrw32.glb` are the bare package body.  ## Provenance  Data extracted from the manufacturer datasheet, not a distributor listing: -- **Datasheet:** [ESPRESSIF datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-p4-chip-revision-v1.3_datasheet_en.pdf) (94 pp, sha256 `52ef629ec92510a6`, retrieved 2026-10-27, tier: manufacturer)+- **Datasheet:** [ESPRESSIF datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-p4-chip-revision-v1.3_datasheet_en.pdf) (94 pp, sha256 `52ef629ec92510a6`, retrieved 2026-10-28, tier: manufacturer) - **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - **CAD:** KiCad official libraries (CC-BY-SA 4.0). 

@@ -1,6 +1,6 @@ {   "slug": "esp32-p4nrw32",-  "version": "0.1.1",+  "version": "0.1.2",   "type": "component",   "description": "ESPRESSIF Functional Modules, QFN-104(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",   "tags": [@@ -28,7 +28,8 @@     "viewers/symbol.html",     "viewers/footprint.html",     "esp32-p4nrw32-hero.glb",-    "esp32-p4nrw32-hero.overlay.json"+    "esp32-p4nrw32-hero.overlay.json",+    "esp32-p4nrw32-etched.glb"   ],   "component": {     "mpn": "ESP32-P4NRW32",@@ -42,15 +43,16 @@       "symbol": "esp32-p4nrw32.kicad_sym",       "footprint": "esp32-p4nrw32.kicad_mod",       "model_3d": "esp32-p4nrw32-hero.glb",-      "model_3d_step": "esp32-p4nrw32.step",-      "lbr": "esp32-p4nrw32.lbr",-      "model_3d_plain": "esp32-p4nrw32.glb"+      "model_3d_plain": "esp32-p4nrw32-etched.glb",+      "model_3d_step": "esp32-p4nrw32-etched.step",+      "model_3d_step_plain": "esp32-p4nrw32.step",+      "lbr": "esp32-p4nrw32.lbr"     },     "distributor_links": {       "lcsc": "C22387510"     },     "distributor_check": {-      "checked_at": "2026-10-27T22:22:52Z",+      "checked_at": "2026-10-28T19:13:05Z",       "source": "Component Ocean /api/assign-pns",       "digikey": {         "pn": null,@@ -66,631 +68,631 @@         "number": "1",         "name": "GPIO1",         "type": "bidirectional",-        "description": "GPIO1 is powered by VDD_LP or VDD_BAT and also offers LP IO MUX and XTAL_32K_P analog functions."+        "description": "GPIO1 is a general-purpose IO powered from VDD_LP/VDD_BAT that also carries the XTAL_32K_P analog function and LP_GPIO1 in Deep-sleep mode, with default drive strength 20 mA."       },       {         "number": "2",         "name": "GPIO2",         "type": "bidirectional",-        "description": "GPIO2 is powered by VDD_LP or VDD_BAT, has input enable and weak pull-up enabled at reset, and offers MTCK and touch channel 1."+        "description": "GPIO2 is an LP IO powered from VDD_LP/VDD_BAT that carries the MTCK JTAG clock, TOUCH_CHANNEL1 and LP_GPIO2, and is input-enabled with weak pull-up at reset (EFUSE_DIS_PAD_JTAG dependent)."       },       {         "number": "3",         "name": "GPIO3",         "type": "bidirectional",-        "description": "GPIO3 is powered by VDD_LP or VDD_BAT, has input enable at reset, and offers MTDI and touch channel 2."+        "description": "GPIO3 is an LP IO powered from VDD_LP/VDD_BAT that carries the MTDI JTAG input, TOUCH_CHANNEL2 and LP_GPIO3, and is input-enabled at reset."       },       {         "number": "4",         "name": "GPIO4",         "type": "bidirectional",-        "description": "GPIO4 is powered by VDD_LP, has input enable at reset, and offers MTMS and touch channel 3."+        "description": "GPIO4 is an LP IO powered from VDD_LP that carries the MTMS JTAG input, TOUCH_CHANNEL3 and LP_GPIO4, and is input-enabled at reset."       },       {         "number": "5",         "name": "GPIO5",         "type": "bidirectional",-        "description": "GPIO5 is powered by VDD_LP and offers the MTDO JTAG output and touch channel 4."+        "description": "GPIO5 is an LP IO powered from VDD_LP that carries the MTDO JTAG output (tri-state capable), TOUCH_CHANNEL4 and LP_GPIO5."       },       {         "number": "6",         "name": "GPIO6",         "type": "bidirectional",-        "description": "GPIO6 is powered by VDD_LP and offers SPI2_HOLD and touch channel 5."+        "description": "GPIO6 is an LP IO powered from VDD_LP that carries the SPI2_HOLD_PAD (8-line/4-line SPI2 interface), TOUCH_CHANNEL5 and LP_GPIO6."       },       {         "number": "7",         "name": "GPIO7",         "type": "bidirectional",-        "description": "GPIO7 is powered by VDD_LP and offers SPI2_CS and touch channel 6."+        "description": "GPIO7 is an LP IO powered from VDD_LP that carries the SPI2_CS_PAD chip select, TOUCH_CHANNEL6 and LP_GPIO7."       },       {         "number": "8",         "name": "GPIO8",         "type": "bidirectional",-        "description": "GPIO8 is powered by VDD_LP and offers SPI2_D and touch channel 7."+        "description": "GPIO8 is an LP IO powered from VDD_LP that carries the SPI2_D_PAD data input, TOUCH_CHANNEL7 and LP_GPIO8."       },       {         "number": "9",         "name": "VDD_LP",         "type": "power_in",-        "description": "LP power domain supply input, recommended 3.0 to 3.6 V (3.3 V typ) per Table 5-2."+        "description": "VDD_LP is the LP power domain supply, recommended at 3.0 V to 3.6 V (typ. 3.3 V)."       },       {         "number": "10",         "name": "GPIO9",         "type": "bidirectional",-        "description": "GPIO9 is powered by VDD_LP and offers SPI2_CK and touch channel 8."+        "description": "GPIO9 is an LP IO powered from VDD_LP that carries the SPI2_CK_PAD clock, TOUCH_CHANNEL8 and LP_GPIO9."       },       {         "number": "11",         "name": "GPIO10",         "type": "bidirectional",-        "description": "GPIO10 is powered by VDD_LP and offers SPI2_Q and touch channel 9."+        "description": "GPIO10 is an LP IO powered from VDD_LP that carries the SPI2_Q_PAD data output, TOUCH_CHANNEL9 and LP_GPIO10."       },       {         "number": "12",         "name": "GPIO11",         "type": "bidirectional",-        "description": "GPIO11 is powered by VDD_LP and offers SPI2_WP and touch channel 10."+        "description": "GPIO11 is an LP IO powered from VDD_LP that carries the SPI2_WP_PAD write protect, TOUCH_CHANNEL10 and LP_GPIO11."       },       {         "number": "13",         "name": "GPIO12",         "type": "bidirectional",-        "description": "GPIO12 is powered by VDD_LP and offers touch channel 11."+        "description": "GPIO12 is an LP IO powered from VDD_LP that carries TOUCH_CHANNEL11 and LP_GPIO12."       },       {         "number": "14",         "name": "GPIO13",         "type": "bidirectional",-        "description": "GPIO13 is powered by VDD_LP and offers touch channel 12."+        "description": "GPIO13 is an LP IO powered from VDD_LP that carries TOUCH_CHANNEL12 and LP_GPIO13."       },       {         "number": "15",         "name": "GPIO14",         "type": "bidirectional",-        "description": "GPIO14 is powered by VDD_LP and offers LP_UART_TXD and touch channel 13."+        "description": "GPIO14 is an LP IO powered from VDD_LP that carries the LP_UART_TXD_PAD transmit output, TOUCH_CHANNEL13 and LP_GPIO14."       },       {         "number": "16",         "name": "GPIO15",         "type": "bidirectional",-        "description": "GPIO15 is powered by VDD_LP and offers LP_UART_RXD and touch channel 14."+        "description": "GPIO15 is an LP IO powered from VDD_LP that carries the LP_UART_RXD_PAD receive input, TOUCH_CHANNEL14 and LP_GPIO15."       },       {         "number": "17",         "name": "GPIO16",         "type": "bidirectional",-        "description": "GPIO16 is powered by VDD_IO_0 and offers ADC1_CHANNEL0 as an analog function."+        "description": "GPIO16 is an HP IO powered from VDD_IO_0 (1.65 V to 3.6 V) that carries the ADC1_CHANNEL0 analog input."       },       {         "number": "18",         "name": "GPIO17",         "type": "bidirectional",-        "description": "GPIO17 is powered by VDD_IO_0 and offers ADC1_CHANNEL1 as an analog function."+        "description": "GPIO17 is an HP IO powered from VDD_IO_0 (1.65 V to 3.6 V) that carries the ADC1_CHANNEL1 analog input."       },       {         "number": "19",         "name": "GPIO18",         "type": "bidirectional",-        "description": "GPIO18 is powered by VDD_IO_0 and offers ADC1_CHANNEL2 as an analog function."+        "description": "GPIO18 is an HP IO powered from VDD_IO_0 (1.65 V to 3.6 V) that carries the ADC1_CHANNEL2 analog input."       },       {         "number": "20",         "name": "GPIO19",         "type": "bidirectional",-        "description": "GPIO19 is powered by VDD_IO_0 and offers ADC1_CHANNEL3 as an analog function."+        "description": "GPIO19 is an HP IO powered from VDD_IO_0 (1.65 V to 3.6 V) that carries the ADC1_CHANNEL3 analog input."       },       {         "number": "21",         "name": "VDD_IO_0",         "type": "power_in",-        "description": "Digital HP IO supply for GPIO16 to GPIO23, recommended 1.65 to 3.6 V (3.3 V typ) per Table 5-2."+        "description": "VDD_IO_0 is the digital IO power supply for the HP IO group, recommended at 1.65 V to 3.6 V (typ. 3.3 V)."       },       {         "number": "22",         "name": "GPIO20",         "type": "bidirectional",-        "description": "GPIO20 is powered by VDD_IO_0 and offers ADC1_CHANNEL4 as an analog function."+        "description": "GPIO20 is an HP IO powered from VDD_IO_0 (1.65 V to 3.6 V) that carries the ADC1_CHANNEL4 analog input."       },       {         "number": "23",         "name": "GPIO21",         "type": "bidirectional",-        "description": "GPIO21 is powered by VDD_IO_0 and offers ADC1_CHANNEL5 as an analog function."+        "description": "GPIO21 is an HP IO powered from VDD_IO_0 (1.65 V to 3.6 V) that carries the ADC1_CHANNEL5 analog input."       },       {         "number": "24",         "name": "GPIO22",         "type": "bidirectional",-        "description": "GPIO22 is powered by VDD_IO_0 and offers ADC1_CHANNEL6 as an analog function."+        "description": "GPIO22 is an HP IO powered from VDD_IO_0 (1.65 V to 3.6 V) that carries the ADC1_CHANNEL6 analog input."       },       {         "number": "25",         "name": "GPIO23",         "type": "bidirectional",-        "description": "GPIO23 is powered by VDD_IO_0 and offers ADC1_CHANNEL7 and the REF_50M_CLK output."+        "description": "GPIO23 is an HP IO powered from VDD_IO_0 (1.65 V to 3.6 V) that carries the ADC1_CHANNEL7 analog input and the REF_50M_CLK_PAD 50 MHz reference clock output."       },       {         "number": "26",         "name": "VDD_HP_0",         "type": "power_in",-        "description": "HP digital core supply, recommended 0.99 to 1.3 V (1.1 V typ) per Table 5-2."+        "description": "VDD_HP_0 is the digital core supply, recommended at 0.99 V to 1.3 V (typ. 1.1 V); the chip can adjust it automatically."       },       {         "number": "27",         "name": "FLASH_CS",         "type": "output",-        "description": "Dedicated chip-select output to the off-package flash, powered by VDD_FLASHIO."+        "description": "FLASH_CS is the dedicated off-package flash chip-select output, powered by VDD_FLASHIO."       },       {         "number": "28",         "name": "FLASH_Q",         "type": "bidirectional",-        "description": "Dedicated flash data output line (DO) for off-package flash, powered by VDD_FLASHIO."+        "description": "FLASH_Q is the dedicated flash data-output line (DO) powered by VDD_FLASHIO."       },       {         "number": "29",         "name": "FLASH_WP",         "type": "bidirectional",-        "description": "Dedicated flash write-protect line (WP#) for off-package flash, powered by VDD_FLASHIO."+        "description": "FLASH_WP is the dedicated flash write-protect line (WP#) powered by VDD_FLASHIO."       },       {         "number": "30",         "name": "VDD_FLASHIO",         "type": "power_in",-        "description": "Power supply for flash IO, which should be adjusted to the flash model (3.3 V flash used as the example)."+        "description": "VDD_FLASHIO powers the flash IO and should be set according to the flash model; the datasheet uses 3.3 V flash as the example, with recommended input 1.65 V to 3.6 V."       },       {         "number": "31",         "name": "FLASH_HOLD",         "type": "bidirectional",-        "description": "Dedicated flash HOLD# line for off-package flash, powered by VDD_FLASHIO."+        "description": "FLASH_HOLD is the dedicated flash hold line (HOLD#) powered by VDD_FLASHIO."       },       {         "number": "32",         "name": "FLASH_CK",         "type": "output",-        "description": "Dedicated flash clock output for off-package flash, powered by VDD_FLASHIO."+        "description": "FLASH_CK is the dedicated flash clock output (CLK) powered by VDD_FLASHIO."       },       {         "number": "33",         "name": "FLASH_D",         "type": "bidirectional",-        "description": "Dedicated flash data input line (DI) for off-package flash, powered by VDD_FLASHIO."+        "description": "FLASH_D is the dedicated flash data-input line (DI) powered by VDD_FLASHIO."       },       {         "number": "34",         "name": "DSI_REXT",         "type": "bidirectional",-        "description": "Connects the external 4.02 kΩ reference resistor for the MIPI DSI PHY."+        "description": "DSI_REXT is the MIPI DSI PHY pin for the 4.02 kΩ external reference resistor, powered by VDD_MIPI_DPHY."       },       {         "number": "35",         "name": "DSI_DATAP1",         "type": "bidirectional",-        "description": "MIPI DSI PHY positive data channel 1, powered by VDD_MIPI_DPHY."+        "description": "DSI_DATAP1 is the positive data channel 1 of the MIPI DSI PHY (2-lane, 1.5 Gbps per lane), powered by VDD_MIPI_DPHY."       },       {         "number": "36",         "name": "DSI_DATAN1",         "type": "bidirectional",-        "description": "MIPI DSI PHY negative data channel 1, powered by VDD_MIPI_DPHY."+        "description": "DSI_DATAN1 is the negative data channel 1 of the MIPI DSI PHY, powered by VDD_MIPI_DPHY."       },       {         "number": "37",         "name": "DSI_CLKN",         "type": "bidirectional",-        "description": "MIPI DSI PHY negative clock channel, powered by VDD_MIPI_DPHY."+        "description": "DSI_CLKN is the negative clock channel of the MIPI DSI PHY, powered by VDD_MIPI_DPHY."       },       {         "number": "38",         "name": "DSI_CLKP",         "type": "bidirectional",-        "description": "MIPI DSI PHY positive clock channel, powered by VDD_MIPI_DPHY."+        "description": "DSI_CLKP is the positive clock channel of the MIPI DSI PHY, powered by VDD_MIPI_DPHY."       },       {         "number": "39",         "name": "DSI_DATAP0",         "type": "bidirectional",-        "description": "MIPI DSI PHY positive data channel 0, powered by VDD_MIPI_DPHY."+        "description": "DSI_DATAP0 is the positive data channel 0 of the MIPI DSI PHY, powered by VDD_MIPI_DPHY."       },       {         "number": "40",         "name": "DSI_DATAN0",         "type": "bidirectional",-        "description": "MIPI DSI PHY negative data channel 0, powered by VDD_MIPI_DPHY."+        "description": "DSI_DATAN0 is the negative data channel 0 of the MIPI DSI PHY, powered by VDD_MIPI_DPHY."       },       {         "number": "41",         "name": "VDD_MIPI_DPHY",         "type": "power_in",-        "description": "MIPI PHY supply, recommended 2.25 to 2.75 V (2.5 V typ) per Table 5-2."+        "description": "VDD_MIPI_DPHY is the MIPI PHY supply, recommended at 2.25 V to 2.75 V (typ. 2.5 V) with an absolute maximum of 2.75 V."       },       {         "number": "42",         "name": "CSI_DATAN0",         "type": "bidirectional",-        "description": "MIPI CSI PHY negative data channel 0, powered by VDD_MIPI_DPHY."+        "description": "CSI_DATAN0 is the negative data channel 0 of the MIPI CSI PHY, powered by VDD_MIPI_DPHY."       },       {         "number": "43",         "name": "CSI_DATAP0",         "type": "bidirectional",-        "description": "MIPI CSI PHY positive data channel 0, powered by VDD_MIPI_DPHY."+        "description": "CSI_DATAP0 is the positive data channel 0 of the MIPI CSI PHY, powered by VDD_MIPI_DPHY."       },       {         "number": "44",         "name": "CSI_CLKP",         "type": "bidirectional",-        "description": "MIPI CSI PHY positive clock channel, powered by VDD_MIPI_DPHY."+        "description": "CSI_CLKP is the positive clock channel of the MIPI CSI PHY, powered by VDD_MIPI_DPHY."       },       {         "number": "45",         "name": "CSI_CLKN",         "type": "bidirectional",-        "description": "MIPI CSI PHY negative clock channel, powered by VDD_MIPI_DPHY."+        "description": "CSI_CLKN is the negative clock channel of the MIPI CSI PHY, powered by VDD_MIPI_DPHY."       },       {         "number": "46",         "name": "CSI_DATAN1",         "type": "bidirectional",-        "description": "MIPI CSI PHY negative data channel 1, powered by VDD_MIPI_DPHY."+        "description": "CSI_DATAN1 is the negative data channel 1 of the MIPI CSI PHY, powered by VDD_MIPI_DPHY."       },       {         "number": "47",         "name": "CSI_DATAP1",         "type": "bidirectional",-        "description": "MIPI CSI PHY positive data channel 1, powered by VDD_MIPI_DPHY."+        "description": "CSI_DATAP1 is the positive data channel 1 of the MIPI CSI PHY, powered by VDD_MIPI_DPHY."       },       {         "number": "48",         "name": "CSI_REXT",         "type": "bidirectional",-        "description": "Connects the external 4.02 kΩ reference resistor for the MIPI CSI PHY."+        "description": "CSI_REXT is the MIPI CSI PHY pin for the 4.02 kΩ external reference resistor, powered by VDD_MIPI_DPHY."       },       {         "number": "49",         "name": "USB_DM",         "type": "bidirectional",-        "description": "USB 2.0 OTG high-speed PHY D- signal, powered by VDD_USBPHY (2.97 to 3.63 V)."+        "description": "USB_DM is the USB 2.0 High-Speed OTG PHY D- signal, powered by VDD_USBPHY."       },       {         "number": "50",         "name": "USB_DP",         "type": "bidirectional",-        "description": "USB 2.0 OTG high-speed PHY D+ signal, powered by VDD_USBPHY (2.97 to 3.63 V)."+        "description": "USB_DP is the USB 2.0 High-Speed OTG PHY D+ signal, powered by VDD_USBPHY."       },       {         "number": "51",         "name": "VDD_USBPHY",         "type": "power_in",-        "description": "USB PHY supply, recommended 2.97 to 3.63 V (3.3 V typ) per Table 5-2."+        "description": "VDD_USBPHY is the USB PHY supply, recommended at 2.97 V to 3.63 V (typ. 3.3 V) with an absolute maximum of 3.96 V."       },       {         "number": "52",         "name": "GPIO24",         "type": "bidirectional",-        "description": "GPIO24 is powered by VDD_IO_4 with a default drive strength of 40 mA and offers USB1P1_N0."+        "description": "GPIO24 is an HP IO powered from VDD_IO_4 with default drive strength 40 mA and the USB1P1_N0 analog function of the USB Full-Speed/Serial-JTAG pair."       },       {         "number": "53",         "name": "GPIO25",         "type": "bidirectional",-        "description": "GPIO25 is powered by VDD_IO_4 with a default drive strength of 40 mA, USB pull-up enabled at reset, and offers USB1P1_P0."+        "description": "GPIO25 is an HP IO powered from VDD_IO_4 with default drive strength 40 mA, USB_PU pull-up enabled at reset, and the USB1P1_P0 analog function."       },       {         "number": "54",         "name": "NC",         "type": "unconnected",-        "description": "Pin is not connected (NC) in the package."+        "description": "Pin 54 is listed as NC (no connection) in the datasheet pin table."       },       {         "number": "55",         "name": "GPIO26",         "type": "bidirectional",-        "description": "GPIO26 is powered by VDD_IO_4 with a default drive strength of 20 mA and offers USB1P1_N1."+        "description": "GPIO26 is an HP IO powered from VDD_IO_4 that carries the USB1P1_N1 analog function of the second USB PHY pair, which is the default USB Full-Speed OTG pin pair."       },       {         "number": "56",         "name": "GPIO27",         "type": "bidirectional",-        "description": "GPIO27 is powered by VDD_IO_4 with a default drive strength of 20 mA and offers USB1P1_P1."+        "description": "GPIO27 is an HP IO powered from VDD_IO_4 that carries the USB1P1_P1 analog function of the second USB PHY pair."       },       {         "number": "57",         "name": "GPIO28",         "type": "bidirectional",-        "description": "GPIO28 is powered by VDD_IO_4 and offers SPI2_CS and the GMAC_PHY_RXDV input."+        "description": "GPIO28 is an HP IO powered from VDD_IO_4 that carries the SPI2_CS_PAD chip select (8-line SPI2) and the GMAC_PHY_RXDV_PAD RMII receive data valid input."       },       {         "number": "58",         "name": "GPIO29",         "type": "bidirectional",-        "description": "GPIO29 is powered by VDD_IO_4 and offers SPI2_D and the GMAC_PHY_RXD0 input."+        "description": "GPIO29 is an HP IO powered from VDD_IO_4 that carries the SPI2_D_PAD data input and the GMAC_PHY_RXD0_PAD RMII receive data line 0."       },       {         "number": "59",         "name": "VDD_PSRAM_0",         "type": "power_in",-        "description": "In-package PSRAM supply, recommended 1.65 to 1.95 V (1.8 V typ) per Table 5-2."+        "description": "VDD_PSRAM_0 is the PSRAM IO supply, recommended at 1.65 V to 1.95 V (typ. 1.8 V)."       },       {         "number": "60",         "name": "GPIO30",         "type": "bidirectional",-        "description": "GPIO30 is powered by VDD_IO_4 and offers SPI2_CK and the GMAC_PHY_RXD1 input."+        "description": "GPIO30 is an HP IO powered from VDD_IO_4 that carries the SPI2_CK_PAD clock and the GMAC_PHY_RXD1_PAD RMII receive data line 1."       },       {         "number": "61",         "name": "GPIO31",         "type": "bidirectional",-        "description": "GPIO31 is powered by VDD_IO_4 and offers SPI2_Q and the GMAC_PHY_RXER input."+        "description": "GPIO31 is an HP IO powered from VDD_IO_4 that carries the SPI2_Q_PAD data output and the GMAC_PHY_RXER_PAD receive error input."       },       {         "number": "62",         "name": "VDD_IO_4",         "type": "power_in",-        "description": "Digital HP IO supply for GPIO24 to GPIO38, recommended 1.65 to 3.6 V (3.3 V typ) per Table 5-2."+        "description": "VDD_IO_4 is the digital IO power supply for the HP IO group, recommended at 1.65 V to 3.6 V (typ. 3.3 V)."       },       {         "number": "63",         "name": "GPIO32",         "type": "bidirectional",-        "description": "GPIO32 is powered by VDD_IO_4, has input enable at reset, and offers SPI2_HOLD and the GMAC_RMII_CLK input."+        "description": "GPIO32 is an HP IO powered from VDD_IO_4 with input enabled at reset, carrying the SPI2_HOLD_PAD signal, the GMAC_RMII_CLK_PAD RMII clock and the I3C clock/data routing option."       },       {         "number": "64",         "name": "GPIO33",         "type": "bidirectional",-        "description": "GPIO33 is powered by VDD_IO_4, has input enable at reset, and offers SPI2_WP and the GMAC_PHY_TXEN output."+        "description": "GPIO33 is an HP IO powered from VDD_IO_4 with input enabled at reset, carrying the SPI2_WP_PAD write protect and the GMAC_PHY_TXEN_PAD transmit enable output."       },       {         "number": "65",         "name": "GPIO34",         "type": "bidirectional",-        "description": "GPIO34 is powered by VDD_IO_4 with input enable at reset, and is the strapping pin for the JTAG signal source control."+        "description": "GPIO34 is an HP IO powered from VDD_IO_4 with input enabled at reset, carrying the SPI2_IO4_PAD signal and the GMAC_PHY_TXD0_PAD transmit data output, and is the JTAG-source strapping pin."       },       {         "number": "66",         "name": "GPIO35",         "type": "bidirectional",-        "description": "GPIO35 is powered by VDD_IO_4 with input enable and weak pull-up at reset, and is the default-high strapping pin for boot mode control."+        "description": "GPIO35 is an HP IO powered from VDD_IO_4 with input enabled and weak pull-up at reset, carrying the SPI2_IO5_PAD signal and the GMAC_PHY_TXD1_PAD output, and is a chip boot-mode strapping pin."       },       {         "number": "67",         "name": "VDD_PSRAM_1",         "type": "power_in",-        "description": "In-package PSRAM supply, recommended 1.65 to 1.95 V (1.8 V typ) per Table 5-2."+        "description": "VDD_PSRAM_1 is the PSRAM IO supply, recommended at 1.65 V to 1.95 V (typ. 1.8 V)."       },       {         "number": "68",         "name": "GPIO36",         "type": "bidirectional",-        "description": "GPIO36 is powered by VDD_IO_4 with input enable at reset, and is the strapping pin for ROM message printing control."+        "description": "GPIO36 is an HP IO powered from VDD_IO_4 with input enabled at reset, carrying the SPI2_IO6_PAD signal and the GMAC_PHY_TXER_PAD output, and is a ROM message-printing strapping pin."       },       {         "number": "69",         "name": "GPIO37",         "type": "bidirectional",-        "description": "GPIO37 is powered by VDD_IO_4 with input enable at reset, a boot mode strapping pin, and offers the UART0_TXD output."+        "description": "GPIO37 is an HP IO powered from VDD_IO_4 that carries the UART0_TXD_PAD transmit output and the SPI2_IO7_PAD signal, and is a boot-mode strapping pin."       },       {         "number": "70",         "name": "GPIO38",         "type": "bidirectional",-        "description": "GPIO38 is powered by VDD_IO_4 with input enable at reset, a boot mode strapping pin, and offers the UART0_RXD input."+        "description": "GPIO38 is an HP IO powered from VDD_IO_4 with input enabled, carrying the UART0_RXD_PAD receive input and the SPI2_DQS_PAD data strobe, and is a boot-mode strapping pin."       },       {         "number": "71",         "name": "VDDO_FLASH",         "type": "power_out",-        "description": "Flash power output, 3.3 V by default or 1.8 V after EFUSE_0PXA_TIEH_SEL_0 is burnt, supplying up to 50 mA."+        "description": "VDDO_FLASH is a regulated output supply for the off-package flash, rated at 50 mA maximum."       },       {         "number": "72",         "name": "VDDO_PSRAM",         "type": "power_out",-        "description": "Output rail for in-package and off-package PSRAM, supplying up to 50 mA."+        "description": "VDDO_PSRAM is a regulated output supply for in-package and off-package PSRAM, rated at 50 mA maximum."       },       {         "number": "73",         "name": "VDDO_3",         "type": "power_out",-        "description": "VO3 LDO output rail for external devices, configurable 0.5 to 2.7 V or 3.3 V, supplying up to 50 mA."+        "description": "VDDO_3 is a regulated output supply rated at 50 mA maximum."       },       {         "number": "74",         "name": "VDDO_4",         "type": "power_out",-        "description": "VO4 LDO output rail for external devices, configurable 0.5 to 2.7 V or 3.3 V, supplying up to 50 mA."+        "description": "VDDO_4 is a regulated output supply rated at 50 mA maximum."       },       {         "number": "75",         "name": "VDD_LDO",         "type": "power_in",-        "description": "Analog power domain input that provides power for the LDOs, recommended 3.0 to 3.6 V."+        "description": "VDD_LDO is the analog power domain supply for the internal LDOs, recommended at 3.0 V to 3.6 V (typ. 3.3 V)."       },       {         "number": "76",         "name": "VDD_HP_2",         "type": "power_in",-        "description": "HP digital core supply, recommended 0.99 to 1.3 V (1.1 V typ) per Table 5-2."+        "description": "VDD_HP_2 is a digital core supply, recommended at 0.99 V to 1.3 V (typ. 1.1 V)."       },       {         "number": "77",         "name": "VDD_DCDCC",         "type": "power_in",-        "description": "Analog power domain input for DC/DC control, recommended 3.0 to 3.6 V."+        "description": "VDD_DCDCC is the analog power supply for the DC/DC control circuit, recommended at 3.0 V to 3.6 V (typ. 3.3 V)."       },       {         "number": "78",         "name": "FB_DCDC",         "type": "passive",-        "description": "Feedback pin of the external DC/DC supply, which regulates VDD_HP_0/2/3 together with feedback resistors."+        "description": "FB_DCDC is the feedback pin of the external DC/DC supply, which regulates VDD_HP_0/2/3 together with external feedback resistors."       },       {         "number": "79",         "name": "EN_DCDC",         "type": "output",-        "description": "Enable output for the external DC/DC converter."+        "description": "EN_DCDC is the enable output pin for the external DC/DC converter."       },       {         "number": "80",         "name": "GPIO39",         "type": "bidirectional",-        "description": "GPIO39 is powered by VDD_IO_5 and offers SD1_CDATA0 and the REF_50M_CLK output."+        "description": "GPIO39 is an HP IO powered from VDD_IO_5 that carries the SD1_CDATA0_PAD SDIO data line and the REF_50M_CLK_PAD 50 MHz clock output."       },       {         "number": "81",         "name": "GPIO40",         "type": "bidirectional",-        "description": "GPIO40 is powered by VDD_IO_5 and offers SD1_CDATA1 and the GMAC_PHY_TXEN output."+        "description": "GPIO40 is an HP IO powered from VDD_IO_5 that carries the SD1_CDATA1_PAD SDIO data line and the GMAC_PHY_TXEN_PAD transmit enable output."       },       {         "number": "82",         "name": "GPIO41",         "type": "bidirectional",-        "description": "GPIO41 is powered by VDD_IO_5 and offers SD1_CDATA2 and the GMAC_PHY_TXD0 output."+        "description": "GPIO41 is an HP IO powered from VDD_IO_5 that carries the SD1_CDATA2_PAD SDIO data line and the GMAC_PHY_TXD0_PAD transmit data output."       },       {         "number": "83",         "name": "GPIO42",         "type": "bidirectional",-        "description": "GPIO42 is powered by VDD_IO_5 and offers SD1_CDATA3 and the GMAC_PHY_TXD1 output."+        "description": "GPIO42 is an HP IO powered from VDD_IO_5 that carries the SD1_CDATA3_PAD SDIO data line and the GMAC_PHY_TXD1_PAD transmit data output."       },       {         "number": "84",         "name": "GPIO43",         "type": "bidirectional",-        "description": "GPIO43 is powered by VDD_IO_5 and offers the SD1_CCLK output and the GMAC_PHY_TXER output."+        "description": "GPIO43 is an HP IO powered from VDD_IO_5 that carries the SD1_CCLK_PAD SDIO card clock output and the GMAC_PHY_TXER_PAD transmit error output."       },       {         "number": "85",         "name": "VDD_IO_5",         "type": "power_in",-        "description": "Digital HP IO supply for GPIO39 to GPIO48, recommended 1.65 to 3.6 V (3.3 V typ) per Table 5-2."+        "description": "VDD_IO_5 is the digital IO power supply for the HP IO group, recommended at 1.65 V to 3.6 V (typ. 3.3 V)."       },       {         "number": "86",         "name": "GPIO44",         "type": "bidirectional",-        "description": "GPIO44 is powered by VDD_IO_5 and offers SD1_CCMD and the GMAC_RMII_CLK input."+        "description": "GPIO44 is an HP IO powered from VDD_IO_5 that carries the SD1_CCMD_PAD SDIO command line and the GMAC_RMII_CLK_PAD RMII clock input."       },       {         "number": "87",         "name": "GPIO45",         "type": "bidirectional",-        "description": "GPIO45 is powered by VDD_IO_5 and offers SD1_CDATA4 and the GMAC_PHY_RXDV input."+        "description": "GPIO45 is an HP IO powered from VDD_IO_5 that carries the SD1_CDATA4_PAD SDIO data line and the GMAC_PHY_RXDV_PAD receive data valid input."       },       {         "number": "88",         "name": "GPIO46",         "type": "bidirectional",-        "description": "GPIO46 is powered by VDD_IO_5 and offers SD1_CDATA5 and the GMAC_PHY_RXD0 input."+        "description": "GPIO46 is an HP IO powered from VDD_IO_5 that carries the SD1_CDATA5_PAD SDIO data line and the GMAC_PHY_RXD0_PAD receive data input."       },       {         "number": "89",         "name": "GPIO47",         "type": "bidirectional",-        "description": "GPIO47 is powered by VDD_IO_5 and offers SD1_CDATA6 and the GMAC_PHY_RXD1 input."+        "description": "GPIO47 is an HP IO powered from VDD_IO_5 that carries the SD1_CDATA6_PAD SDIO data line and the GMAC_PHY_RXD1_PAD receive data input."       },       {         "number": "90",         "name": "GPIO48",         "type": "bidirectional",-        "description": "GPIO48 is powered by VDD_IO_5 and offers SD1_CDATA7 and the GMAC_PHY_RXER input."+        "description": "GPIO48 is an HP IO powered from VDD_IO_5 that carries the SD1_CDATA7_PAD SDIO data line and the GMAC_PHY_RXER_PAD receive error input."       },       {         "number": "91",         "name": "VDD_HP_3",         "type": "power_in",-        "description": "HP digital core supply, recommended 0.99 to 1.3 V (1.1 V typ) per Table 5-2."+        "description": "VDD_HP_3 is a digital core supply, recommended at 0.99 V to 1.3 V (typ. 1.1 V)."       },       {         "number": "92",         "name": "GPIO49",         "type": "bidirectional",-        "description": "GPIO49 is powered by VDD_IO_6, offers ADC2_CHANNEL0, and offers the GMAC_PHY_TXEN output."+        "description": "GPIO49 is an HP IO powered from VDD_IO_6 that carries the ADC2_CHANNEL0 analog input and the GMAC_PHY_TXEN_PAD transmit enable output."       },       {         "number": "93",         "name": "GPIO50",         "type": "bidirectional",-        "description": "GPIO50 is powered by VDD_IO_6, offers ADC2_CHANNEL1, and offers the GMAC_RMII_CLK input."+        "description": "GPIO50 is an HP IO powered from VDD_IO_6 that carries the ADC2_CHANNEL1 analog input and the GMAC_RMII_CLK_PAD RMII clock input."       },       {         "number": "94",         "name": "GPIO51",         "type": "bidirectional",-        "description": "GPIO51 is powered by VDD_IO_6, offers ADC2_CHANNEL2, and offers ANA_COMP0."+        "description": "GPIO51 is an HP IO powered from VDD_IO_6 that carries the ADC2_CHANNEL2 and ANA_COMP0 analog functions and the GMAC_PHY_RXDV_PAD receive data valid input."       },       {         "number": "95",         "name": "GPIO52",         "type": "bidirectional",-        "description": "GPIO52 is powered by VDD_IO_6, offers ADC2_CHANNEL3, and offers ANA_COMP0."+        "description": "GPIO52 is an HP IO powered from VDD_IO_6 that carries the ADC2_CHANNEL3 and ANA_COMP0 analog functions and the GMAC_PHY_RXD0_PAD receive data input."       },       {         "number": "96",         "name": "VDD_IO_6",         "type": "power_in",-        "description": "Digital HP IO supply for GPIO49 to GPIO54, recommended 1.65 to 3.6 V (3.3 V typ) per Table 5-2."+        "description": "VDD_IO_6 is the digital IO power supply for the HP IO group, recommended at 1.65 V to 3.6 V (typ. 3.3 V)."       },       {         "number": "97",         "name": "GPIO53",         "type": "bidirectional",-        "description": "GPIO53 is powered by VDD_IO_6, offers ADC2_CHANNEL4, and offers ANA_COMP1."+        "description": "GPIO53 is an HP IO powered from VDD_IO_6 that carries the ADC2_CHANNEL4 and ANA_COMP1 analog functions and the GMAC_PHY_RXD1_PAD receive data input."       },       {         "number": "98",         "name": "GPIO54",         "type": "bidirectional",-        "description": "GPIO54 is powered by VDD_IO_6, offers ADC2_CHANNEL5, and offers ANA_COMP1."+        "description": "GPIO54 is an HP IO powered from VDD_IO_6 that carries the ADC2_CHANNEL5 and ANA_COMP1 analog functions and the GMAC_PHY_RXER_PAD receive error input."       },       {         "number": "99",         "name": "XTAL_N",         "type": "passive",-        "description": "Negative side of the external clock input/output connected to the chip crystal or oscillator (40 MHz XTAL_CLK)."+        "description": "XTAL_N is the negative side of the differential clock connection to the chip's crystal or oscillator."       },       {         "number": "100",         "name": "XTAL_P",         "type": "passive",-        "description": "Positive side of the external clock input/output connected to the chip crystal or oscillator (40 MHz XTAL_CLK)."+        "description": "XTAL_P is the positive side of the differential clock connection to the chip's crystal or oscillator."       },       {         "number": "101",         "name": "VDD_ANA",         "type": "power_in",-        "description": "Analog power domain supply, recommended 3.0 to 3.6 V."+        "description": "VDD_ANA is the analog power domain supply, recommended at 3.0 V to 3.6 V (typ. 3.3 V)."       },       {         "number": "102",         "name": "VDD_BAT",         "type": "power_in",-        "description": "Analog power domain input that can optionally connect to an external battery, recommended 2.5 to 3.6 V."+        "description": "VDD_BAT is the analog power domain supply that can optionally connect to an external battery, recommended at 2.5 V to 3.6 V (typ. 3.3 V)."       },       {         "number": "103",         "name": "CHIP_PU",         "type": "input",-        "description": "Chip enable: high powers up and enables the chip, low powers it down, and it must not be left floating."+        "description": "CHIP_PU is the chip enable input: high enables the chip and low powers it down, and it must not be left floating."       },       {         "number": "104",         "name": "GPIO0",         "type": "bidirectional",-        "description": "GPIO0 is powered by VDD_LP or VDD_BAT and also offers LP_GPIO0 and XTAL_32K_N analog function."+        "description": "GPIO0 is an LP IO powered from VDD_LP/VDD_BAT that carries the XTAL_32K_N analog function and LP_GPIO0."       },       {         "number": "105",         "name": "GND",         "type": "power_in",-        "description": "External ground connection."+        "description": "GND is the external ground connection pin."       }     ],     "provenance": {@@ -704,11 +706,12 @@         "consensus": "agreed",         "guards": "pin_guards 0.1: passed",         "guard_notes": [-          "extractor flagged: The MPN ESP32-P4NRW32 is marked End of Life in this datasheet (upgraded to ESP32-P4NRW32X). The pino; Table 2-11 lists VDD_FLASHIO2 with a footnote, while Table 2-1 and Figure 2-1 name the pin VDD_FLASH; Pin 54 is printed as NC and pin 105 is GND, which is the package ground pad. Pin 105 is typed power_"+          "extractor flagged: The datasheet marks ESP32-P4NRW32 as End of life (EOL), upgraded to ESP32-P4NRW32X, and refers to th; The datasheet pin table (Table 2-1 and Appendix A) lists the QFN104 package for this series. The pac; Pin 30 is named VDD_FLASHIO in Table 2-1 and Figure 2-1, but Table 2-11 writes VDD_FLASHIO2 with a f",+          "9/105 pins cited to the wrong page (name found elsewhere): ['9:VDD_LP@p79', '21:VDD_IO_0@p79', '30:VDD_FLASHIO@p79', '41:VDD_MIPI_DPHY@p79']"         ],-        "pages_sent": 94,-        "cost_usd": 0.2826,-        "at": "2026-10-27T22:22:15"+        "pages_sent": 53,+        "cost_usd": 0.2825,+        "at": "2026-10-28T19:12:25"       },       "datasheet": {         "url": "https://www.espressif.com/sites/default/files/documentation/esp32-p4-chip-revision-v1.3_datasheet_en.pdf",@@ -744,8 +747,27 @@         "zmin_mm": 0.0,         "centre_offset_mm": 0.0,         "footprint_binding": "none",-        "sha256": "4768606132501b6e08a104c25fd4482e49df118ce235014d13dd1b2ecba470ee",-        "checked": "2026-10-27",+        "sha256": "457ab6b63d8e996dbb736b913bc7e8e932306d4c484c72ca3c2c8c8418cd18a8",+        "checked": "2026-10-28",+        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+      },+      {+        "file": "esp32-p4nrw32-etched.step",+        "role": "eda",+        "up": "Z",+        "units": "mm",+        "origin": "footprint origin = pad-pattern centre",+        "seat": "z = 0",+        "extents_mm": [+          10.02,+          10.02,+          0.85+        ],+        "zmin_mm": 0.0,+        "centre_offset_mm": 0.0,+        "footprint_binding": "none",+        "sha256": "4c84a2b1fdb66dfa038957de4bc65ed976e3e63b5fd37b1524e854a4d58def9a",+        "checked": "2026-10-28",         "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"       }     ]

@@ -4,7 +4,7 @@   "slug": "esp32-p4nrw32",   "title": "ESP32-P4NRW32",   "brief": "ESPRESSIF Functional Modules, QFN-104(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",-  "version": "0.1.0",+  "version": "0.1.2",   "license": "CC-BY-SA-4.0",   "tags": [     "component",@@ -25,15 +25,16 @@       "symbol": "esp32-p4nrw32.kicad_sym",       "footprint": "esp32-p4nrw32.kicad_mod",       "model_3d": "esp32-p4nrw32-hero.glb",-      "model_3d_step": "esp32-p4nrw32.step",-      "lbr": "esp32-p4nrw32.lbr",-      "model_3d_plain": "esp32-p4nrw32.glb"+      "model_3d_plain": "esp32-p4nrw32-etched.glb",+      "model_3d_step": "esp32-p4nrw32-etched.step",+      "model_3d_step_plain": "esp32-p4nrw32.step",+      "lbr": "esp32-p4nrw32.lbr"     },     "distributor_links": {       "lcsc": "C22387510"     },     "distributor_check": {-      "checked_at": "2026-10-27T22:22:52Z",+      "checked_at": "2026-10-28T19:13:05Z",       "source": "Component Ocean /api/assign-pns",       "digikey": {         "pn": null,@@ -49,631 +50,631 @@         "number": "1",         "name": "GPIO1",         "type": "bidirectional",-        "description": "GPIO1 is powered by VDD_LP or VDD_BAT and also offers LP IO MUX and XTAL_32K_P analog functions."+        "description": "GPIO1 is a general-purpose IO powered from VDD_LP/VDD_BAT that also carries the XTAL_32K_P analog function and LP_GPIO1 in Deep-sleep mode, with default drive strength 20 mA."       },       {         "number": "2",         "name": "GPIO2",         "type": "bidirectional",-        "description": "GPIO2 is powered by VDD_LP or VDD_BAT, has input enable and weak pull-up enabled at reset, and offers MTCK and touch channel 1."+        "description": "GPIO2 is an LP IO powered from VDD_LP/VDD_BAT that carries the MTCK JTAG clock, TOUCH_CHANNEL1 and LP_GPIO2, and is input-enabled with weak pull-up at reset (EFUSE_DIS_PAD_JTAG dependent)."       },       {         "number": "3",         "name": "GPIO3",         "type": "bidirectional",-        "description": "GPIO3 is powered by VDD_LP or VDD_BAT, has input enable at reset, and offers MTDI and touch channel 2."+        "description": "GPIO3 is an LP IO powered from VDD_LP/VDD_BAT that carries the MTDI JTAG input, TOUCH_CHANNEL2 and LP_GPIO3, and is input-enabled at reset."       },       {         "number": "4",         "name": "GPIO4",         "type": "bidirectional",-        "description": "GPIO4 is powered by VDD_LP, has input enable at reset, and offers MTMS and touch channel 3."+        "description": "GPIO4 is an LP IO powered from VDD_LP that carries the MTMS JTAG input, TOUCH_CHANNEL3 and LP_GPIO4, and is input-enabled at reset."       },       {         "number": "5",         "name": "GPIO5",         "type": "bidirectional",-        "description": "GPIO5 is powered by VDD_LP and offers the MTDO JTAG output and touch channel 4."+        "description": "GPIO5 is an LP IO powered from VDD_LP that carries the MTDO JTAG output (tri-state capable), TOUCH_CHANNEL4 and LP_GPIO5."       },       {         "number": "6",         "name": "GPIO6",         "type": "bidirectional",-        "description": "GPIO6 is powered by VDD_LP and offers SPI2_HOLD and touch channel 5."+        "description": "GPIO6 is an LP IO powered from VDD_LP that carries the SPI2_HOLD_PAD (8-line/4-line SPI2 interface), TOUCH_CHANNEL5 and LP_GPIO6."       },       {         "number": "7",         "name": "GPIO7",         "type": "bidirectional",-        "description": "GPIO7 is powered by VDD_LP and offers SPI2_CS and touch channel 6."+        "description": "GPIO7 is an LP IO powered from VDD_LP that carries the SPI2_CS_PAD chip select, TOUCH_CHANNEL6 and LP_GPIO7."       },       {         "number": "8",         "name": "GPIO8",         "type": "bidirectional",-        "description": "GPIO8 is powered by VDD_LP and offers SPI2_D and touch channel 7."+        "description": "GPIO8 is an LP IO powered from VDD_LP that carries the SPI2_D_PAD data input, TOUCH_CHANNEL7 and LP_GPIO8."       },       {         "number": "9",         "name": "VDD_LP",         "type": "power_in",-        "description": "LP power domain supply input, recommended 3.0 to 3.6 V (3.3 V typ) per Table 5-2."+        "description": "VDD_LP is the LP power domain supply, recommended at 3.0 V to 3.6 V (typ. 3.3 V)."       },       {         "number": "10",         "name": "GPIO9",         "type": "bidirectional",-        "description": "GPIO9 is powered by VDD_LP and offers SPI2_CK and touch channel 8."+        "description": "GPIO9 is an LP IO powered from VDD_LP that carries the SPI2_CK_PAD clock, TOUCH_CHANNEL8 and LP_GPIO9."       },       {         "number": "11",         "name": "GPIO10",         "type": "bidirectional",-        "description": "GPIO10 is powered by VDD_LP and offers SPI2_Q and touch channel 9."+        "description": "GPIO10 is an LP IO powered from VDD_LP that carries the SPI2_Q_PAD data output, TOUCH_CHANNEL9 and LP_GPIO10."       },       {         "number": "12",         "name": "GPIO11",         "type": "bidirectional",-        "description": "GPIO11 is powered by VDD_LP and offers SPI2_WP and touch channel 10."+        "description": "GPIO11 is an LP IO powered from VDD_LP that carries the SPI2_WP_PAD write protect, TOUCH_CHANNEL10 and LP_GPIO11."       },       {         "number": "13",         "name": "GPIO12",         "type": "bidirectional",-        "description": "GPIO12 is powered by VDD_LP and offers touch channel 11."+        "description": "GPIO12 is an LP IO powered from VDD_LP that carries TOUCH_CHANNEL11 and LP_GPIO12."       },       {         "number": "14",         "name": "GPIO13",         "type": "bidirectional",-        "description": "GPIO13 is powered by VDD_LP and offers touch channel 12."+        "description": "GPIO13 is an LP IO powered from VDD_LP that carries TOUCH_CHANNEL12 and LP_GPIO13."       },       {         "number": "15",         "name": "GPIO14",         "type": "bidirectional",-        "description": "GPIO14 is powered by VDD_LP and offers LP_UART_TXD and touch channel 13."+        "description": "GPIO14 is an LP IO powered from VDD_LP that carries the LP_UART_TXD_PAD transmit output, TOUCH_CHANNEL13 and LP_GPIO14."       },       {         "number": "16",         "name": "GPIO15",         "type": "bidirectional",-        "description": "GPIO15 is powered by VDD_LP and offers LP_UART_RXD and touch channel 14."+        "description": "GPIO15 is an LP IO powered from VDD_LP that carries the LP_UART_RXD_PAD receive input, TOUCH_CHANNEL14 and LP_GPIO15."       },       {         "number": "17",         "name": "GPIO16",         "type": "bidirectional",-        "description": "GPIO16 is powered by VDD_IO_0 and offers ADC1_CHANNEL0 as an analog function."+        "description": "GPIO16 is an HP IO powered from VDD_IO_0 (1.65 V to 3.6 V) that carries the ADC1_CHANNEL0 analog input."       },       {         "number": "18",         "name": "GPIO17",         "type": "bidirectional",-        "description": "GPIO17 is powered by VDD_IO_0 and offers ADC1_CHANNEL1 as an analog function."+        "description": "GPIO17 is an HP IO powered from VDD_IO_0 (1.65 V to 3.6 V) that carries the ADC1_CHANNEL1 analog input."       },       {         "number": "19",         "name": "GPIO18",         "type": "bidirectional",-        "description": "GPIO18 is powered by VDD_IO_0 and offers ADC1_CHANNEL2 as an analog function."+        "description": "GPIO18 is an HP IO powered from VDD_IO_0 (1.65 V to 3.6 V) that carries the ADC1_CHANNEL2 analog input."       },       {         "number": "20",         "name": "GPIO19",         "type": "bidirectional",-        "description": "GPIO19 is powered by VDD_IO_0 and offers ADC1_CHANNEL3 as an analog function."+        "description": "GPIO19 is an HP IO powered from VDD_IO_0 (1.65 V to 3.6 V) that carries the ADC1_CHANNEL3 analog input."       },       {         "number": "21",         "name": "VDD_IO_0",         "type": "power_in",-        "description": "Digital HP IO supply for GPIO16 to GPIO23, recommended 1.65 to 3.6 V (3.3 V typ) per Table 5-2."+        "description": "VDD_IO_0 is the digital IO power supply for the HP IO group, recommended at 1.65 V to 3.6 V (typ. 3.3 V)."       },       {         "number": "22",         "name": "GPIO20",         "type": "bidirectional",-        "description": "GPIO20 is powered by VDD_IO_0 and offers ADC1_CHANNEL4 as an analog function."+        "description": "GPIO20 is an HP IO powered from VDD_IO_0 (1.65 V to 3.6 V) that carries the ADC1_CHANNEL4 analog input."       },       {         "number": "23",         "name": "GPIO21",         "type": "bidirectional",-        "description": "GPIO21 is powered by VDD_IO_0 and offers ADC1_CHANNEL5 as an analog function."+        "description": "GPIO21 is an HP IO powered from VDD_IO_0 (1.65 V to 3.6 V) that carries the ADC1_CHANNEL5 analog input."       },       {         "number": "24",         "name": "GPIO22",         "type": "bidirectional",-        "description": "GPIO22 is powered by VDD_IO_0 and offers ADC1_CHANNEL6 as an analog function."+        "description": "GPIO22 is an HP IO powered from VDD_IO_0 (1.65 V to 3.6 V) that carries the ADC1_CHANNEL6 analog input."       },       {         "number": "25",         "name": "GPIO23",         "type": "bidirectional",-        "description": "GPIO23 is powered by VDD_IO_0 and offers ADC1_CHANNEL7 and the REF_50M_CLK output."+        "description": "GPIO23 is an HP IO powered from VDD_IO_0 (1.65 V to 3.6 V) that carries the ADC1_CHANNEL7 analog input and the REF_50M_CLK_PAD 50 MHz reference clock output."       },       {         "number": "26",         "name": "VDD_HP_0",         "type": "power_in",-        "description": "HP digital core supply, recommended 0.99 to 1.3 V (1.1 V typ) per Table 5-2."+        "description": "VDD_HP_0 is the digital core supply, recommended at 0.99 V to 1.3 V (typ. 1.1 V); the chip can adjust it automatically."       },       {         "number": "27",         "name": "FLASH_CS",         "type": "output",-        "description": "Dedicated chip-select output to the off-package flash, powered by VDD_FLASHIO."+        "description": "FLASH_CS is the dedicated off-package flash chip-select output, powered by VDD_FLASHIO."       },       {         "number": "28",         "name": "FLASH_Q",         "type": "bidirectional",-        "description": "Dedicated flash data output line (DO) for off-package flash, powered by VDD_FLASHIO."+        "description": "FLASH_Q is the dedicated flash data-output line (DO) powered by VDD_FLASHIO."       },       {         "number": "29",         "name": "FLASH_WP",         "type": "bidirectional",-        "description": "Dedicated flash write-protect line (WP#) for off-package flash, powered by VDD_FLASHIO."+        "description": "FLASH_WP is the dedicated flash write-protect line (WP#) powered by VDD_FLASHIO."       },       {         "number": "30",         "name": "VDD_FLASHIO",         "type": "power_in",-        "description": "Power supply for flash IO, which should be adjusted to the flash model (3.3 V flash used as the example)."+        "description": "VDD_FLASHIO powers the flash IO and should be set according to the flash model; the datasheet uses 3.3 V flash as the example, with recommended input 1.65 V to 3.6 V."       },       {         "number": "31",         "name": "FLASH_HOLD",         "type": "bidirectional",-        "description": "Dedicated flash HOLD# line for off-package flash, powered by VDD_FLASHIO."+        "description": "FLASH_HOLD is the dedicated flash hold line (HOLD#) powered by VDD_FLASHIO."       },       {         "number": "32",         "name": "FLASH_CK",         "type": "output",-        "description": "Dedicated flash clock output for off-package flash, powered by VDD_FLASHIO."+        "description": "FLASH_CK is the dedicated flash clock output (CLK) powered by VDD_FLASHIO."       },       {         "number": "33",         "name": "FLASH_D",         "type": "bidirectional",-        "description": "Dedicated flash data input line (DI) for off-package flash, powered by VDD_FLASHIO."+        "description": "FLASH_D is the dedicated flash data-input line (DI) powered by VDD_FLASHIO."       },       {         "number": "34",         "name": "DSI_REXT",         "type": "bidirectional",-        "description": "Connects the external 4.02 kΩ reference resistor for the MIPI DSI PHY."+        "description": "DSI_REXT is the MIPI DSI PHY pin for the 4.02 kΩ external reference resistor, powered by VDD_MIPI_DPHY."       },       {         "number": "35",         "name": "DSI_DATAP1",         "type": "bidirectional",-        "description": "MIPI DSI PHY positive data channel 1, powered by VDD_MIPI_DPHY."+        "description": "DSI_DATAP1 is the positive data channel 1 of the MIPI DSI PHY (2-lane, 1.5 Gbps per lane), powered by VDD_MIPI_DPHY."       },       {         "number": "36",         "name": "DSI_DATAN1",         "type": "bidirectional",-        "description": "MIPI DSI PHY negative data channel 1, powered by VDD_MIPI_DPHY."+        "description": "DSI_DATAN1 is the negative data channel 1 of the MIPI DSI PHY, powered by VDD_MIPI_DPHY."       },       {         "number": "37",         "name": "DSI_CLKN",         "type": "bidirectional",-        "description": "MIPI DSI PHY negative clock channel, powered by VDD_MIPI_DPHY."+        "description": "DSI_CLKN is the negative clock channel of the MIPI DSI PHY, powered by VDD_MIPI_DPHY."       },       {         "number": "38",         "name": "DSI_CLKP",         "type": "bidirectional",-        "description": "MIPI DSI PHY positive clock channel, powered by VDD_MIPI_DPHY."+        "description": "DSI_CLKP is the positive clock channel of the MIPI DSI PHY, powered by VDD_MIPI_DPHY."       },       {         "number": "39",         "name": "DSI_DATAP0",         "type": "bidirectional",-        "description": "MIPI DSI PHY positive data channel 0, powered by VDD_MIPI_DPHY."+        "description": "DSI_DATAP0 is the positive data channel 0 of the MIPI DSI PHY, powered by VDD_MIPI_DPHY."       },       {         "number": "40",         "name": "DSI_DATAN0",         "type": "bidirectional",-        "description": "MIPI DSI PHY negative data channel 0, powered by VDD_MIPI_DPHY."+        "description": "DSI_DATAN0 is the negative data channel 0 of the MIPI DSI PHY, powered by VDD_MIPI_DPHY."       },       {         "number": "41",         "name": "VDD_MIPI_DPHY",         "type": "power_in",-        "description": "MIPI PHY supply, recommended 2.25 to 2.75 V (2.5 V typ) per Table 5-2."+        "description": "VDD_MIPI_DPHY is the MIPI PHY supply, recommended at 2.25 V to 2.75 V (typ. 2.5 V) with an absolute maximum of 2.75 V."       },       {         "number": "42",         "name": "CSI_DATAN0",         "type": "bidirectional",-        "description": "MIPI CSI PHY negative data channel 0, powered by VDD_MIPI_DPHY."+        "description": "CSI_DATAN0 is the negative data channel 0 of the MIPI CSI PHY, powered by VDD_MIPI_DPHY."       },       {         "number": "43",         "name": "CSI_DATAP0",         "type": "bidirectional",-        "description": "MIPI CSI PHY positive data channel 0, powered by VDD_MIPI_DPHY."+        "description": "CSI_DATAP0 is the positive data channel 0 of the MIPI CSI PHY, powered by VDD_MIPI_DPHY."       },       {         "number": "44",         "name": "CSI_CLKP",         "type": "bidirectional",-        "description": "MIPI CSI PHY positive clock channel, powered by VDD_MIPI_DPHY."+        "description": "CSI_CLKP is the positive clock channel of the MIPI CSI PHY, powered by VDD_MIPI_DPHY."       },       {         "number": "45",         "name": "CSI_CLKN",         "type": "bidirectional",-        "description": "MIPI CSI PHY negative clock channel, powered by VDD_MIPI_DPHY."+        "description": "CSI_CLKN is the negative clock channel of the MIPI CSI PHY, powered by VDD_MIPI_DPHY."       },       {         "number": "46",         "name": "CSI_DATAN1",         "type": "bidirectional",-        "description": "MIPI CSI PHY negative data channel 1, powered by VDD_MIPI_DPHY."+        "description": "CSI_DATAN1 is the negative data channel 1 of the MIPI CSI PHY, powered by VDD_MIPI_DPHY."       },       {         "number": "47",         "name": "CSI_DATAP1",         "type": "bidirectional",-        "description": "MIPI CSI PHY positive data channel 1, powered by VDD_MIPI_DPHY."+        "description": "CSI_DATAP1 is the positive data channel 1 of the MIPI CSI PHY, powered by VDD_MIPI_DPHY."       },       {         "number": "48",         "name": "CSI_REXT",         "type": "bidirectional",-        "description": "Connects the external 4.02 kΩ reference resistor for the MIPI CSI PHY."+        "description": "CSI_REXT is the MIPI CSI PHY pin for the 4.02 kΩ external reference resistor, powered by VDD_MIPI_DPHY."       },       {         "number": "49",         "name": "USB_DM",         "type": "bidirectional",-        "description": "USB 2.0 OTG high-speed PHY D- signal, powered by VDD_USBPHY (2.97 to 3.63 V)."+        "description": "USB_DM is the USB 2.0 High-Speed OTG PHY D- signal, powered by VDD_USBPHY."       },       {         "number": "50",         "name": "USB_DP",         "type": "bidirectional",-        "description": "USB 2.0 OTG high-speed PHY D+ signal, powered by VDD_USBPHY (2.97 to 3.63 V)."+        "description": "USB_DP is the USB 2.0 High-Speed OTG PHY D+ signal, powered by VDD_USBPHY."       },       {         "number": "51",         "name": "VDD_USBPHY",         "type": "power_in",-        "description": "USB PHY supply, recommended 2.97 to 3.63 V (3.3 V typ) per Table 5-2."+        "description": "VDD_USBPHY is the USB PHY supply, recommended at 2.97 V to 3.63 V (typ. 3.3 V) with an absolute maximum of 3.96 V."       },       {         "number": "52",         "name": "GPIO24",         "type": "bidirectional",-        "description": "GPIO24 is powered by VDD_IO_4 with a default drive strength of 40 mA and offers USB1P1_N0."+        "description": "GPIO24 is an HP IO powered from VDD_IO_4 with default drive strength 40 mA and the USB1P1_N0 analog function of the USB Full-Speed/Serial-JTAG pair."       },       {         "number": "53",         "name": "GPIO25",         "type": "bidirectional",-        "description": "GPIO25 is powered by VDD_IO_4 with a default drive strength of 40 mA, USB pull-up enabled at reset, and offers USB1P1_P0."+        "description": "GPIO25 is an HP IO powered from VDD_IO_4 with default drive strength 40 mA, USB_PU pull-up enabled at reset, and the USB1P1_P0 analog function."       },       {         "number": "54",         "name": "NC",         "type": "unconnected",-        "description": "Pin is not connected (NC) in the package."+        "description": "Pin 54 is listed as NC (no connection) in the datasheet pin table."       },       {         "number": "55",         "name": "GPIO26",         "type": "bidirectional",-        "description": "GPIO26 is powered by VDD_IO_4 with a default drive strength of 20 mA and offers USB1P1_N1."+        "description": "GPIO26 is an HP IO powered from VDD_IO_4 that carries the USB1P1_N1 analog function of the second USB PHY pair, which is the default USB Full-Speed OTG pin pair."       },       {         "number": "56",         "name": "GPIO27",         "type": "bidirectional",-        "description": "GPIO27 is powered by VDD_IO_4 with a default drive strength of 20 mA and offers USB1P1_P1."+        "description": "GPIO27 is an HP IO powered from VDD_IO_4 that carries the USB1P1_P1 analog function of the second USB PHY pair."       },       {         "number": "57",         "name": "GPIO28",         "type": "bidirectional",-        "description": "GPIO28 is powered by VDD_IO_4 and offers SPI2_CS and the GMAC_PHY_RXDV input."+        "description": "GPIO28 is an HP IO powered from VDD_IO_4 that carries the SPI2_CS_PAD chip select (8-line SPI2) and the GMAC_PHY_RXDV_PAD RMII receive data valid input."       },       {         "number": "58",         "name": "GPIO29",         "type": "bidirectional",-        "description": "GPIO29 is powered by VDD_IO_4 and offers SPI2_D and the GMAC_PHY_RXD0 input."+        "description": "GPIO29 is an HP IO powered from VDD_IO_4 that carries the SPI2_D_PAD data input and the GMAC_PHY_RXD0_PAD RMII receive data line 0."       },       {         "number": "59",         "name": "VDD_PSRAM_0",         "type": "power_in",-        "description": "In-package PSRAM supply, recommended 1.65 to 1.95 V (1.8 V typ) per Table 5-2."+        "description": "VDD_PSRAM_0 is the PSRAM IO supply, recommended at 1.65 V to 1.95 V (typ. 1.8 V)."       },       {         "number": "60",         "name": "GPIO30",         "type": "bidirectional",-        "description": "GPIO30 is powered by VDD_IO_4 and offers SPI2_CK and the GMAC_PHY_RXD1 input."+        "description": "GPIO30 is an HP IO powered from VDD_IO_4 that carries the SPI2_CK_PAD clock and the GMAC_PHY_RXD1_PAD RMII receive data line 1."       },       {         "number": "61",         "name": "GPIO31",         "type": "bidirectional",-        "description": "GPIO31 is powered by VDD_IO_4 and offers SPI2_Q and the GMAC_PHY_RXER input."+        "description": "GPIO31 is an HP IO powered from VDD_IO_4 that carries the SPI2_Q_PAD data output and the GMAC_PHY_RXER_PAD receive error input."       },       {         "number": "62",         "name": "VDD_IO_4",         "type": "power_in",-        "description": "Digital HP IO supply for GPIO24 to GPIO38, recommended 1.65 to 3.6 V (3.3 V typ) per Table 5-2."+        "description": "VDD_IO_4 is the digital IO power supply for the HP IO group, recommended at 1.65 V to 3.6 V (typ. 3.3 V)."       },       {         "number": "63",         "name": "GPIO32",         "type": "bidirectional",-        "description": "GPIO32 is powered by VDD_IO_4, has input enable at reset, and offers SPI2_HOLD and the GMAC_RMII_CLK input."+        "description": "GPIO32 is an HP IO powered from VDD_IO_4 with input enabled at reset, carrying the SPI2_HOLD_PAD signal, the GMAC_RMII_CLK_PAD RMII clock and the I3C clock/data routing option."       },       {         "number": "64",         "name": "GPIO33",         "type": "bidirectional",-        "description": "GPIO33 is powered by VDD_IO_4, has input enable at reset, and offers SPI2_WP and the GMAC_PHY_TXEN output."+        "description": "GPIO33 is an HP IO powered from VDD_IO_4 with input enabled at reset, carrying the SPI2_WP_PAD write protect and the GMAC_PHY_TXEN_PAD transmit enable output."       },       {         "number": "65",         "name": "GPIO34",         "type": "bidirectional",-        "description": "GPIO34 is powered by VDD_IO_4 with input enable at reset, and is the strapping pin for the JTAG signal source control."+        "description": "GPIO34 is an HP IO powered from VDD_IO_4 with input enabled at reset, carrying the SPI2_IO4_PAD signal and the GMAC_PHY_TXD0_PAD transmit data output, and is the JTAG-source strapping pin."       },       {         "number": "66",         "name": "GPIO35",         "type": "bidirectional",-        "description": "GPIO35 is powered by VDD_IO_4 with input enable and weak pull-up at reset, and is the default-high strapping pin for boot mode control."+        "description": "GPIO35 is an HP IO powered from VDD_IO_4 with input enabled and weak pull-up at reset, carrying the SPI2_IO5_PAD signal and the GMAC_PHY_TXD1_PAD output, and is a chip boot-mode strapping pin."       },       {         "number": "67",         "name": "VDD_PSRAM_1",         "type": "power_in",-        "description": "In-package PSRAM supply, recommended 1.65 to 1.95 V (1.8 V typ) per Table 5-2."+        "description": "VDD_PSRAM_1 is the PSRAM IO supply, recommended at 1.65 V to 1.95 V (typ. 1.8 V)."       },       {         "number": "68",         "name": "GPIO36",         "type": "bidirectional",-        "description": "GPIO36 is powered by VDD_IO_4 with input enable at reset, and is the strapping pin for ROM message printing control."+        "description": "GPIO36 is an HP IO powered from VDD_IO_4 with input enabled at reset, carrying the SPI2_IO6_PAD signal and the GMAC_PHY_TXER_PAD output, and is a ROM message-printing strapping pin."       },       {         "number": "69",         "name": "GPIO37",         "type": "bidirectional",-        "description": "GPIO37 is powered by VDD_IO_4 with input enable at reset, a boot mode strapping pin, and offers the UART0_TXD output."+        "description": "GPIO37 is an HP IO powered from VDD_IO_4 that carries the UART0_TXD_PAD transmit output and the SPI2_IO7_PAD signal, and is a boot-mode strapping pin."       },       {         "number": "70",         "name": "GPIO38",         "type": "bidirectional",-        "description": "GPIO38 is powered by VDD_IO_4 with input enable at reset, a boot mode strapping pin, and offers the UART0_RXD input."+        "description": "GPIO38 is an HP IO powered from VDD_IO_4 with input enabled, carrying the UART0_RXD_PAD receive input and the SPI2_DQS_PAD data strobe, and is a boot-mode strapping pin."       },       {         "number": "71",         "name": "VDDO_FLASH",         "type": "power_out",-        "description": "Flash power output, 3.3 V by default or 1.8 V after EFUSE_0PXA_TIEH_SEL_0 is burnt, supplying up to 50 mA."+        "description": "VDDO_FLASH is a regulated output supply for the off-package flash, rated at 50 mA maximum."       },       {         "number": "72",         "name": "VDDO_PSRAM",         "type": "power_out",-        "description": "Output rail for in-package and off-package PSRAM, supplying up to 50 mA."+        "description": "VDDO_PSRAM is a regulated output supply for in-package and off-package PSRAM, rated at 50 mA maximum."       },       {         "number": "73",         "name": "VDDO_3",         "type": "power_out",-        "description": "VO3 LDO output rail for external devices, configurable 0.5 to 2.7 V or 3.3 V, supplying up to 50 mA."+        "description": "VDDO_3 is a regulated output supply rated at 50 mA maximum."       },       {         "number": "74",         "name": "VDDO_4",         "type": "power_out",-        "description": "VO4 LDO output rail for external devices, configurable 0.5 to 2.7 V or 3.3 V, supplying up to 50 mA."+        "description": "VDDO_4 is a regulated output supply rated at 50 mA maximum."       },       {         "number": "75",         "name": "VDD_LDO",         "type": "power_in",-        "description": "Analog power domain input that provides power for the LDOs, recommended 3.0 to 3.6 V."+        "description": "VDD_LDO is the analog power domain supply for the internal LDOs, recommended at 3.0 V to 3.6 V (typ. 3.3 V)."       },       {         "number": "76",         "name": "VDD_HP_2",         "type": "power_in",-        "description": "HP digital core supply, recommended 0.99 to 1.3 V (1.1 V typ) per Table 5-2."+        "description": "VDD_HP_2 is a digital core supply, recommended at 0.99 V to 1.3 V (typ. 1.1 V)."       },       {         "number": "77",         "name": "VDD_DCDCC",         "type": "power_in",-        "description": "Analog power domain input for DC/DC control, recommended 3.0 to 3.6 V."+        "description": "VDD_DCDCC is the analog power supply for the DC/DC control circuit, recommended at 3.0 V to 3.6 V (typ. 3.3 V)."       },       {         "number": "78",         "name": "FB_DCDC",         "type": "passive",-        "description": "Feedback pin of the external DC/DC supply, which regulates VDD_HP_0/2/3 together with feedback resistors."+        "description": "FB_DCDC is the feedback pin of the external DC/DC supply, which regulates VDD_HP_0/2/3 together with external feedback resistors."       },       {         "number": "79",         "name": "EN_DCDC",         "type": "output",-        "description": "Enable output for the external DC/DC converter."+        "description": "EN_DCDC is the enable output pin for the external DC/DC converter."       },       {         "number": "80",         "name": "GPIO39",         "type": "bidirectional",-        "description": "GPIO39 is powered by VDD_IO_5 and offers SD1_CDATA0 and the REF_50M_CLK output."+        "description": "GPIO39 is an HP IO powered from VDD_IO_5 that carries the SD1_CDATA0_PAD SDIO data line and the REF_50M_CLK_PAD 50 MHz clock output."       },       {         "number": "81",         "name": "GPIO40",         "type": "bidirectional",-        "description": "GPIO40 is powered by VDD_IO_5 and offers SD1_CDATA1 and the GMAC_PHY_TXEN output."+        "description": "GPIO40 is an HP IO powered from VDD_IO_5 that carries the SD1_CDATA1_PAD SDIO data line and the GMAC_PHY_TXEN_PAD transmit enable output."       },       {         "number": "82",         "name": "GPIO41",         "type": "bidirectional",-        "description": "GPIO41 is powered by VDD_IO_5 and offers SD1_CDATA2 and the GMAC_PHY_TXD0 output."+        "description": "GPIO41 is an HP IO powered from VDD_IO_5 that carries the SD1_CDATA2_PAD SDIO data line and the GMAC_PHY_TXD0_PAD transmit data output."       },       {         "number": "83",         "name": "GPIO42",         "type": "bidirectional",-        "description": "GPIO42 is powered by VDD_IO_5 and offers SD1_CDATA3 and the GMAC_PHY_TXD1 output."+        "description": "GPIO42 is an HP IO powered from VDD_IO_5 that carries the SD1_CDATA3_PAD SDIO data line and the GMAC_PHY_TXD1_PAD transmit data output."       },       {         "number": "84",         "name": "GPIO43",         "type": "bidirectional",-        "description": "GPIO43 is powered by VDD_IO_5 and offers the SD1_CCLK output and the GMAC_PHY_TXER output."+        "description": "GPIO43 is an HP IO powered from VDD_IO_5 that carries the SD1_CCLK_PAD SDIO card clock output and the GMAC_PHY_TXER_PAD transmit error output."       },       {         "number": "85",         "name": "VDD_IO_5",         "type": "power_in",-        "description": "Digital HP IO supply for GPIO39 to GPIO48, recommended 1.65 to 3.6 V (3.3 V typ) per Table 5-2."+        "description": "VDD_IO_5 is the digital IO power supply for the HP IO group, recommended at 1.65 V to 3.6 V (typ. 3.3 V)."       },       {         "number": "86",         "name": "GPIO44",         "type": "bidirectional",-        "description": "GPIO44 is powered by VDD_IO_5 and offers SD1_CCMD and the GMAC_RMII_CLK input."+        "description": "GPIO44 is an HP IO powered from VDD_IO_5 that carries the SD1_CCMD_PAD SDIO command line and the GMAC_RMII_CLK_PAD RMII clock input."       },       {         "number": "87",         "name": "GPIO45",         "type": "bidirectional",-        "description": "GPIO45 is powered by VDD_IO_5 and offers SD1_CDATA4 and the GMAC_PHY_RXDV input."+        "description": "GPIO45 is an HP IO powered from VDD_IO_5 that carries the SD1_CDATA4_PAD SDIO data line and the GMAC_PHY_RXDV_PAD receive data valid input."       },       {         "number": "88",         "name": "GPIO46",         "type": "bidirectional",-        "description": "GPIO46 is powered by VDD_IO_5 and offers SD1_CDATA5 and the GMAC_PHY_RXD0 input."+        "description": "GPIO46 is an HP IO powered from VDD_IO_5 that carries the SD1_CDATA5_PAD SDIO data line and the GMAC_PHY_RXD0_PAD receive data input."       },       {         "number": "89",         "name": "GPIO47",         "type": "bidirectional",-        "description": "GPIO47 is powered by VDD_IO_5 and offers SD1_CDATA6 and the GMAC_PHY_RXD1 input."+        "description": "GPIO47 is an HP IO powered from VDD_IO_5 that carries the SD1_CDATA6_PAD SDIO data line and the GMAC_PHY_RXD1_PAD receive data input."       },       {         "number": "90",         "name": "GPIO48",         "type": "bidirectional",-        "description": "GPIO48 is powered by VDD_IO_5 and offers SD1_CDATA7 and the GMAC_PHY_RXER input."+        "description": "GPIO48 is an HP IO powered from VDD_IO_5 that carries the SD1_CDATA7_PAD SDIO data line and the GMAC_PHY_RXER_PAD receive error input."       },       {         "number": "91",         "name": "VDD_HP_3",         "type": "power_in",-        "description": "HP digital core supply, recommended 0.99 to 1.3 V (1.1 V typ) per Table 5-2."+        "description": "VDD_HP_3 is a digital core supply, recommended at 0.99 V to 1.3 V (typ. 1.1 V)."       },       {         "number": "92",         "name": "GPIO49",         "type": "bidirectional",-        "description": "GPIO49 is powered by VDD_IO_6, offers ADC2_CHANNEL0, and offers the GMAC_PHY_TXEN output."+        "description": "GPIO49 is an HP IO powered from VDD_IO_6 that carries the ADC2_CHANNEL0 analog input and the GMAC_PHY_TXEN_PAD transmit enable output."       },       {         "number": "93",         "name": "GPIO50",         "type": "bidirectional",-        "description": "GPIO50 is powered by VDD_IO_6, offers ADC2_CHANNEL1, and offers the GMAC_RMII_CLK input."+        "description": "GPIO50 is an HP IO powered from VDD_IO_6 that carries the ADC2_CHANNEL1 analog input and the GMAC_RMII_CLK_PAD RMII clock input."       },       {         "number": "94",         "name": "GPIO51",         "type": "bidirectional",-        "description": "GPIO51 is powered by VDD_IO_6, offers ADC2_CHANNEL2, and offers ANA_COMP0."+        "description": "GPIO51 is an HP IO powered from VDD_IO_6 that carries the ADC2_CHANNEL2 and ANA_COMP0 analog functions and the GMAC_PHY_RXDV_PAD receive data valid input."       },       {         "number": "95",         "name": "GPIO52",         "type": "bidirectional",-        "description": "GPIO52 is powered by VDD_IO_6, offers ADC2_CHANNEL3, and offers ANA_COMP0."+        "description": "GPIO52 is an HP IO powered from VDD_IO_6 that carries the ADC2_CHANNEL3 and ANA_COMP0 analog functions and the GMAC_PHY_RXD0_PAD receive data input."       },       {         "number": "96",         "name": "VDD_IO_6",         "type": "power_in",-        "description": "Digital HP IO supply for GPIO49 to GPIO54, recommended 1.65 to 3.6 V (3.3 V typ) per Table 5-2."+        "description": "VDD_IO_6 is the digital IO power supply for the HP IO group, recommended at 1.65 V to 3.6 V (typ. 3.3 V)."       },       {         "number": "97",         "name": "GPIO53",         "type": "bidirectional",-        "description": "GPIO53 is powered by VDD_IO_6, offers ADC2_CHANNEL4, and offers ANA_COMP1."+        "description": "GPIO53 is an HP IO powered from VDD_IO_6 that carries the ADC2_CHANNEL4 and ANA_COMP1 analog functions and the GMAC_PHY_RXD1_PAD receive data input."       },       {         "number": "98",         "name": "GPIO54",         "type": "bidirectional",-        "description": "GPIO54 is powered by VDD_IO_6, offers ADC2_CHANNEL5, and offers ANA_COMP1."+        "description": "GPIO54 is an HP IO powered from VDD_IO_6 that carries the ADC2_CHANNEL5 and ANA_COMP1 analog functions and the GMAC_PHY_RXER_PAD receive error input."       },       {         "number": "99",         "name": "XTAL_N",         "type": "passive",-        "description": "Negative side of the external clock input/output connected to the chip crystal or oscillator (40 MHz XTAL_CLK)."+        "description": "XTAL_N is the negative side of the differential clock connection to the chip's crystal or oscillator."       },       {         "number": "100",         "name": "XTAL_P",         "type": "passive",-        "description": "Positive side of the external clock input/output connected to the chip crystal or oscillator (40 MHz XTAL_CLK)."+        "description": "XTAL_P is the positive side of the differential clock connection to the chip's crystal or oscillator."       },       {         "number": "101",         "name": "VDD_ANA",         "type": "power_in",-        "description": "Analog power domain supply, recommended 3.0 to 3.6 V."+        "description": "VDD_ANA is the analog power domain supply, recommended at 3.0 V to 3.6 V (typ. 3.3 V)."       },       {         "number": "102",         "name": "VDD_BAT",         "type": "power_in",-        "description": "Analog power domain input that can optionally connect to an external battery, recommended 2.5 to 3.6 V."+        "description": "VDD_BAT is the analog power domain supply that can optionally connect to an external battery, recommended at 2.5 V to 3.6 V (typ. 3.3 V)."       },       {         "number": "103",         "name": "CHIP_PU",         "type": "input",-        "description": "Chip enable: high powers up and enables the chip, low powers it down, and it must not be left floating."+        "description": "CHIP_PU is the chip enable input: high enables the chip and low powers it down, and it must not be left floating."       },       {         "number": "104",         "name": "GPIO0",         "type": "bidirectional",-        "description": "GPIO0 is powered by VDD_LP or VDD_BAT and also offers LP_GPIO0 and XTAL_32K_N analog function."+        "description": "GPIO0 is an LP IO powered from VDD_LP/VDD_BAT that carries the XTAL_32K_N analog function and LP_GPIO0."       },       {         "number": "105",         "name": "GND",         "type": "power_in",-        "description": "External ground connection."+        "description": "GND is the external ground connection pin."       }     ],     "provenance": {@@ -687,11 +688,12 @@         "consensus": "agreed",         "guards": "pin_guards 0.1: passed",         "guard_notes": [-          "extractor flagged: The MPN ESP32-P4NRW32 is marked End of Life in this datasheet (upgraded to ESP32-P4NRW32X). The pino; Table 2-11 lists VDD_FLASHIO2 with a footnote, while Table 2-1 and Figure 2-1 name the pin VDD_FLASH; Pin 54 is printed as NC and pin 105 is GND, which is the package ground pad. Pin 105 is typed power_"+          "extractor flagged: The datasheet marks ESP32-P4NRW32 as End of life (EOL), upgraded to ESP32-P4NRW32X, and refers to th; The datasheet pin table (Table 2-1 and Appendix A) lists the QFN104 package for this series. The pac; Pin 30 is named VDD_FLASHIO in Table 2-1 and Figure 2-1, but Table 2-11 writes VDD_FLASHIO2 with a f",+          "9/105 pins cited to the wrong page (name found elsewhere): ['9:VDD_LP@p79', '21:VDD_IO_0@p79', '30:VDD_FLASHIO@p79', '41:VDD_MIPI_DPHY@p79']"         ],-        "pages_sent": 94,-        "cost_usd": 0.2826,-        "at": "2026-10-27T22:22:15"+        "pages_sent": 53,+        "cost_usd": 0.2825,+        "at": "2026-10-28T19:12:25"       },       "datasheet": {         "url": "https://www.espressif.com/sites/default/files/documentation/esp32-p4-chip-revision-v1.3_datasheet_en.pdf",@@ -727,8 +729,27 @@         "zmin_mm": 0,         "centre_offset_mm": 0,         "footprint_binding": "none",-        "sha256": "4768606132501b6e08a104c25fd4482e49df118ce235014d13dd1b2ecba470ee",-        "checked": "2026-10-27",+        "sha256": "457ab6b63d8e996dbb736b913bc7e8e932306d4c484c72ca3c2c8c8418cd18a8",+        "checked": "2026-10-28",+        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+      },+      {+        "file": "esp32-p4nrw32-etched.step",+        "role": "eda",+        "up": "Z",+        "units": "mm",+        "origin": "footprint origin = pad-pattern centre",+        "seat": "z = 0",+        "extents_mm": [+          10.02,+          10.02,+          0.85+        ],+        "zmin_mm": 0,+        "centre_offset_mm": 0,+        "footprint_binding": "none",+        "sha256": "4c84a2b1fdb66dfa038957de4bc65ed976e3e63b5fd37b1524e854a4d58def9a",+        "checked": "2026-10-28",         "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"       }     ]@@ -1106,9 +1127,10 @@     "viewers/symbol.html",     "viewers/footprint.html",     "esp32-p4nrw32-hero.glb",-    "esp32-p4nrw32-hero.overlay.json"+    "esp32-p4nrw32-hero.overlay.json",+    "esp32-p4nrw32-etched.glb"   ],-  "visibility": {-    "public": true-  }+  "visibility": "public",+  "description": "ESPRESSIF Functional Modules, QFN-104(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+  "org": "adom" }\ No newline at end of file