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ESP32-P4NRW16X
Public Made by Adomby adom
Espressif Systems Integrated Circuits (ICs), ESP32-P4. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D. Chip revision v3.x, the newer revision of ESP32-P4NRW16 (v1.x).
3D Model
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Symbol & Footprint
Schematic Symbol
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Datasheet
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Contents
README
markdownESP32-P4NRW16X
Espressif Systems · Integrated Circuits (ICs) · ESP32-P4
ESP32-P4NRW16X from Espressif Systems, in a ESP32-P4. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Silicon revision
ESP32-P4NRW16X is chip revision v3.x, the newer revision. ESP32-P4NRW16 is the older revision, v1.x, in the same 104-pin 10 x 10 mm QFN. Espressif documents them separately: v3.x in the ESP32-P4 Series datasheet (v0.7 covers v3.x only), v1.x in the ESP32-P4 chip revision v1.3 datasheet. Two differences matter for a board, both from Espressif's own KiCad symbols (ESP32-P4 and ESP32-P4X): pin 54 is NC on v1.x but VDD_HP_1 (a supply pin) on v3.x, so a board drawn for v1.x needs pin 54 wired to the supply before it takes a v3.x part; and the ADC pins move. On v1.x GPIO0 to GPIO23 and GPIO49 to GPIO54 are marked ADC; on v3.x only GPIO16 to GPIO23 (ADC1 channels 0 to 7) and GPIO49 to GPIO54 (ADC2 channels 0 to 5) are, so a v1.x design reading an analog input on GPIO0 to GPIO15 needs it moved. Check both against the datasheets before swapping one for the other.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GPIO1 | bidirectional | Powered by VDD_LP or VDD_BAT, it offers IO MUX, LP IO MUX and XTAL_32K_P analog functions with a default drive strength of 20 mA. |
| 2 | GPIO2 | bidirectional | Powered by VDD_LP or VDD_BAT, it has input enabled and weak pull-up at reset, carries the MTCK JTAG function and touch channel 1, with a default drive strength of 20 mA. |
| 3 | GPIO3 | bidirectional | Powered by VDD_LP or VDD_BAT, it has input enabled at reset, carries the MTDI JTAG function and touch channel 2, with a default drive strength of 20 mA. |
| 4 | GPIO4 | bidirectional | Powered by VDD_LP, it has input enabled at reset, carries the MTMS JTAG function and touch channel 3, with a default drive strength of 20 mA. |
| 5 | GPIO5 | bidirectional | Powered by VDD_LP, it carries the MTDO JTAG function and touch channel 4, with a default drive strength of 20 mA. |
| 6 | GPIO6 | bidirectional | Powered by VDD_LP, it carries touch channel 5 and the SPI2_HOLD_PAD function, with a default drive strength of 20 mA. |
| 7 | GPIO7 | bidirectional | Powered by VDD_LP, it carries touch channel 6 and the SPI2_CS_PAD function, with a default drive strength of 20 mA. |
| 8 | GPIO8 | bidirectional | Powered by VDD_LP, it carries touch channel 7, the UART0_RTS_PAD function and the SPI2_D_PAD function, with a default drive strength of 20 mA. |
| 9 | VDD_LP | power_in | LP power domain supply that powers the LP IO pins. |
| 10 | GPIO9 | bidirectional | Powered by VDD_LP, it carries touch channel 8, UART0_CTS_PAD and SPI2_CK_PAD functions, with a default drive strength of 20 mA. |
| 11 | GPIO10 | bidirectional | Powered by VDD_LP, it carries touch channel 9, UART1_TXD_PAD and SPI2_Q_PAD functions, with a default drive strength of 20 mA. |
| 12 | GPIO11 | bidirectional | Powered by VDD_LP, it carries touch channel 10, UART1_RXD_PAD and SPI2_WP_PAD functions, with a default drive strength of 20 mA. |
| 13 | GPIO12 | bidirectional | Powered by VDD_LP, it carries touch channel 11 and UART1_RTS_PAD, with a default drive strength of 20 mA. |
| 14 | GPIO13 | bidirectional | Powered by VDD_LP, it carries touch channel 12 and UART1_CTS_PAD, with a default drive strength of 20 mA. |
| 15 | GPIO14 | bidirectional | Powered by VDD_LP, it carries touch channel 13 and the LP_UART_TXD_PAD function, with a default drive strength of 20 mA. |
| 16 | GPIO15 | bidirectional | Powered by VDD_LP, it carries touch channel 14 and the LP_UART_RXD_PAD function, with a default drive strength of 20 mA. |
| 17 | GPIO16 | bidirectional | Powered by VDD_IO_0, it carries the ADC1_CHANNEL0 analog function with a default drive strength of 20 mA. |
| 18 | GPIO17 | bidirectional | Powered by VDD_IO_0, it carries the ADC1_CHANNEL1 analog function with a default drive strength of 20 mA. |
| 19 | GPIO18 | bidirectional | Powered by VDD_IO_0, it carries the ADC1_CHANNEL2 analog function with a default drive strength of 20 mA. |
| 20 | GPIO19 | bidirectional | Powered by VDD_IO_0, it carries the ADC1_CHANNEL3 analog function with a default drive strength of 20 mA. |
| 21 | VDD_IO_0 | power_in | Digital power domain supply for the HP IO pins GPIO16-GPIO23. |
| 22 | GPIO20 | bidirectional | Powered by VDD_IO_0, it carries the ADC1_CHANNEL4 analog function with a default drive strength of 20 mA. |
| 23 | GPIO21 | bidirectional | Powered by VDD_IO_0, it carries the ADC1_CHANNEL5 analog function with a default drive strength of 20 mA. |
| 24 | GPIO22 | bidirectional | Powered by VDD_IO_0, it carries the ADC1_CHANNEL6 analog function with a default drive strength of 20 mA. |
| 25 | GPIO23 | bidirectional | Powered by VDD_IO_0, it carries the ADC1_CHANNEL7 analog function and the REF_50M_CLK_PAD output with a default drive strength of 20 mA. |
| 26 | VDD_HP_0 | power_in | Digital power domain supply pin. |
| 27 | FLASH_CS | output | Dedicated flash chip-select output connected to off-package flash, powered by VDD_FLASHIO. |
| 28 | FLASH_Q | bidirectional | Dedicated flash data output connection, powered by VDD_FLASHIO. |
| 29 | FLASH_WP | bidirectional | Dedicated flash write-protect connection, powered by VDD_FLASHIO. |
| 30 | VDD_FLASHIO | power_in | Power supply for flash IO, whose voltage should be adjusted to the specific flash model (3.3 V used as example in the datasheet). |
| 31 | FLASH_HOLD | bidirectional | Dedicated flash hold connection, powered by VDD_FLASHIO. |
| 32 | FLASH_CK | output | Dedicated flash clock output, powered by VDD_FLASHIO. |
| 33 | FLASH_D | bidirectional | Dedicated flash data-in connection, powered by VDD_FLASHIO. |
| 34 | DSI_REXT | passive | MIPI DSI PHY external 4.02 kΩ reference resistor pin, powered by VDD_MIPI_DPHY. |
| 35 | DSI_DATAP1 | bidirectional | MIPI DSI PHY positive data channel 1, powered by VDD_MIPI_DPHY. |
| 36 | DSI_DATAN1 | bidirectional | MIPI DSI PHY negative data channel 1, powered by VDD_MIPI_DPHY. |
| 37 | DSI_CLKN | bidirectional | MIPI DSI PHY negative clock channel, powered by VDD_MIPI_DPHY. |
| 38 | DSI_CLKP | bidirectional | MIPI DSI PHY positive clock channel, powered by VDD_MIPI_DPHY. |
| 39 | DSI_DATAP0 | bidirectional | MIPI DSI PHY positive data channel 0, powered by VDD_MIPI_DPHY. |
| 40 | DSI_DATAN0 | bidirectional | MIPI DSI PHY negative data channel 0, powered by VDD_MIPI_DPHY. |
| 41 | VDD_MIPI_DPHY | power_in | MIPI PHY power supply for the MIPI DSI and CSI pins. |
| 42 | CSI_DATAN0 | bidirectional | MIPI CSI PHY negative data channel 0, powered by VDD_MIPI_DPHY. |
| 43 | CSI_DATAP0 | bidirectional | MIPI CSI PHY positive data channel 0, powered by VDD_MIPI_DPHY. |
| 44 | CSI_CLKP | bidirectional | MIPI CSI PHY positive clock channel, powered by VDD_MIPI_DPHY. |
| 45 | CSI_CLKN | bidirectional | MIPI CSI PHY negative clock channel, powered by VDD_MIPI_DPHY. |
| 46 | CSI_DATAN1 | bidirectional | MIPI CSI PHY negative data channel 1, powered by VDD_MIPI_DPHY. |
| 47 | CSI_DATAP1 | bidirectional | MIPI CSI PHY positive data channel 1, powered by VDD_MIPI_DPHY. |
| 48 | CSI_REXT | passive | MIPI CSI PHY external 4.02 kΩ reference resistor pin, powered by VDD_MIPI_DPHY. |
| 49 | USB_DM | bidirectional | USB 2.0 High-Speed OTG PHY D- signal, powered by VDD_USBPHY. |
| 50 | USB_DP | bidirectional | USB 2.0 High-Speed OTG PHY D+ signal, powered by VDD_USBPHY. |
| 51 | VDD_USBPHY | power_in | USB PHY power supply for the high-speed USB IO pins. |
| 52 | GPIO24 | bidirectional | Powered by VDD_IO_4, it carries USB1P1_N0 (USB Serial/JTAG by default) with a default drive strength of 40 mA. |
| 53 | GPIO25 | bidirectional | Powered by VDD_IO_4, it carries USB1P1_P0 (USB Serial/JTAG by default) with USB pull-up at reset and a default drive strength of 40 mA. |
| 54 | VDD_HP_1 | power_in | Digital power domain supply pin. |
| 55 | GPIO26 | bidirectional | Powered by VDD_IO_4, it carries USB1P1_N1 (USB 2.0 Full-Speed OTG by default) with a default drive strength of 20 mA. |
| 56 | GPIO27 | bidirectional | Powered by VDD_IO_4, it carries USB1P1_P1 (USB 2.0 Full-Speed OTG by default) with a default drive strength of 20 mA. |
| 57 | GPIO28 | bidirectional | Powered by VDD_IO_4, it carries the SPI2_CS_PAD and GMAC_PHY_RXDV_PAD functions with a default drive strength of 20 mA. |
| 58 | GPIO29 | bidirectional | Powered by VDD_IO_4, it carries the SPI2_D_PAD and GMAC_PHY_RXD0_PAD functions with a default drive strength of 20 mA. |
| 59 | VDD_PSRAM_0 | power_in | PSRAM power supply pin for PSRAM IO, specified at 1.8 V in Table 5-2. |
| 60 | GPIO30 | bidirectional | Powered by VDD_IO_4, it carries the SPI2_CK_PAD and GMAC_PHY_RXD1_PAD functions with a default drive strength of 20 mA. |
| 61 | GPIO31 | bidirectional | Powered by VDD_IO_4, it carries the SPI2_Q_PAD and GMAC_PHY_RXER_PAD functions with a default drive strength of 20 mA. |
| 62 | VDD_IO_4 | power_in | Digital power domain supply for HP IO pins GPIO24-GPIO31 and GPIO32-GPIO38. |
| 63 | GPIO32 | bidirectional | Powered by VDD_IO_4, input enabled at reset, it is a dedicated I3C master SCL pin with configurable pull-up that can also be used as GPIO. |
| 64 | GPIO33 | bidirectional | Powered by VDD_IO_4, input enabled at reset, it is a dedicated I3C master SDA pin with configurable pull-up that can also be used as GPIO. |
| 65 | GPIO34 | bidirectional | Powered by VDD_IO_4, input enabled at reset, it is a strapping pin that selects the JTAG signal source. |
| 66 | GPIO35 | bidirectional | Powered by VDD_IO_4, input enabled with weak pull-up at reset, it is a strapping pin for chip boot mode. |
| 67 | VDD_PSRAM_1 | power_in | PSRAM power supply pin for PSRAM IO, specified at 1.8 V in Table 5-2. |
| 68 | GPIO36 | bidirectional | Powered by VDD_IO_4, input enabled at reset, it is a strapping pin that controls ROM message printing. |
| 69 | GPIO37 | bidirectional | Powered by VDD_IO_4, it is a strapping pin for chip boot mode and carries UART0_TXD_PAD. |
| 70 | GPIO38 | bidirectional | Powered by VDD_IO_4, input enabled at reset, it is a strapping pin for chip boot mode and carries UART0_RXD_PAD. |
| 71 | VDDO_FLASH | power_out | Output supply for off-package flash, rated at 50 mA maximum. |
| 72 | VDDO_PSRAM | power_out | Output supply for in-package and off-package PSRAM, rated at 50 mA maximum. |
| 73 | VDDO_3 | power_out | Output supply rated at 50 mA maximum. |
| 74 | VDDO_4 | power_out | Output supply rated at 50 mA maximum. |
| 75 | VDD_LDO | power_in | Analog power domain supply providing power for the LDOs. |
| 76 | VDD_HP_2 | power_in | Digital power domain supply pin. |
| 77 | VDD_DCDCC | power_in | Analog power domain supply providing power for the DC/DC control. |
| 78 | FB_DCDC | passive | Feedback pin of the power supply for the external DC/DC, which regulates VDD_HP_0/1/2/3 together with feedback resistors. |
| 79 | EN_DCDC | output | Enable pin for the external DC/DC converter. |
| 80 | GPIO39 | bidirectional | Powered by VDD_IO_5, it carries SD1_CDATA0_PAD and REF_50M_CLK_PAD functions with a default drive strength of 20 mA. |
| 81 | GPIO40 | bidirectional | Powered by VDD_IO_5, it carries SD1_CDATA1_PAD and GMAC_PHY_TXEN_PAD functions with a default drive strength of 20 mA. |
| 82 | GPIO41 | bidirectional | Powered by VDD_IO_5, it carries SD1_CDATA2_PAD and GMAC_PHY_TXD0_PAD functions with a default drive strength of 20 mA. |
| 83 | GPIO42 | bidirectional | Powered by VDD_IO_5, it carries SD1_CDATA3_PAD and GMAC_PHY_TXD1_PAD functions with a default drive strength of 20 mA. |
| 84 | GPIO43 | bidirectional | Powered by VDD_IO_5, it carries SD1_CCLK_PAD and GMAC_PHY_TXER_PAD functions with a default drive strength of 20 mA. |
| 85 | VDD_IO_5 | power_in | Digital power domain supply for HP IO pins GPIO39-GPIO48. |
| 86 | GPIO44 | bidirectional | Powered by VDD_IO_5, it carries SD1_CCMD_PAD and GMAC_RMII_CLK_PAD functions with a default drive strength of 20 mA. |
| 87 | GPIO45 | bidirectional | Powered by VDD_IO_5, it carries SD1_CDATA4_PAD and GMAC_PHY_RXDV_PAD functions with a default drive strength of 20 mA. |
| 88 | GPIO46 | bidirectional | Powered by VDD_IO_5, it carries SD1_CDATA5_PAD and GMAC_PHY_RXD0_PAD functions with a default drive strength of 20 mA. |
| 89 | GPIO47 | bidirectional | Powered by VDD_IO_5, it carries SD1_CDATA6_PAD and GMAC_PHY_RXD1_PAD functions with a default drive strength of 20 mA. |
| 90 | GPIO48 | bidirectional | Powered by VDD_IO_5, it carries SD1_CDATA7_PAD and GMAC_PHY_RXER_PAD functions with a default drive strength of 20 mA. |
| 91 | VDD_HP_3 | power_in | Digital power domain supply pin. |
| 92 | GPIO49 | bidirectional | Powered by VDD_IO_6, it carries ADC2_CHANNEL0 and GMAC_PHY_TXEN_PAD functions with a default drive strength of 20 mA. |
| 93 | GPIO50 | bidirectional | Powered by VDD_IO_6, it carries ADC2_CHANNEL1 and GMAC_RMII_CLK_PAD functions with a default drive strength of 20 mA. |
| 94 | GPIO51 | bidirectional | Powered by VDD_IO_6, it carries ADC2_CHANNEL2, ANA_COMP0 and GMAC_PHY_RXDV_PAD functions with a default drive strength of 20 mA. |
| 95 | GPIO52 | bidirectional | Powered by VDD_IO_6, it carries ADC2_CHANNEL3, ANA_COMP0 and GMAC_PHY_RXD0_PAD functions with a default drive strength of 20 mA. |
| 96 | VDD_IO_6 | power_in | Digital power domain supply for HP IO pins GPIO49-GPIO54. |
| 97 | GPIO53 | bidirectional | Powered by VDD_IO_6, it carries ADC2_CHANNEL4, ANA_COMP1 and GMAC_PHY_RXD1_PAD functions with a default drive strength of 20 mA. |
| 98 | GPIO54 | bidirectional | Powered by VDD_IO_6, it carries ADC2_CHANNEL5, ANA_COMP1 and GMAC_PHY_RXER_PAD functions with a default drive strength of 20 mA. |
| 99 | XTAL_N | passive | Negative terminal of the differential external clock connected to the chip crystal or oscillator. |
| 100 | XTAL_P | passive | Positive terminal of the differential external clock connected to the chip crystal or oscillator. |
| 101 | VDD_ANA | power_in | Analog power domain supply pin. |
| 102 | VDD_BAT | power_in | Analog power domain supply that can optionally connect to an external battery and powers LP IO pins. |
| 103 | CHIP_PU | input | Chip enable input where high enables the chip and low disables it; it must not be left floating. |
| 104 | GPIO0 | bidirectional | Powered by VDD_LP or VDD_BAT, it offers IO MUX, LP IO MUX and XTAL_32K_N analog functions with a default drive strength of 20 mA. |
| 105 | GND | power_in | External ground connection for the package. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Espressif Systems |
| Package | ESP32-P4 |
| Category | Integrated Circuits (ICs) |
| Pins | 105 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Recommended input voltage (VDD_LDO, VDD_DCDCC, VDD_ANA, VDD_LP) | 3 | 3.3 | 3.6 | V | 88 | ||
| Recommended input voltage (VDD_BAT) | 2.5 | 3.3 | 3.6 | V | 88 | ||
| Recommended input voltage (VDD_IO_0, VDD_FLASHIO, VDD_IO_4, VDD_IO_5, VDD_IO_6) | 1.65 | 1.8 | 3.6 | V | 88 | ||
| Recommended input voltage (VDD_PSRAM_0, VDD_PSRAM_1) | 1.65 | 1.8 | 1.95 | V | 88 | ||
| Recommended input voltage (VDD_HP_0, VDD_HP_1, VDD_HP_2, VDD_HP_3) | 0.99 | 1.1 | 1.3 | V | 89 | ||
| Recommended input voltage (VDD_MIPI_DPHY) | 2.25 | 2.5 | 2.75 | V | 89 | ||
| Recommended input voltage (VDD_USBPHY) | 2.97 | 3.3 | 3.63 | V | 89 | ||
| Current supplied to core | IVDD | 0.5 | A | 89 | |||
| Ambient temperature | TA | -40 | 85 | °C | 89 | ||
| Allowed input voltage (VDD_LDO, VDD_DCDCC, VDD_ANA, VDD_BAT, VDD_LP) | -0.3 | 3.6 | V | 88 | |||
| Allowed input voltage (VDD_IO_0, VDD_FLASHIO, VDD_IO_4, VDD_IO_5, VDD_IO_6) | -0.3 | 3.6 | V | 88 | |||
| Allowed input voltage (VDD_PSRAM_0, VDD_PSRAM_1) | 1.62 | 1.98 | V | 88 | |||
| Allowed input voltage (VDD_HP_0, VDD_HP_1, VDD_HP_2, VDD_HP_3) | 0 | 1.3 | V | 88 | |||
| Allowed input voltage (VDD_MIPI_DPHY) | 0 | 2.75 | V | 88 | |||
| Allowed input voltage (VDD_USBPHY) | -0.66 | 3.96 | V | 88 | |||
| Cumulative IO output current | Ioutput | 1500 | mA | 88 | |||
| Storage temperature | TSTORE | -40 | 150 | °C | 88 | ||
| DNL (Differential nonlinearity) | DNL | -1 | 3 | LSB | ADC measurements with external 100 nF capacitor, DC input, 25 °C | 90 | |
| INL (Integral nonlinearity) | INL | -5 | 3 | LSB | ADC measurements with external 100 nF capacitor, DC input, 25 °C | 90 | |
| Sampling rate | 100 | kSPS | 90 | ||||
| Total error, ATTEN0, effective measurement range of 0-1000 | -12 | 12 | mV | Calibrated ADC results after hardware and software calibration | 90 | ||
| Total error, ATTEN1, effective measurement range of 0-1300 | -12 | 12 | mV | Calibrated ADC results after hardware and software calibration | 90 | ||
| Total error, ATTEN2, effective measurement range of 0-1900 | -12 | 12 | mV | Calibrated ADC results after hardware and software calibration | 90 | ||
| Total error, ATTEN3, effective measurement range of 0-3300 | -15 | 15 | mV | Calibrated ADC results after hardware and software calibration | 90 | ||
| Power supply voltage (1.8 V) | VCC | 1.62 | 1.8 | 1.98 | V | PSRAM specification, sourced from memory vendor datasheet | 92 |
| Power supply voltage (3.3 V) | VCC | 2.7 | 3.3 | 3.6 | V | PSRAM specification, sourced from memory vendor datasheet | 92 |
| Maximum clock frequency | FC | 80 | MHz | PSRAM specification, sourced from memory vendor datasheet | 92 |
CAD (KiCad official)
- Symbol:
ESP32-P4NRW16X - Footprint:
PCM_Espressif:ESP32-P4 - 3D model: ESP32-P4, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.85 mm nominal QFN height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files:
esp32-p4nrw16x-etched.step/esp32-p4nrw16x-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);esp32-p4nrw16x.step/esp32-p4nrw16x.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Espressif Systems datasheet (102 pp, sha256
fb4f3e91cc2ac519, retrieved 2026-10-29, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).