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ESP32-C6FH4
Public Made by Adomby adom
Espressif Systems RF and Wireless, 32-VFQFN Exposed Pad. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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ESP32-C6FH4
Espressif Systems · RF and Wireless · 32-VFQFN Exposed Pad
ESP32-C6FH4 from Espressif Systems, in a 32-VFQFN Exposed Pad. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | ANT | bidirectional | RF input and output pin for the antenna. |
| 2 | VDDA3P3 | power_in | Input for the analog power domain. |
| 3 | VDDA3P3 | power_in | Input for the analog power domain. |
| 4 | CHIP_PU | input | Chip enable: high powers up the chip, low powers it down, and it must not be left floating. |
| 5 | VDDPST1 | power_in | Input for the LP digital and part of the analog pin power domains, supplying the LP IO pins. |
| 6 | XTAL_32K_P | bidirectional | Positive terminal of the 32 kHz external clock crystal or oscillator, also usable as GPIO0 and ADC1_CH0. |
| 7 | XTAL_32K_N | bidirectional | Negative terminal of the 32 kHz external clock crystal or oscillator, also usable as GPIO1 and ADC1_CH1. |
| 8 | GPIO2 | bidirectional | General-purpose IO that is also usable as ADC1_CH2 and as the FSPIQ SPI2 signal, with input enabled after reset. |
| 9 | GPIO3 | bidirectional | General-purpose IO that is also usable as ADC1_CH3 and as an LP IO, with input enabled after reset. |
| 10 | MTMS | bidirectional | JTAG test mode select, also usable as ADC1_CH4 and as the FSPIHD SPI2 signal; a strapping pin. |
| 11 | MTDI | bidirectional | JTAG test data input, also usable as ADC1_CH5 and as the FSPIWP SPI2 signal; a strapping pin. |
| 12 | MTCK | bidirectional | JTAG test clock, also usable as ADC1_CH6 and as the FSPICLK SPI2 signal, with input and weak pull-up enabled at reset unless EFUSE_DIS_PAD_JTAG is set. |
| 13 | MTDO | bidirectional | JTAG test data output, also usable as GPIO7 and as the FSPID SPI2 signal. |
| 14 | GPIO8 | bidirectional | General-purpose IO that is also a strapping pin used for chip boot mode and ROM message printing control. |
| 15 | GPIO9 | bidirectional | General-purpose IO that is also a strapping pin used for chip boot mode control, with weak pull-up enabled at reset. |
| 16 | GPIO12 | bidirectional | General-purpose IO that is also the USB_D- signal of the USB Serial/JTAG controller, with a default drive strength of 40 mA. |
| 17 | GPIO13 | bidirectional | General-purpose IO that is also the USB_D+ signal of the USB Serial/JTAG controller, with a default drive strength of 40 mA. |
| 18 | GPIO14 | bidirectional | General-purpose IO with input enabled after reset. |
| 19 | GPIO15 | bidirectional | General-purpose IO that is also a strapping pin used for the JTAG signal source control, with input enabled. |
| 20 | VDDPST2 | power_in | Input for the HP digital power domain, supplying the HP IO pins. |
| 21 | U0TXD | bidirectional | UART0 transmit data output, also usable as GPIO16 and as the FSPICS0 SPI2 signal, with output enabled. |
| 22 | U0RXD | bidirectional | UART0 receive data input, also usable as GPIO17 and as the FSPICS1 SPI2 signal, with input and weak pull-up enabled at reset. |
| 23 | SDIO_CMD | bidirectional | SDIO interface command signal, also usable as GPIO18 and as the FSPICS2 SPI2 signal, with weak pull-up enabled at reset. |
| 24 | SDIO_CLK | bidirectional | SDIO interface clock signal, also usable as GPIO19 and as the FSPICS3 SPI2 signal, with weak pull-up enabled at reset. |
| 25 | SDIO_DATA0 | bidirectional | SDIO interface data line 0, also usable as GPIO20 and as the FSPICS4 SPI2 signal, with weak pull-up enabled at reset. |
| 26 | SDIO_DATA1 | bidirectional | SDIO interface data line 1, also usable as GPIO21 and as the FSPICS5 SPI2 signal, with weak pull-up enabled at reset. |
| 27 | SDIO_DATA2 | bidirectional | SDIO interface data line 2, also usable as GPIO22, with weak pull-up enabled at reset. |
| 28 | SDIO_DATA3 | bidirectional | SDIO interface data line 3, also usable as GPIO23, with weak pull-up enabled at reset. |
| 29 | VDDA1 | power_in | Input for the analog power domain. |
| 30 | XTAL_N | passive | Negative differential clock input/output connected to the chip's crystal or oscillator. |
| 31 | XTAL_P | passive | Positive differential clock input/output connected to the chip's crystal or oscillator. |
| 32 | VDDA2 | power_in | Input for the analog power domain. |
| 33 | GND | power_in | External ground connection, the exposed pad of the QFN32 package. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Espressif Systems |
| Package | 32-VFQFN Exposed Pad |
| Category | RF and Wireless |
| Pins | 33 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Allowed input voltage (input power pins) | -0.3 | 3.6 | V | 64 | |||
| Cumulative IO output current | Ioutput | 1000 | mA | 64 | |||
| Storage temperature | TSTORE | -40 | 150 | °C | 64 | ||
| Recommended input voltage (VDDA1, VDDA2, VDDA3P3) | VDDA1, VDDA2, VDDA3P3 | 3 | 3.3 | 3.6 | V | 64 | |
| Recommended input voltage (VDDPST1) | VDDPST1 | 3 | 3.3 | 3.6 | V | 64 | |
| Recommended input voltage (VDD_SPI as input) | VDD_SPI | 3 | 3.3 | 3.6 | V | as input | 64 |
| Recommended input voltage (VDDPST2) | VDDPST2 | 3 | 3.3 | 3.6 | V | 64 | |
| Cumulative input current | IVDD | 0.5 | A | 64 | |||
| Ambient temperature | TA | -40 | 105 | °C | 64 | ||
| High-level input current | IIH | 50 | nA | 65 | |||
| Low-level input current | IIL | 50 | nA | 65 | |||
| Differential nonlinearity (ADC) | DNL | -8 | 12 | LSB | 66 | ||
| Integral nonlinearity (ADC) | INL | -10 | 10 | LSB | 66 | ||
| ADC sampling rate | 100 | kSPS | 66 | ||||
| ADC total error | -12 | 12 | mV | ATTEN0, effective measurement range of 0 ~ 1000 | 66 | ||
| ADC total error | -23 | 23 | mV | ATTEN2, effective measurement range of 0 ~ 1900 | 66 | ||
| ADC total error | -40 | 40 | mV | ATTEN3, effective measurement range of 0 ~ 3300 | 66 | ||
| Flash power supply voltage (1.8 V) | VCC | 1.65 | 1.8 | 2 | V | Power supply voltage (1.8 V) | 68 |
| Flash power supply voltage (3.3 V) | VCC | 2.7 | 3.3 | 3.6 | V | Power supply voltage (3.3 V) | 68 |
| Flash maximum clock frequency | FC | 80 | MHz | 68 | |||
| Flash program/erase cycles | 100000 | cycles | 68 | ||||
| Flash data retention time | TRET | 20 | years | 68 | |||
| Flash page program time | TPP | 0.8 | 5 | ms | Page program time | 68 | |
| Flash sector erase time (4 KB) | TSE | 70 | 500 | ms | Sector erase time (4 KB) | 68 | |
| Flash block erase time (32 KB) | TBE1 | 0.2 | 2 | s | Block erase time (32 KB) | 68 | |
| Flash block erase time (64 KB) | TBE2 | 0.3 | 3 | s | Block erase time (64 KB) | 68 | |
| Flash chip erase time (16 Mb) | TCE | 7 | 20 | s | Chip erase time (16 Mb) | 68 | |
| Flash chip erase time (32 Mb) | TCE | 20 | 60 | s | Chip erase time (32 Mb) | 68 | |
| Flash chip erase time (64 Mb) | TCE | 25 | 100 | s | Chip erase time (64 Mb) | 68 | |
| Flash chip erase time (128 Mb) | TCE | 60 | 200 | s | Chip erase time (128 Mb) | 68 | |
| Flash chip erase time (256 Mb) | TCE | 70 | 300 | s | Chip erase time (256 Mb) | 68 | |
| ESD HBM | -2000 | 2000 | V | HBM (Human Body Mode) | 68 | ||
| ESD CDM | -1000 | 1000 | V | CDM (Charge Device Mode) | 68 | ||
| Latch-up current trigger | -200 | 200 | mA | Current trigger | 68 | ||
| Bluetooth LE RF transmit power range | -15 | 20 | dBm | 73 | |||
| 802.15.4 RF transmit power range | -15 | 20 | dBm | 77 | |||
| Wi-Fi center frequency range of operating channel | 2412 | 2484 | MHz | Center frequency range of operating channel | 70 | ||
| Bluetooth LE center frequency range of operating channel | 2402 | 2480 | MHz | Center frequency range of operating channel | 73 | ||
| 802.15.4 center frequency range of operating channel | 2405 | 2480 | MHz | Center frequency range of operating channel | 77 |
CAD (KiCad official)
- Symbol:
ESP32-C6FH4 - Footprint:
Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.6x3.6mm - 3D model: 32-VFQFN Exposed Pad (KiCad packages3D, STEP)
- 3D model files:
esp32-c6fh4-etched.step/esp32-c6fh4-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);esp32-c6fh4.step/esp32-c6fh4.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Espressif Systems datasheet (86 pp, sha256
372a5b42b2900c83, retrieved 2026-10-27, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# ESP32-C6FH4
**Espressif Systems** · RF and Wireless · 32-VFQFN Exposed Pad
ESP32-C6FH4 from Espressif Systems, in a 32-VFQFN Exposed Pad. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | ANT | bidirectional | RF input and output pin for the antenna. |
| 2 | VDDA3P3 | power_in | Input for the analog power domain. |
| 3 | VDDA3P3 | power_in | Input for the analog power domain. |
| 4 | CHIP_PU | input | Chip enable: high powers up the chip, low powers it down, and it must not be left floating. |
| 5 | VDDPST1 | power_in | Input for the LP digital and part of the analog pin power domains, supplying the LP IO pins. |
| 6 | XTAL_32K_P | bidirectional | Positive terminal of the 32 kHz external clock crystal or oscillator, also usable as GPIO0 and ADC1_CH0. |
| 7 | XTAL_32K_N | bidirectional | Negative terminal of the 32 kHz external clock crystal or oscillator, also usable as GPIO1 and ADC1_CH1. |
| 8 | GPIO2 | bidirectional | General-purpose IO that is also usable as ADC1_CH2 and as the FSPIQ SPI2 signal, with input enabled after reset. |
| 9 | GPIO3 | bidirectional | General-purpose IO that is also usable as ADC1_CH3 and as an LP IO, with input enabled after reset. |
| 10 | MTMS | bidirectional | JTAG test mode select, also usable as ADC1_CH4 and as the FSPIHD SPI2 signal; a strapping pin. |
| 11 | MTDI | bidirectional | JTAG test data input, also usable as ADC1_CH5 and as the FSPIWP SPI2 signal; a strapping pin. |
| 12 | MTCK | bidirectional | JTAG test clock, also usable as ADC1_CH6 and as the FSPICLK SPI2 signal, with input and weak pull-up enabled at reset unless EFUSE_DIS_PAD_JTAG is set. |
| 13 | MTDO | bidirectional | JTAG test data output, also usable as GPIO7 and as the FSPID SPI2 signal. |
| 14 | GPIO8 | bidirectional | General-purpose IO that is also a strapping pin used for chip boot mode and ROM message printing control. |
| 15 | GPIO9 | bidirectional | General-purpose IO that is also a strapping pin used for chip boot mode control, with weak pull-up enabled at reset. |
| 16 | GPIO12 | bidirectional | General-purpose IO that is also the USB_D- signal of the USB Serial/JTAG controller, with a default drive strength of 40 mA. |
| 17 | GPIO13 | bidirectional | General-purpose IO that is also the USB_D+ signal of the USB Serial/JTAG controller, with a default drive strength of 40 mA. |
| 18 | GPIO14 | bidirectional | General-purpose IO with input enabled after reset. |
| 19 | GPIO15 | bidirectional | General-purpose IO that is also a strapping pin used for the JTAG signal source control, with input enabled. |
| 20 | VDDPST2 | power_in | Input for the HP digital power domain, supplying the HP IO pins. |
| 21 | U0TXD | bidirectional | UART0 transmit data output, also usable as GPIO16 and as the FSPICS0 SPI2 signal, with output enabled. |
| 22 | U0RXD | bidirectional | UART0 receive data input, also usable as GPIO17 and as the FSPICS1 SPI2 signal, with input and weak pull-up enabled at reset. |
| 23 | SDIO_CMD | bidirectional | SDIO interface command signal, also usable as GPIO18 and as the FSPICS2 SPI2 signal, with weak pull-up enabled at reset. |
| 24 | SDIO_CLK | bidirectional | SDIO interface clock signal, also usable as GPIO19 and as the FSPICS3 SPI2 signal, with weak pull-up enabled at reset. |
| 25 | SDIO_DATA0 | bidirectional | SDIO interface data line 0, also usable as GPIO20 and as the FSPICS4 SPI2 signal, with weak pull-up enabled at reset. |
| 26 | SDIO_DATA1 | bidirectional | SDIO interface data line 1, also usable as GPIO21 and as the FSPICS5 SPI2 signal, with weak pull-up enabled at reset. |
| 27 | SDIO_DATA2 | bidirectional | SDIO interface data line 2, also usable as GPIO22, with weak pull-up enabled at reset. |
| 28 | SDIO_DATA3 | bidirectional | SDIO interface data line 3, also usable as GPIO23, with weak pull-up enabled at reset. |
| 29 | VDDA1 | power_in | Input for the analog power domain. |
| 30 | XTAL_N | passive | Negative differential clock input/output connected to the chip's crystal or oscillator. |
| 31 | XTAL_P | passive | Positive differential clock input/output connected to the chip's crystal or oscillator. |
| 32 | VDDA2 | power_in | Input for the analog power domain. |
| 33 | GND | power_in | External ground connection, the exposed pad of the QFN32 package. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Espressif Systems |
| Package | 32-VFQFN Exposed Pad |
| Category | RF and Wireless |
| Pins | 33 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Allowed input voltage (input power pins) | | -0.3 | | 3.6 | V | | 64 |
| Cumulative IO output current | Ioutput | | | 1000 | mA | | 64 |
| Storage temperature | TSTORE | -40 | | 150 | °C | | 64 |
| Recommended input voltage (VDDA1, VDDA2, VDDA3P3) | VDDA1, VDDA2, VDDA3P3 | 3 | 3.3 | 3.6 | V | | 64 |
| Recommended input voltage (VDDPST1) | VDDPST1 | 3 | 3.3 | 3.6 | V | | 64 |
| Recommended input voltage (VDD_SPI as input) | VDD_SPI | 3 | 3.3 | 3.6 | V | as input | 64 |
| Recommended input voltage (VDDPST2) | VDDPST2 | 3 | 3.3 | 3.6 | V | | 64 |
| Cumulative input current | IVDD | 0.5 | | | A | | 64 |
| Ambient temperature | TA | -40 | | 105 | °C | | 64 |
| High-level input current | IIH | | | 50 | nA | | 65 |
| Low-level input current | IIL | | | 50 | nA | | 65 |
| Differential nonlinearity (ADC) | DNL | -8 | | 12 | LSB | | 66 |
| Integral nonlinearity (ADC) | INL | -10 | | 10 | LSB | | 66 |
| ADC sampling rate | | | | 100 | kSPS | | 66 |
| ADC total error | | -12 | | 12 | mV | ATTEN0, effective measurement range of 0 ~ 1000 | 66 |
| ADC total error | | -23 | | 23 | mV | ATTEN2, effective measurement range of 0 ~ 1900 | 66 |
| ADC total error | | -40 | | 40 | mV | ATTEN3, effective measurement range of 0 ~ 3300 | 66 |
| Flash power supply voltage (1.8 V) | VCC | 1.65 | 1.8 | 2 | V | Power supply voltage (1.8 V) | 68 |
| Flash power supply voltage (3.3 V) | VCC | 2.7 | 3.3 | 3.6 | V | Power supply voltage (3.3 V) | 68 |
| Flash maximum clock frequency | FC | 80 | | | MHz | | 68 |
| Flash program/erase cycles | | 100000 | | | cycles | | 68 |
| Flash data retention time | TRET | 20 | | | years | | 68 |
| Flash page program time | TPP | | 0.8 | 5 | ms | Page program time | 68 |
| Flash sector erase time (4 KB) | TSE | | 70 | 500 | ms | Sector erase time (4 KB) | 68 |
| Flash block erase time (32 KB) | TBE1 | | 0.2 | 2 | s | Block erase time (32 KB) | 68 |
| Flash block erase time (64 KB) | TBE2 | | 0.3 | 3 | s | Block erase time (64 KB) | 68 |
| Flash chip erase time (16 Mb) | TCE | | 7 | 20 | s | Chip erase time (16 Mb) | 68 |
| Flash chip erase time (32 Mb) | TCE | | 20 | 60 | s | Chip erase time (32 Mb) | 68 |
| Flash chip erase time (64 Mb) | TCE | | 25 | 100 | s | Chip erase time (64 Mb) | 68 |
| Flash chip erase time (128 Mb) | TCE | | 60 | 200 | s | Chip erase time (128 Mb) | 68 |
| Flash chip erase time (256 Mb) | TCE | | 70 | 300 | s | Chip erase time (256 Mb) | 68 |
| ESD HBM | | -2000 | | 2000 | V | HBM (Human Body Mode) | 68 |
| ESD CDM | | -1000 | | 1000 | V | CDM (Charge Device Mode) | 68 |
| Latch-up current trigger | | -200 | | 200 | mA | Current trigger | 68 |
| Bluetooth LE RF transmit power range | | -15 | | 20 | dBm | | 73 |
| 802.15.4 RF transmit power range | | -15 | | 20 | dBm | | 77 |
| Wi-Fi center frequency range of operating channel | | 2412 | | 2484 | MHz | Center frequency range of operating channel | 70 |
| Bluetooth LE center frequency range of operating channel | | 2402 | | 2480 | MHz | Center frequency range of operating channel | 73 |
| 802.15.4 center frequency range of operating channel | | 2405 | | 2480 | MHz | Center frequency range of operating channel | 77 |
## CAD (KiCad official)
- Symbol: `ESP32-C6FH4`
- Footprint: `Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.6x3.6mm`
- 3D model: 32-VFQFN Exposed Pad (KiCad packages3D, STEP)
- 3D model files: `esp32-c6fh4-etched.step` / `esp32-c6fh4-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `esp32-c6fh4.step` / `esp32-c6fh4.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Espressif Systems datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-c6_datasheet_en.pdf) (86 pp, sha256 `372a5b42b2900c83`, retrieved 2026-10-27, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/esp32-c6fh4-datasheet.pdf)