component
ESP32-C5HR2
Public Made by Adomby adom
Espressif Systems RF and Wireless, QFN-48-1EP_6x6mm_P0.4mm_EP4.6x4.6mm. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Made with kicad-footprint-generator 10.0 · KiCad file format 20260206
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ESP32-C5HR2
Espressif Systems · RF and Wireless · QFN-48-1EP_6x6mm_P0.4mm_EP4.6x4.6mm
ESP32-C5HR2 from Espressif Systems, in a QFN-48-1EP_6x6mm_P0.4mm_EP4.6x4.6mm. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDDA6 | power_in | Analog power domain supply input, 3.3 V. |
| 2 | GND | power_in | External ground connection. |
| 3 | VDDA7 | power_in | Analog power domain supply input, 3.3 V. |
| 4 | XTAL_N | passive | Negative side of the differential external clock input/output connected to the chip's crystal or oscillator. |
| 5 | XTAL_P | passive | Positive side of the differential external clock input/output connected to the chip's crystal or oscillator. |
| 6 | VDDA8 | power_in | Analog power domain supply input, 3.3 V. |
| 7 | CHIP_PU | input | Chip enable and reset, powered from VDDPST1: high powers the chip on, low powers it off, and the pin must not be left floating. |
| 8 | VDDPST1 | power_in | Supply input for the LP digital power domain and the LP IO pins. |
| 9 | XTAL_32K_P | bidirectional | GPIO0/LP_GPIO0 powered by VDDPST1, with the 32 kHz crystal positive analog function and LP_UART_DTRN. |
| 10 | XTAL_32K_N | bidirectional | GPIO1/LP_GPIO1 powered by VDDPST1, with the 32 kHz crystal negative analog function, ADC1_CH0 and LP_UART_DSRN. |
| 11 | MTMS | bidirectional | GPIO2/LP_GPIO2 powered by VDDPST1 with JTAG MTMS, FSPIQ, ADC1_CH1, LP_UART_RTSN and LP_I2C_SDA; it is a strapping pin and input is enabled at and after reset. |
| 12 | MTDI | bidirectional | GPIO3/LP_GPIO3 powered by VDDPST1 with JTAG MTDI, ADC1_CH2, LP_UART_CTSN and LP_I2C_SCL; it is a strapping pin for SDIO sampling and driving clock edge and input is enabled at and after reset. |
| 13 | MTCK | bidirectional | GPIO4/LP_GPIO4 powered by VDDPST1 with JTAG MTCK, FSPIHD, ADC1_CH3 and LP_UART_RXD; input and weak pull-up are enabled at reset. |
| 14 | MTDO | bidirectional | GPIO5/LP_GPIO5 powered by VDDPST1 with JTAG MTDO, FSPIWP, ADC1_CH4 and LP_UART_TXD; input is enabled at and after reset. |
| 15 | GPIO6 | bidirectional | GPIO6/LP_GPIO6 powered by VDDPST1 with FSPICLK and ADC1_CH5; input is enabled at and after reset. |
| 16 | GPIO7 | bidirectional | GPIO powered by VDDPST1 with SDIO_DATA1 and FSPID; it is the strapping pin for JTAG signal source control. |
| 17 | GPIO8 | bidirectional | GPIO powered by VDDPST1 with SDIO_DATA0 and the PAD_COMP0 analog comparator input. |
| 18 | GPIO9 | bidirectional | GPIO powered by VDDPST1 with SDIO_CLK and the PAD_COMP1 analog comparator input. |
| 19 | GPIO10 | bidirectional | GPIO powered by VDDPST1 with SDIO_CMD and FSPICS0; input is enabled at and after reset. |
| 20 | U0TXD | bidirectional | GPIO11 powered by VDDPST1 with UART0 transmit data; input and output are enabled at reset. |
| 21 | U0RXD | bidirectional | GPIO12 powered by VDDPST1 with UART0 receive data; input and weak pull-up are enabled at reset. |
| 22 | GPIO13 | bidirectional | GPIO powered by VDDPST2 with USB_D- (USB Serial/JTAG) and SDIO_DATA3; default drive strength is 40 mA. |
| 23 | GPIO14 | bidirectional | GPIO powered by VDDPST2 with USB_D+ (USB Serial/JTAG) and SDIO_DATA2; default drive strength is 40 mA and the USB pull-up is enabled at reset. |
| 24 | VDDPST2 | power_in | Supply input for the HP digital and part of the analog pin power domains (HP IO). |
| 25 | SPICS1 | bidirectional | GPIO15/SPICS1 powered by VDD_SPI, the chip select (CE#) used to access PSRAM; weak pull-up is enabled at and after reset. |
| 26 | SPICS0 | bidirectional | GPIO16/SPICS0 powered by VDD_SPI, the chip select (CS#) used to access flash; weak pull-up is enabled at and after reset. |
| 27 | SPIQ | bidirectional | GPIO17/SPIQ (MISO/SIO1) powered by VDD_SPI for the SPI0/1 flash/PSRAM bus; weak pull-up is enabled at and after reset. |
| 28 | SPIWP | bidirectional | GPIO18/SPIWP (WP#/SIO2) powered by VDD_SPI for the SPI0/1 flash/PSRAM bus; weak pull-up is enabled at and after reset. |
| 29 | VDD_SPI | power_out | Output supply for off-package flash by default; it can only be used as GPIO19 if the flash is powered externally. |
| 30 | SPIHD | bidirectional | GPIO20/SPIHD (HOLD#/SIO3) powered by VDD_SPI for the SPI0/1 flash/PSRAM bus; weak pull-up is enabled at and after reset. |
| 31 | SPICLK | bidirectional | GPIO21/SPICLK powered by VDD_SPI, the clock for the SPI0/1 flash/PSRAM bus; weak pull-up is enabled at and after reset. |
| 32 | SPID | bidirectional | GPIO22/SPID (MOSI/SIO0) powered by VDD_SPI for the SPI0/1 flash/PSRAM bus; weak pull-up is enabled at and after reset. |
| 33 | GPIO23 | bidirectional | General-purpose IO powered by VDDPST3; input is enabled at reset. |
| 34 | GPIO24 | bidirectional | General-purpose IO powered by VDDPST3; input is enabled at reset. |
| 35 | GPIO25 | bidirectional | General-purpose IO powered by VDDPST3; it is a strapping pin for SDIO sampling and driving clock edge and input is enabled at and after reset. |
| 36 | GPIO26 | bidirectional | General-purpose IO powered by VDDPST3; it is a strapping pin for chip boot mode and input is enabled at and after reset. |
| 37 | GPIO27 | bidirectional | General-purpose IO powered by VDDPST3; it is a strapping pin for boot mode and ROM message printing, with input and weak pull-up enabled at and after reset. |
| 38 | GPIO28 | bidirectional | General-purpose IO powered by VDDPST3; it is a strapping pin for chip boot mode, with input and weak pull-up enabled at reset and after reset (depends on EFUSE_DIS_PAD_JTAG). |
| 39 | VDDPST3 | power_in | Supply input for the HP digital power domain (HP IO). |
| 40 | VDDA1 | power_in | Analog power domain supply input, 3.3 V. |
| 41 | VDDA2 | power_in | Analog power domain supply input, 3.3 V. |
| 42 | ANT_2G | bidirectional | 2.4 GHz RF input/output. |
| 43 | GND | power_in | External ground connection. |
| 44 | VDDA3 | power_in | Analog power domain supply input, 3.3 V. |
| 45 | VDDA4 | power_in | Analog power domain supply input, 3.3 V. |
| 46 | VDDA5 | power_in | Analog power domain supply input, 3.3 V. |
| 47 | GND | power_in | External ground connection. |
| 48 | ANT_5G | bidirectional | 5 GHz RF input/output. |
| 49 | GND | power_in | Exposed ground pad shown in the pin layout figure. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Espressif Systems |
| Package | QFN-48-1EP_6x6mm_P0.4mm_EP4.6x4.6mm |
| Category | RF and Wireless |
| Pins | 49 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input power pins allowed input voltage | -0.3 | 3.6 | V | 70 | |||
| Storage temperature | TSTORE | -40 | 150 | °C | 70 | ||
| Recommended input voltage | VDDA1, VDDA2, VDDA3, VDDA4, VDDA5, VDDA6, VDDA7, VDDA8 | 3 | 3.3 | 3.6 | V | 70 | |
| Recommended input voltage (VDD_SPI as input) | VDD_SPI | 3 | 3.3 | 3.6 | V | 70 | |
| Cumulative input current | IVDD | 0.6 | A | 70 | |||
| High-level input current | IIH | 50 | nA | 71 | |||
| Low-level input current | IIL | 50 | nA | 71 | |||
| Differential nonlinearity | DNL | -5 | 5 | LSB | 72 | ||
| Integral nonlinearity | INL | -5 | 5 | LSB | 72 | ||
| Sampling rate | 2000 | kSPS | 72 | ||||
| Total error | -10 | 10 | mV | ATTEN0, effective measurement range of 0 ~ 1000 | 72 | ||
| Total error | -12 | 12 | mV | ATTEN2, effective measurement range of 0 ~ 1900 | 72 | ||
| Total error | -15 | 15 | mV | ATTEN3, effective measurement range of 0 ~ 3300 | 72 | ||
| Flash power supply voltage (1.8 V) | VCC | 1.65 | 1.8 | 2 | V | 74 | |
| Flash power supply voltage (3.3 V) | VCC | 2.7 | 3.3 | 3.6 | V | 74 | |
| Flash maximum clock frequency | FC | 80 | MHz | 75 | |||
| Flash program/erase cycles | 100000 | cycles | 75 | ||||
| Flash data retention time | TRET | 20 | years | 75 | |||
| Flash page program time | TPP | 0.8 | 5 | ms | 75 | ||
| Flash sector erase time (4 KB) | TSE | 70 | 500 | ms | 75 | ||
| Flash block erase time (32 KB) | TBE1 | 0.2 | 2 | s | 75 | ||
| Flash block erase time (64 KB) | TBE2 | 0.3 | 3 | s | 75 | ||
| Flash chip erase time (16 Mb) | TCE | 7 | 20 | s | 75 | ||
| Flash chip erase time (32 Mb) | TCE | 20 | 60 | s | 75 | ||
| Flash chip erase time (64 Mb) | TCE | 25 | 100 | s | 75 | ||
| Flash chip erase time (128 Mb) | TCE | 60 | 200 | s | 75 | ||
| Flash chip erase time (256 Mb) | TCE | 70 | 300 | s | 75 | ||
| PSRAM power supply voltage (1.8 V) | VCC | 1.62 | 1.8 | 1.98 | V | 75 | |
| PSRAM power supply voltage (3.3 V) | VCC | 2.7 | 3.3 | 3.6 | V | 75 | |
| PSRAM maximum clock frequency | FC | 80 | MHz | 75 |
CAD (KiCad official)
- Symbol:
ESP32-C5HR2 - Footprint:
Package_DFN_QFN:QFN-48-1EP_6x6mm_P0.4mm_EP4.6x4.6mm - 3D model: QFN-48-1EP_6x6mm_P0.4mm_EP4.6x4.6mm, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.9 mm nominal QFN height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files:
esp32-c5hr2-etched.step/esp32-c5hr2-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);esp32-c5hr2.step/esp32-c5hr2.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Espressif Systems datasheet (96 pp, sha256
e3cb7ad57b6fdf16, retrieved 2026-10-29, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).