component
ESP32-C3FH4
Public Made by Adomby adom
Espressif Systems Microcontrollers (MCU/MPU/SOC), QFN-32-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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ESP32-C3FH4
Espressif Systems · Microcontrollers (MCU/MPU/SOC) · QFN-32-EP(5x5)
ESP32-C3FH4 from Espressif Systems, in a QFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | LNA_IN | passive | RF low-noise amplifier input/output signal pin for the 2.4 GHz radio. |
| 2 | VDD3P3 | power_in | Analog power-domain supply; recommended input 3.0 V to 3.6 V (3.3 V typical). |
| 3 | VDD3P3 | power_in | Analog power-domain supply; recommended input 3.0 V to 3.6 V (3.3 V typical). |
| 4 | XTAL_32K_P | bidirectional | Positive terminal for an external 32 kHz passive or active crystal/clock input-output; also selectable as GPIO0 and ADC1_CH0, powered from VDD3P3_RTC. |
| 5 | XTAL_32K_N | bidirectional | Negative terminal for an external 32 kHz passive or active crystal/clock input-output; also selectable as GPIO1 and ADC1_CH1, powered from VDD3P3_RTC. |
| 6 | GPIO2 | bidirectional | General-purpose IO and boot strapping pin (boot mode, with GPIO8/GPIO9); datasheet recommends a pull-up due to pin glitches, default drive 10 mA, also ADC1_CH2 and FSPIQ. |
| 7 | CHIP_EN | input | Chip enable: high level enables (powers up) the chip, low level shuts it down; must not be left floating. |
| 8 | GPIO3 | bidirectional | General-purpose IO with default drive 10 mA; also ADC1_CH3. |
| 9 | MTMS | bidirectional | JTAG test mode select (default function), also GPIO4, ADC1_CH4 and FSPIHD; default drive 10 mA, powered from VDD3P3_RTC. |
| 10 | MTDI | bidirectional | JTAG test data input (default function), also GPIO5, ADC2_CH0 and FSPIWP; default drive 10 mA, powered from VDD3P3_RTC. |
| 11 | VDD3P3_RTC | power_in | Supply for the RTC and part of the digital power domain (RTC IO); recommended 3.0 V to 3.6 V. |
| 12 | MTCK | bidirectional | JTAG test clock (default function), also GPIO6 and FSPICLK; may output a 5 ns low-level glitch at power-up, powered from VDD3P3_CPU. |
| 13 | MTDO | bidirectional | JTAG test data output (default function), also GPIO7 and FSPID; may output a 5 ns low-level glitch at power-up, powered from VDD3P3_CPU. |
| 14 | GPIO8 | bidirectional | General-purpose IO and strapping pin controlling ROM log printing (with EFUSE_UART_PRINT_CONTROL); powered from VDD3P3_CPU. |
| 15 | GPIO9 | bidirectional | General-purpose IO and boot-mode strapping pin with internal weak pull-up enabled at reset; powered from VDD3P3_CPU. |
| 16 | GPIO10 | bidirectional | General-purpose IO (also FSPICS0); may output a 5 ns low-level glitch at power-up, powered from VDD3P3_CPU. |
| 17 | VDD3P3_CPU | power_in | Supply for the digital power domain and digital IO; recommended 3.0 V to 3.6 V, and must not exceed 3.3 V when writing eFuse. |
| 18 | VDD_SPI | power_in | Power pin for the in-package (and optionally external) SPI flash; recommended 3.0 V to 3.6 V as input, and it can be driven from VDD3P3_CPU through an internal resistor (RSPI 7.5 Ω) as output. |
| 19 | SPIHD | bidirectional | SPI flash HOLD# signal for the in-package flash (GPIO12 when not used for flash); connections to flash pins are not recommended for other uses. |
| 20 | SPIWP | bidirectional | SPI flash write-protect (WP#) signal for the in-package flash (GPIO13 when not used for flash). |
| 21 | SPICS0 | bidirectional | SPI flash chip-select (CS#) signal for the in-package flash (GPIO14 when not used for flash); a strapping-related default output function. |
| 22 | SPICLK | bidirectional | SPI flash clock signal for the in-package flash (GPIO15 when not used for flash). |
| 23 | SPID | bidirectional | SPI flash data input (DI) for the in-package flash (GPIO16 when not used for flash). |
| 24 | SPIQ | bidirectional | SPI flash data output (DO) for the in-package flash (GPIO17 when not used for flash). |
| 25 | GPIO18 | bidirectional | General-purpose IO; by default configured as USB_D- for the USB serial/JTAG controller, default drive 40 mA, with a high-level glitch of about 50000 ns at power-up. |
| 26 | GPIO19 | bidirectional | General-purpose IO; by default configured as USB_D+ for the USB serial/JTAG controller, default drive 40 mA. |
| 27 | U0RXD | bidirectional | UART0 receive (default function), also GPIO20; input enabled with weak pull-up at reset and a 5 ns low-level glitch at power-up. |
| 28 | U0TXD | bidirectional | UART0 transmit (default function), also GPIO21; weak pull-up enabled at reset. |
| 29 | XTAL_N | passive | Negative terminal of the external main crystal (passive or active) clock input/output; the chip must have an external main crystal to operate. |
| 30 | XTAL_P | passive | Positive terminal of the external main crystal (passive or active) clock input/output; the chip must have an external main crystal to operate. |
| 31 | VDDA | power_in | Analog power-domain supply; recommended input 3.0 V to 3.6 V (3.3 V typical). |
| 32 | VDDA | power_in | Analog power-domain supply; recommended input 3.0 V to 3.6 V (3.3 V typical). |
| 33 | GND | power_in | Ground reference; the package's exposed thermal pad is connected to external ground. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Espressif Systems |
| Package | QFN-32-EP(5x5) |
| Category | Embedded Processors & Controllers |
| Pins | 33 |
CAD (KiCad official)
- Symbol:
ESP32-C3FH4 - Footprint:
Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm - 3D model: QFN-32-EP(5x5) (KiCad packages3D, STEP)
- 3D model files:
esp32-c3fh4-etched.step/esp32-c3fh4-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);esp32-c3fh4.step/esp32-c3fh4.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Espressif Systems datasheet (65 pp, sha256
85ca330ab81d6967, retrieved 2026-10-09, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# ESP32-C3FH4
**Espressif Systems** · Microcontrollers (MCU/MPU/SOC) · QFN-32-EP(5x5)
ESP32-C3FH4 from Espressif Systems, in a QFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | LNA_IN | passive | RF low-noise amplifier input/output signal pin for the 2.4 GHz radio. |
| 2 | VDD3P3 | power_in | Analog power-domain supply; recommended input 3.0 V to 3.6 V (3.3 V typical). |
| 3 | VDD3P3 | power_in | Analog power-domain supply; recommended input 3.0 V to 3.6 V (3.3 V typical). |
| 4 | XTAL_32K_P | bidirectional | Positive terminal for an external 32 kHz passive or active crystal/clock input-output; also selectable as GPIO0 and ADC1_CH0, powered from VDD3P3_RTC. |
| 5 | XTAL_32K_N | bidirectional | Negative terminal for an external 32 kHz passive or active crystal/clock input-output; also selectable as GPIO1 and ADC1_CH1, powered from VDD3P3_RTC. |
| 6 | GPIO2 | bidirectional | General-purpose IO and boot strapping pin (boot mode, with GPIO8/GPIO9); datasheet recommends a pull-up due to pin glitches, default drive 10 mA, also ADC1_CH2 and FSPIQ. |
| 7 | CHIP_EN | input | Chip enable: high level enables (powers up) the chip, low level shuts it down; must not be left floating. |
| 8 | GPIO3 | bidirectional | General-purpose IO with default drive 10 mA; also ADC1_CH3. |
| 9 | MTMS | bidirectional | JTAG test mode select (default function), also GPIO4, ADC1_CH4 and FSPIHD; default drive 10 mA, powered from VDD3P3_RTC. |
| 10 | MTDI | bidirectional | JTAG test data input (default function), also GPIO5, ADC2_CH0 and FSPIWP; default drive 10 mA, powered from VDD3P3_RTC. |
| 11 | VDD3P3_RTC | power_in | Supply for the RTC and part of the digital power domain (RTC IO); recommended 3.0 V to 3.6 V. |
| 12 | MTCK | bidirectional | JTAG test clock (default function), also GPIO6 and FSPICLK; may output a 5 ns low-level glitch at power-up, powered from VDD3P3_CPU. |
| 13 | MTDO | bidirectional | JTAG test data output (default function), also GPIO7 and FSPID; may output a 5 ns low-level glitch at power-up, powered from VDD3P3_CPU. |
| 14 | GPIO8 | bidirectional | General-purpose IO and strapping pin controlling ROM log printing (with EFUSE_UART_PRINT_CONTROL); powered from VDD3P3_CPU. |
| 15 | GPIO9 | bidirectional | General-purpose IO and boot-mode strapping pin with internal weak pull-up enabled at reset; powered from VDD3P3_CPU. |
| 16 | GPIO10 | bidirectional | General-purpose IO (also FSPICS0); may output a 5 ns low-level glitch at power-up, powered from VDD3P3_CPU. |
| 17 | VDD3P3_CPU | power_in | Supply for the digital power domain and digital IO; recommended 3.0 V to 3.6 V, and must not exceed 3.3 V when writing eFuse. |
| 18 | VDD_SPI | power_in | Power pin for the in-package (and optionally external) SPI flash; recommended 3.0 V to 3.6 V as input, and it can be driven from VDD3P3_CPU through an internal resistor (RSPI 7.5 Ω) as output. |
| 19 | SPIHD | bidirectional | SPI flash HOLD# signal for the in-package flash (GPIO12 when not used for flash); connections to flash pins are not recommended for other uses. |
| 20 | SPIWP | bidirectional | SPI flash write-protect (WP#) signal for the in-package flash (GPIO13 when not used for flash). |
| 21 | SPICS0 | bidirectional | SPI flash chip-select (CS#) signal for the in-package flash (GPIO14 when not used for flash); a strapping-related default output function. |
| 22 | SPICLK | bidirectional | SPI flash clock signal for the in-package flash (GPIO15 when not used for flash). |
| 23 | SPID | bidirectional | SPI flash data input (DI) for the in-package flash (GPIO16 when not used for flash). |
| 24 | SPIQ | bidirectional | SPI flash data output (DO) for the in-package flash (GPIO17 when not used for flash). |
| 25 | GPIO18 | bidirectional | General-purpose IO; by default configured as USB_D- for the USB serial/JTAG controller, default drive 40 mA, with a high-level glitch of about 50000 ns at power-up. |
| 26 | GPIO19 | bidirectional | General-purpose IO; by default configured as USB_D+ for the USB serial/JTAG controller, default drive 40 mA. |
| 27 | U0RXD | bidirectional | UART0 receive (default function), also GPIO20; input enabled with weak pull-up at reset and a 5 ns low-level glitch at power-up. |
| 28 | U0TXD | bidirectional | UART0 transmit (default function), also GPIO21; weak pull-up enabled at reset. |
| 29 | XTAL_N | passive | Negative terminal of the external main crystal (passive or active) clock input/output; the chip must have an external main crystal to operate. |
| 30 | XTAL_P | passive | Positive terminal of the external main crystal (passive or active) clock input/output; the chip must have an external main crystal to operate. |
| 31 | VDDA | power_in | Analog power-domain supply; recommended input 3.0 V to 3.6 V (3.3 V typical). |
| 32 | VDDA | power_in | Analog power-domain supply; recommended input 3.0 V to 3.6 V (3.3 V typical). |
| 33 | GND | power_in | Ground reference; the package's exposed thermal pad is connected to external ground. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Espressif Systems |
| Package | QFN-32-EP(5x5) |
| Category | Embedded Processors & Controllers |
| Pins | 33 |
## CAD (KiCad official)
- Symbol: `ESP32-C3FH4`
- Footprint: `Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm`
- 3D model: QFN-32-EP(5x5) (KiCad packages3D, STEP)
- 3D model files: `esp32-c3fh4-etched.step` / `esp32-c3fh4-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `esp32-c3fh4.step` / `esp32-c3fh4.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Espressif Systems datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588919389660200960) (65 pp, sha256 `85ca330ab81d6967`, retrieved 2026-10-09, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/esp32-c3fh4-datasheet.pdf)