# ESDLC3V3LB

**Leiditech** · ESD And Surge Protection (TVS/ESD) · DFN1006-2

ESDLC3V3LB from Leiditech, in a DFN1006-2. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1 | passive | Terminal 1 of an unpolarised bidirectional ESD/TVS diode; either orientation. |
| 2 | 2 | passive | Terminal 2 of an unpolarised bidirectional ESD/TVS diode; either orientation. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Leiditech |
| Package | DFN1006-2 |
| Category | Circuit Protection |
| Pins | 2 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Breakdown Voltage | VBR | 3.5 |  |  | V | IT = 1mA | 2 |
| Reverse Working Voltage | VRWM |  |  | 3.3 | V |  | 2 |
| Reverse Leakage Current | IR |  |  | 0.5 | µA | VRWM = 3.3V | 2 |
| Clamping Voltage | VC |  |  | 6.5 | V | IPP = 1A (8 x 20 s pulse) | 2 |
| Clamping Voltage | VC |  |  | 10 | V | IPP = 8A (8 x 20 s pulse) | 2 |
| ESD per IEC 61000-4-2 (Air) | VESD | -30 |  | 30 | Kv | Tamb=25°C unless otherwise specified | 1 |
| ESD per IEC 61000-4-2 (Contact) | VESD | -30 |  | 30 | Kv | Tamb=25°C unless otherwise specified | 1 |
| Peak Pulse Power (8/20µs) | Ppp |  |  | 80 | W | 8/20µs, Tamb=25°C unless otherwise specified | 1 |
| Operating Temperature Range | TJ | -55 |  | 125 | ℃ |  | 1 |
| Storage Temperature Range | TSTJ | -55 |  | 150 | ℃ |  | 1 |
| Junction Capacitance | CJ |  | 12 |  | pF | V = 0V, f = 1MHz | 2 |

## CAD (KiCad official)

- Symbol: `ESDLC3V3LB`
- Footprint: `Diode_SMD:D_SOD-882`
- 3D model: DFN1006-2 (KiCad packages3D, STEP)
- 3D model files: `esdlc3v3lb-etched.step` / `esdlc3v3lb-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `esdlc3v3lb.step` / `esdlc3v3lb.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Leiditech datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590261066056822784) (4 pp, sha256 `ed81fd53eebaed6e`, retrieved 2026-10-15, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins`, primary `two-terminal convention` (convention), consensus `off` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/esdlc3v3lb-datasheet.pdf)