# ESDALC6V1P5

**Leiditech** · ESD And Surge Protection (TVS/ESD) · SOT-553

ESDALC6V1P5 from Leiditech, in a SOT-553. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | I/O1 | passive | Protected line 1 of the TVS diode array, connected through its diode pair to the common node at pin 2 (VRWM 5V, 0.5pF typ. capacitance). |
| 2 | GND | power_in | Common/ground node of the TVS array, tied to the center junction of the diode pairs for the ±15kV air / ±8kV contact IEC 61000-4-2 ESD clamp path. |
| 3 | I/O2 | passive | Protected line 2 of the TVS diode array, connected through its diode pair to the common node at pin 2 (VRWM 5V). |
| 4 | I/O3 | passive | Protected line 3 of the TVS diode array, connected through its diode to the common node at pin 2 (VRWM 5V); shares a diode string with pin 3. |
| 5 | I/O4 | passive | Protected line 4 of the TVS diode array, connected through its diode to the common node at pin 2 (VRWM 5V); shares a diode string with pin 1. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Leiditech |
| Package | SOT-553 |
| Category | Circuit Protection |
| Pins | 5 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Reverse stand-off voltage (VRWM) | VRWM |  | 5 |  | V |  | 2 |
| Breakdown voltage (VBR), minimum | VBR | 6 |  |  | V | IT = 1 mA | 2 |
| Clamping voltage (VC) at 1 A, maximum column | VC |  | 9.8 |  | V | @1A | 2 |
| Clamping voltage (Vc), maximum | Vc |  |  | 12 | V |  | 2 |
| Reverse leakage current (IR), maximum | IR |  |  | 5 | μA |  | 2 |
| Capacitance (C), typical | C |  | 0.5 |  | Pf |  | 2 |
| Capacitance (C), maximum | C |  |  | 0.7 | Pf |  | 2 |
| Peak Pulse Power (8/20µs) | Ppp |  |  | 60 | W | 8/20µs | 1 |
| ESD per IEC 61000-4-2 (Air) | VESD | -15 |  | 15 | Kv | IEC 61000-4-2 (Air) | 1 |
| ESD per IEC 61000-4-2 (Contact) | VESD | -8 |  | 8 | Kv | IEC 61000-4-2 (Contact) | 1 |
| Operating Temperature Range | TJ | -55 |  | 125 | ℃ |  | 1 |
| Storage Temperature Range | TSTJ | -55 |  | 150 | ℃ |  | 1 |

## CAD (KiCad official)

- Symbol: `ESDALC6V1P5`
- Footprint: `Package_TO_SOT_SMD:SOT-553`
- 3D model: SOT-553 (KiCad packages3D, STEP)
- 3D model files: `esdalc6v1p5-etched.step` / `esdalc6v1p5-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `esdalc6v1p5.step` / `esdalc6v1p5.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Leiditech datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590224350680428544) (3 pp, sha256 `2dfa7f83b157b7d9`, retrieved 2026-10-17, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text+vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/esdalc6v1p5-datasheet.pdf)