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Name	Last commit message	Last updated
docs	esda14v2sc6: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray	3d ago
viewers	esda14v2sc6: viewers · Ray	6d ago
esda14v2sc6-etched.fit.json	esda14v2sc6: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray	3d ago
esda14v2sc6-etched.glb	esda14v2sc6: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray	3d ago
esda14v2sc6-etched.step	esda14v2sc6: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray	3d ago
esda14v2sc6.glb	Publish 0.1.0 · Ray	6d ago
esda14v2sc6.kicad_mod	Publish 0.1.0 · Ray	6d ago
esda14v2sc6.kicad_sym	Publish 0.1.0 · Ray	6d ago
esda14v2sc6.lbr	Publish 0.1.0 · Ray	6d ago
esda14v2sc6.step	Publish 0.1.0 · Ray	6d ago
package.json	Publish 0.1.0 · Ray	6d ago
page.json	Set visibility: public · Ray	6d ago
README.md	Initial commit: component/esda14v2sc6 · Ray	6d ago

ESDA14V2SC6

STMicroelectronics · ESD And Surge Protection (TVS/ESD) · SOT-23-6L

ESDA14V2SC6 from STMicroelectronics, in a SOT-23-6L. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	IO1	passive	Protected signal line for one of the four unidirectional Transil ESD protection cells, paired internally with pin 6 through a common node (pins 2/5); clamps to VCL max 35 V at IPP 14 A and VBR 14.2-15.8 V for the ESDA14V2SC6 (IRM max 5 µA at VRM 12 V, C typ 100 pF).
2	COM	power_in	Common node pin, internally shorted to pin 5, forming the shared return/ground reference for all four Transil diode pairs in the array (per functional diagram, Figure 2).
3	IO2	passive	Protected signal line for one of the four unidirectional Transil ESD protection cells, paired internally with pin 4 through a common node (pins 2/5); clamps to VCL max 35 V at IPP 14 A and VBR 14.2-15.8 V for the ESDA14V2SC6 (IRM max 5 µA at VRM 12 V, C typ 100 pF).
4	IO3	passive	Protected signal line for one of the four unidirectional Transil ESD protection cells, paired internally with pin 3 through a common node (pins 2/5); clamps to VCL max 35 V at IPP 14 A and VBR 14.2-15.8 V for the ESDA14V2SC6 (IRM max 5 µA at VRM 12 V, C typ 100 pF).
5	COM	power_in	Common node pin, internally shorted to pin 2, forming the shared return/ground reference for all four Transil diode pairs in the array (per functional diagram, Figure 2).
6	IO4	passive	Protected signal line for one of the four unidirectional Transil ESD protection cells, paired internally with pin 1 through a common node (pins 2/5); clamps to VCL max 35 V at IPP 14 A and VBR 14.2-15.8 V for the ESDA14V2SC6 (IRM max 5 µA at VRM 12 V, C typ 100 pF).

Key specifications

Parameter	Value
Manufacturer	STMicroelectronics
Package	SOT-23-6L
Category	Circuit Protection
Pins	6

CAD (KiCad official)

Symbol: ESDA14V2SC6
Footprint: Package_TO_SOT_SMD:SOT-23-6
3D model: SOT-23-6L (KiCad packages3D, STEP)
3D model files: esda14v2sc6-etched.step / esda14v2sc6-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); esda14v2sc6.step / esda14v2sc6.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: STMicroelectronics datasheet (9 pp, sha256 83535cf61c43011c, retrieved 2026-09-29, tier: manufacturer)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF