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ESD5682E12-3

Public Made by Adom

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WILLSEMI Will Semicon ESD And Surge Protection (TVS/ESD), SOT-23. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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ESD5682E12-3

WILLSEMI Will Semicon · ESD And Surge Protection (TVS/ESD) · SOT-23

ESD5682E12-3 from WILLSEMI Will Semicon, in a SOT-23. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 I/O1 passive Protected I/O line 1 of the 2-line uni-directional TVS, rated for a 12 V max reverse stand-off voltage (VRWM) with ±30 kV IEC61000-4-2 contact and air ESD protection.
2 I/O2 passive Protected I/O line 2 of the 2-line uni-directional TVS, rated for a 12 V max reverse stand-off voltage (VRWM) with ±30 kV IEC61000-4-2 contact and air ESD protection.
3 GND power_in Ground reference pin and common return for the two TVS channels.

Key specifications

Parameter Value
Manufacturer WILLSEMI Will Semicon
Package SOT-23
Category Circuit Protection
Pins 3

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Peak pulse power Ppk 450 W tp=8/20μs 2
ESD IEC61000-4-2 air discharge VESD -30 30 kV IEC61000-4-2 air discharge 2
ESD IEC61000-4-2 contact discharge VESD -30 30 kV IEC61000-4-2 contact discharge 2
Junction temperature TJ 125 oC 2
Operating temperature TOP -40 85 oC 2
Lead temperature TL 260 oC 2
Storage temperature TSTG -55 150 oC 2
Reverse stand-off voltage VRWM 12 V 3
Reverse leakage current IR 1 100 nA VRWM = 12V 3
Reverse breakdown voltage VBR 13 15 17 V IBR = 1mA 3
Forward voltage VF 0.45 1.25 V IF = 20mA 3
Clamping voltage (TLP) VCL 18 V IPP = 16A, tp = 100ns 3
Clamping voltage (contact discharge) VCL 19 V VESD = 8kV 3
Clamping voltage (8/20μs) VCL 17.5 V IPP = 1A, tp = 8/20μs 3
Clamping voltage (8/20μs) VCL 26 V IPP = 18A, tp = 8/20μs 3
Dynamic resistance (TLP) RDYN 0.2 Ω TLP, calculated from 4A to 16A (note 1) 3
Junction capacitance, any I/O pin to GND CJ 80 120 pF F = 1MHz, VR = 0V 3
Junction capacitance, between I/O pins CJ 40 60 pF F = 1MHz, VR = 0V 3

CAD (KiCad official)

  • Symbol: ESD5682E12-3
  • Footprint: Package_TO_SOT_SMD:SOT-23
  • 3D model: SOT-23 (KiCad packages3D, STEP)
  • 3D model files: esd5682e12-3-etched.step / esd5682e12-3-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); esd5682e12-3.step / esd5682e12-3.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: WILLSEMI Will Semicon datasheet (6 pp, sha256 3a4fd12d6580dc01, retrieved 2026-10-17, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF