ESD12VS2UT-MS

MSKSEMI · ESD And Surge Protection (TVS/ESD) · SOT-23

ESD12VS2UT-MS from MSKSEMI, in a SOT-23. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	1	passive	Protected line 1 connection of the two-line TVS array, shown in the package diagram as the terminal of one diode, with a 12V maximum working voltage (VRWM) and 13.3V minimum breakdown at 1mA.
2	2	passive	Protected line 2 connection of the two-line TVS array, shown in the package diagram as the terminal of the second diode, with a 12V maximum working voltage (VRWM) and 13.3V minimum breakdown at 1mA.
3	3	passive	Common terminal joining both diodes in the package diagram, shared by lines 1 and 2; the datasheet does not label it as ground or give its function by name.

Key specifications

Parameter	Value
Manufacturer	MSKSEMI
Package	SOT-23
Category	Circuit Protection
Pins	3

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Max	Unit	Conditions	Page
Reverse working voltage (max)	VRWM		12	V		2
Breakdown voltage (min)	VB	13.3		V	IT = 1 mA	2
Clamping voltage at 1 A (max)	VC@1A		19	V	@1A	2
Clamping voltage (max)	VC		32	V	@A column = 11 (A)	2
Reverse leakage current (max)	IR		1	µA		2
Capacitance (max)	CT		130	pF		2
Peak pulse power	PPK		300	Watts	tp = 8/20μs	2
Lead soldering temperature	TL		260	℃	10 sec.	2
Operating temperature	TJ	-55	125	℃		2
Storage temperature	TSTG	-55	150	℃		2

CAD (KiCad official)

Symbol: ESD12VS2UT-MS
Footprint: Package_TO_SOT_SMD:SOT-23
3D model: SOT-23 (KiCad packages3D, STEP)
3D model files: esd12vs2ut-ms-etched.step / esd12vs2ut-ms-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); esd12vs2ut-ms.step / esd12vs2ut-ms.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: MSKSEMI datasheet (5 pp, sha256 4271396bad2a5453, retrieved 2026-10-19, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

# ESD12VS2UT-MS

**MSKSEMI** · ESD And Surge Protection (TVS/ESD) · SOT-23

ESD12VS2UT-MS from MSKSEMI, in a SOT-23. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1 | passive | Protected line 1 connection of the two-line TVS array, shown in the package diagram as the terminal of one diode, with a 12V maximum working voltage (VRWM) and 13.3V minimum breakdown at 1mA. |
| 2 | 2 | passive | Protected line 2 connection of the two-line TVS array, shown in the package diagram as the terminal of the second diode, with a 12V maximum working voltage (VRWM) and 13.3V minimum breakdown at 1mA. |
| 3 | 3 | passive | Common terminal joining both diodes in the package diagram, shared by lines 1 and 2; the datasheet does not label it as ground or give its function by name. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | MSKSEMI |
| Package | SOT-23 |
| Category | Circuit Protection |
| Pins | 3 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Reverse working voltage (max) | VRWM |  |  | 12 | V |  | 2 |
| Breakdown voltage (min) | VB | 13.3 |  |  | V | IT = 1 mA | 2 |
| Clamping voltage at 1 A (max) | VC@1A |  |  | 19 | V | @1A | 2 |
| Clamping voltage (max) | VC |  |  | 32 | V | @A column = 11 (A) | 2 |
| Reverse leakage current (max) | IR |  |  | 1 | µA |  | 2 |
| Capacitance (max) | CT |  |  | 130 | pF |  | 2 |
| Peak pulse power | PPK |  |  | 300 | Watts | tp = 8/20μs | 2 |
| Lead soldering temperature | TL |  |  | 260 | ℃ | 10 sec. | 2 |
| Operating temperature | TJ | -55 |  | 125 | ℃ |  | 2 |
| Storage temperature | TSTG | -55 |  | 150 | ℃ |  | 2 |

## CAD (KiCad official)

- Symbol: `ESD12VS2UT-MS`
- Footprint: `Package_TO_SOT_SMD:SOT-23`
- 3D model: SOT-23 (KiCad packages3D, STEP)
- 3D model files: `esd12vs2ut-ms-etched.step` / `esd12vs2ut-ms-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `esd12vs2ut-ms.step` / `esd12vs2ut-ms.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [MSKSEMI datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590228996714893312) (5 pp, sha256 `4271396bad2a5453`, retrieved 2026-10-19, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text+vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/esd12vs2ut-ms-datasheet.pdf)