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ENC424J600T-I

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Microchip Tech Ethernet ICs, TQFP-44(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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ENC424J600T-I

Microchip Tech · Ethernet ICs · TQFP-44(10x10)

ENC424J600T-I from Microchip Tech, in a TQFP-44(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VSSOSC power_in Ground reference for the 25 MHz oscillator.
2 OSC2 output 25 MHz crystal oscillator output.
3 OSC1 input 25 MHz crystal oscillator / clock input (analog level), needing no more than ±50 ppm total error.
4 VDDOSC power_in Positive 3.3V power supply for the 25 MHz oscillator.
5 AD4 bidirectional PSP multiplexed address input and/or bidirectional data bus bit 4 (CMOS input, 5V tolerant as input).
6 AD5 bidirectional PSP multiplexed address input and/or bidirectional data bus bit 5 (CMOS input, 5V tolerant as input).
7 AD6 bidirectional PSP multiplexed address input and/or bidirectional data bus bit 6 (CMOS input, 5V tolerant as input).
8 AD7 bidirectional PSP multiplexed address input and/or bidirectional data bus bit 7 (CMOS input, 5V tolerant as input).
9 LEDB output Programmable Ethernet status/activity LED output; by default shows PHY-level TX/RX activity.
10 LEDA output Programmable Ethernet status/activity LED output; by default shows Ethernet link status.
11 RBIAS passive PHY bias connection for an external resistor (analog).
12 VDDPLL power_in Positive 3.3V power supply for the PHY PLL circuitry.
13 VSSPLL power_in Ground reference for the PHY PLL circuitry.
14 VSSRX power_in Ground reference for the PHY RX circuitry.
15 VDDRX power_in Positive 3.3V power supply for the PHY RX circuitry.
16 TPIN+ input Differential Ethernet receive plus signal input (analog).
17 TPIN- input Differential Ethernet receive minus signal input (analog).
18 VDDTX power_in Positive 3.3V power supply for the PHY TX circuitry.
19 VSSTX power_in Ground reference for the PHY TX circuitry.
20 TPOUT+ output Differential Ethernet transmit plus signal output.
21 TPOUT- output Differential Ethernet transmit minus signal output.
22 VSSTX power_in Ground reference for the PHY TX circuitry.
23 CLKOUT output Programmable clock output for external use; defaults to 4 MHz after POR.
24 INT/SPISEL bidirectional Active-low interrupt output, multiplexed with the SPI/PSP interface select latched at power-up (needs a pull-up or pull-down resistor of 100 kΩ or smaller, no direct VDD/VSS connection).
25 AD8 bidirectional PSP multiplexed address input and/or bidirectional data bus bit 8 (CMOS input, 5V tolerant as input).
26 AD9 bidirectional PSP multiplexed address input and/or bidirectional data bus bit 9 (CMOS input, 5V tolerant as input).
27 AD10 bidirectional PSP multiplexed address input and/or bidirectional data bus bit 10 (CMOS input, 5V tolerant as input).
28 AD11 bidirectional PSP multiplexed address input and/or bidirectional data bus bit 11 (CMOS input, 5V tolerant as input).
29 AD12 bidirectional PSP multiplexed address input and/or bidirectional data bus bit 12 (CMOS input, 5V tolerant as input).
30 AD13 bidirectional PSP multiplexed address input and/or bidirectional data bus bit 13 (CMOS input, 5V tolerant as input).
31 AD14 bidirectional PSP multiplexed address input and/or bidirectional data bus bit 14 (CMOS input, 5V tolerant as input).
32 PSPCFG0 input PSP mode select 0, latched at power-up: VSS selects PSP Mode 5, VDD selects PSP Mode 6.
33 VSS power_in Ground reference for digital logic.
34 CS input SPI chip select (active-low) or PSP chip select (active-high); internal weak pull-up in SPI mode and pull-down in PSP mode.
35 SO/~{WR}/EN bidirectional SPI serial data output to master (SO), or PSP R/W enable strobe (EN) or write strobe (WR) as an input.
36 SI/RD/RW input SPI serial data input from master (SI), or PSP read strobe (RD) or combined read/write signal (RW); 5V tolerant.
37 SCK/AL input SPI serial clock input (SCK) or PSP address latch (AL); 5V tolerant.
38 AD0 bidirectional PSP multiplexed address input and/or bidirectional data bus bit 0 (CMOS input, 5V tolerant as input).
39 AD1 bidirectional PSP multiplexed address input and/or bidirectional data bus bit 1 (CMOS input, 5V tolerant as input).
40 AD2 bidirectional PSP multiplexed address input and/or bidirectional data bus bit 2 (CMOS input, 5V tolerant as input).
41 AD3 bidirectional PSP multiplexed address input and/or bidirectional data bus bit 3 (CMOS input, 5V tolerant as input).
42 VSS power_in Ground reference for digital logic.
43 VCAP power_in Regulator external capacitor connection.
44 VDD power_in Positive 3.3V power supply for digital logic.

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package TQFP-44(10x10)
Category Interface ICs
Pins 44

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage VDD 3 3.3 3.6 V -40°C ≤ TA ≤ 85°C 145
VDD Start Voltage to Ensure Internal Power-on Reset VPOR 1.75 1.95 V 145
VDD Rise Rate to Ensure Internal Power-on Reset SVDD 0.05 V/ms 145
Input High Voltage, Digital Input Pins (min) VIH 0.6 VDD D004; min printed as 0.6 VDD 145
Input High Voltage, Digital Input Pins (max) VIH 5.5 V D004 145
Input High Voltage, OSC1 Pin VIH 0.7 VDD D005; min printed as 0.7 VDD, max printed as VDD 145
Input Low Voltage, Digital Input Pins VIL 0.2 VDD D006; min printed as VSS, max as 0.2 VDD 145
Input Low Voltage, OSC1 Pin VIL 0.2 VDD D007; min printed as VSS, max as 0.2 VDD 145
Output High Voltage, All Digital Output Pins VOH 2.4 V IOH = -8mA; max printed as VDD 145
Output Low Voltage, All Digital Output Pins VOL 0.4 V IOL = 8mA; min printed as VSS 145
Weak Pull-up Current IWPU -150 -260 -400 μA VDD = 3.3V, VPIN = VSS 145
Weak Pull-Down Current IWPD 28 56 112 μA VDD = 3.3V, VPIN = VDD 145
Input Leakage Current, Digital Input Pins IIL -1 1 μA VSS ≤ VPIN ≤ VDD 145
Input Leakage Current, OSC1 Pin IIL -150 150 μA VSS ≤ VPIN ≤ VDD 145
Supply Current, 100Base-TX Linked, Maximum TX Utilization IDD 96 117 mA Note 1 145
Supply Current, 10Base-T Linked, Maximum TX Utilization IDD 82 103 mA Note 1 145
Supply Current, Not Linked IDD 74 mA Note 1 145
Supply Current, 100Base-TX Linked, Idle IDD 96 mA Note 1 145
Supply Current, 10Base-T Linked, Idle IDD 82 mA Note 1 145
Cryptographic Module Current ΔICT 40 mA EIR<15> = 1 145
TX Transformer Center Tap Current, 100Base-TX Linked ITXCT 30 mA 145
TX Transformer Center Tap Current, 10Base-T Linked ITXCT 80 mA 145
Power-Down Current, Energy Detect Power-Down IPD 29.2 34 mA PHCON2<13> = 1 146
Power-Down Current, Sleep IPD 23.8 28 mA PHCON1<11> = 1 146
Peak Differential Output Voltage, 100Base-TX VTPOUT 0.95 1 1.05 V Note 3 146
Peak Differential Output Voltage, 10Base-T VTPOUT 2.2 2.5 2.8 V Note 3 146
10Base-T RX Differential Squelch Threshold VSQ 160 300 585 mV 146
Regulator Output Voltage VRGOUT 1.62 1.8 1.98 V -40°C < TA < +85°C 146
External Filter Capacitor Value CEFC 4.7 10 μF Capacitor must have low series resistance (< 3Ω) 146
Operating Junction Temperature Range TJ -40 125 °C 144
Operating Ambient Temperature Range TA -40 85 °C 144
Package Thermal Resistance, 44-Pin TQFP (10x10x1 mm) θJA 49.8 °C/W Note 1: package simulation 144
Storage temperature -65 150 °C 143
Ambient temperature under bias -40 85 °C Industrial 143
Voltage on VDD, VDDOSC, VDDPLL, VDDRX, VDDTX -0.3 4 V with respect to VSS 143
Voltage on any digital pin -0.3 6 V with respect to VSS 143
Voltage on OSC1 and RBIAS analog pins -0.3 V with respect to VSS; max printed as VDD + 0.3V 143
Voltage on TPIN+/- and TPOUT+/- -0.3 5 V with respect to VSS 143
Voltage on VCAP -0.3 2 V with respect to all VSS pins 143
ESD protection on all pins 2 kV 143
Clock In Frequency FOSC 25 25 MHz 147
Clock Frequency Error Δf -50 50 ppm 147
Duty Cycle (external clock input) TDUTY 40 60 % 147
CLKOUT Frequency FCLKOUT 33.3 MHz min printed as DC 147
CLKOUT Duty Cycle TDUTY 40 50 60 % All prescaler settings except divide by 12.5 147
CLKOUT Duty Cycle, divide by 12.5 TDUTY 37.5 47.5 57.5 % Divide by 12.5 prescaler 147
CLKOUT Pin Rise Time trCLKOUT 3 ns Note 1: 0.1 VDD to 0.9 VDD, 10 pF load 147
CLKOUT Pin Fall Time tfCLKOUT 4 ns Note 1: 0.1 VDD to 0.9 VDD, 10 pF load 147
CLKOUT Stability (jitter) ΔCLKOUT -0.25 0.25 % 147
SPI Clock Frequency FSCK 14 MHz min printed as DC 148
SCK Duty Cycle TDUTY 45 55 % 148
CS Setup Time TCSS 50 ns 148
CS Hold Time TCSH 50 ns 148
CS Disable Time TCSD 20 ns 148
Data Setup Time TSU 10 ns 148
Data Hold Time THD 10 ns 148
Output Valid from Clock Low TV 10 ns Load on SO pin = 30 pF 148
Output Disable Time TDIS 10 ns Load on SO pin = 30 pF 148
RD, EN, BxSEL to Data Valid TPSP2 75 ns 149

CAD (KiCad official)

  • Symbol: ENC424J600T-I
  • Footprint: Package_QFP:TQFP-44_10x10mm_P0.8mm
  • 3D model: TQFP-44(10x10) (KiCad packages3D, STEP)
  • 3D model files: enc424j600t-i-etched.step / enc424j600t-i-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); enc424j600t-i.step / enc424j600t-i.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (168 pp, sha256 8ebdbf6c80574668, retrieved 2026-10-26, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF