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ENC28J60T
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Microchip Tech Interface - Specialized, SSOP-28-208mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownENC28J60T
Microchip Tech · Interface - Specialized · SSOP-28-208mil
ENC28J60T from Microchip Tech, in a SSOP-28-208mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VCAP | passive | 2.5V output from internal regulator; requires a low-ESR capacitor, typically 10 µF (minimum 1 µF), to ground. |
| 2 | VSS | power_in | Ground reference. |
| 3 | CLKOUT | output | Programmable clock output pin with maximum current capacity of 8 mA. |
| 4 | INT | output | Interrupt output pin with maximum current capacity of 4 mA. |
| 5 | NC | unconnected | Reserved function; always leave unconnected. |
| 6 | SO | output | Data out pin for SPI interface with maximum current capacity of 4 mA. |
| 7 | SI | input | Schmitt trigger data in pin for SPI interface; 5V tolerant. |
| 8 | SCK | input | Schmitt trigger clock in pin for SPI interface; 5V tolerant, up to 20 MHz. |
| 9 | CS | input | Schmitt trigger chip select input for SPI interface; 5V tolerant with internal weak pull-up to VDD. |
| 10 | RESET | input | Active-low device Reset input, Schmitt trigger, 5V tolerant with internal weak pull-up to VDD. |
| 11 | VSSRX | power_in | Ground reference for PHY RX. |
| 12 | TPIN- | input | Differential analog signal input. |
| 13 | TPIN+ | input | Differential analog signal input. |
| 14 | RBIAS | input | PHY bias current pin; must be tied to ground via a 2.32 kΩ, 1% resistor. |
| 15 | VDDTX | power_in | Positive supply for PHY TX. |
| 16 | TPOUT- | output | Differential signal output. |
| 17 | TPOUT+ | output | Differential signal output. |
| 18 | VSSTX | power_in | Ground reference for PHY TX. |
| 19 | VDDRX | power_in | Positive 3.3V supply for PHY RX. |
| 20 | VDDPLL | power_in | Positive 3.3V supply for PHY PLL. |
| 21 | VSSPLL | power_in | Ground reference for PHY PLL. |
| 22 | VSSOSC | power_in | Ground reference for oscillator. |
| 23 | OSC1 | input | Analog oscillator input for the 25 MHz crystal or external clock. |
| 24 | OSC2 | output | Oscillator output. |
| 25 | VDDOSC | power_in | Positive 3.3V supply for oscillator. |
| 26 | LEDB | output | LEDB driver pin with maximum current capacity of 12 mA. |
| 27 | LEDA | output | LEDA driver pin with maximum current capacity of 12 mA. |
| 28 | VDD | power_in | Positive 3.3V supply. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | SSOP-28-208mil |
| Category | Communication Interface Chip/UART/485/232 |
| Pins | 28 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage | VDD | 3.1 | 3.3 | 3.6 | V | 80 | |
| VDD Power-on Reset Voltage | VPOR | 0.7 | V | See Section 11.1 | 80 | ||
| VDD Rise Rate to Ensure Internal POR | SVDD | 0.05 | V/ms | See Section 11.1 | 80 | ||
| Input High Voltage SCK, CS, SI, RESET | VIH | 2.25 | 5.5 | V | 80 | ||
| Input High Voltage OSC1 | VIH | 0.7 | V | Min 0.7 VDD, max VDD (value in VDD units) | 80 | ||
| Input Low Voltage SCK, CS, SI, RESET | VIL | 1 | V | Min VSS | 80 | ||
| Input Low Voltage OSC1 | VIL | 0.3 | V | Max 0.3 VDD (value in VDD units); min VSS | 80 | ||
| Output High Voltage LEDA, LEDB | VOH | -0.7 | V | Min VDD - 0.7; IOH = -12.0 mA (Note 1) | 80 | ||
| Output High Voltage CLKOUT | VOH | -0.7 | V | Min VDD - 0.7; IOH = -8.0 mA (Note 1) | 80 | ||
| Output High Voltage INT, SO | VOH | -0.7 | V | Min VDD - 0.7; IOH = -4.0 mA (Note 1) | 80 | ||
| Output Low Voltage LEDA, LEDB | VOL | 0.4 | V | IOL = 12.0 mA | 80 | ||
| Output Low Voltage CLKOUT | VOL | 0.4 | V | IOL = 8.0 mA | 80 | ||
| Output Low Voltage INT, SO | VOL | 0.4 | V | IOL = 4.0 mA | 80 | ||
| Weak Pull-up Resistance | RPU | 74 | 173 | kΩ | 80 | ||
| Input Leakage Current, all input pins except OSC1 | IIL | -1 | 1 | µA | CS = RESET = VDD, VSS ≤ VPIN ≤ VDD, pins in high-impedance state (Note 1) | 80 | |
| Input Leakage Current, OSC1 pin | IIL | -200 | 200 | µA | OSC1 = VDD (Note 1) | 80 | |
| Operating Current, Transmitting Ethernet Packets | IDD | 160 | 180 | mA | VDD = 3.30V, FSCK = 10 MHz, SO = Open, LEDA and LEDB Open, ECON2 = 0 | 80 | |
| Operating Current, Active, not Transmitting | IDD | 120 | mA | VDD = 3.30V, LEDA and LEDB Open, ECON2 = 0 | 80 | ||
| Standby Current (Sleep mode) | IDDS | 1.2 | 2 | mA | CS = VDD, Inputs tied to VDD or VSS, VDD = 3.3V, TA = 25°C, ECON2 = 1 | 80 | |
| Clock In Frequency | FOSC | 25 | 25 | MHz | 81 | ||
| Clock In Period | TOSC | 40 | 40 | ns | 81 | ||
| Duty Cycle (external clock input) | TDUTY | 40 | 60 | % | 81 | ||
| Clock Tolerance | Δf | 50 | ppm | 81 | |||
| RESET Pin High Time (between Reset events) | trl | 2 | µs | 81 | |||
| RESET Pin Low Time to Trigger Reset | tRSTLOW | 400 | ns | 81 | |||
| CLKOUT Pin High Time | thCLKOUT | 16.5 | ns | TDUTY = 50% (Note 1) | 81 | ||
| CLKOUT Pin Low Time | tlCLKOUT | 16.5 | ns | TDUTY = 50% (Note 1) | 81 | ||
| CLKOUT Pin Rise Time | trCLKOUT | 3 | ns | Measured from 0.1 VDD to 0.9 VDD, Load = 10 pF (Note 1) | 81 | ||
| CLKOUT Pin Fall Time | tfCLKOUT | 4 | ns | Measured from 0.9 VDD to 0.1 VDD, Load = 10 pF (Note 1) | 81 | ||
| Transformer Insertion Loss | 0 | 0.6 | 1.1 | dB | 81 | ||
| Transformer Primary Inductance | 350 | µH | 8 mA bias | 81 | |||
| Transformer Isolation | 1.5 | kV | 81 | ||||
| Differential to Common Mode Rejection | 40 | dB | 0.1 to 10 MHz | 81 | |||
| Transformer Return Loss | -16 | dB | 81 | ||||
| CS Setup Time | TCSS | 50 | ns | 82 | |||
| CS Hold Time, ETH registers and memory buffer | TCSH | 10 | ns | ETH registers and memory buffer | 82 | ||
| CS Hold Time, MAC and MII registers | TCSH | 210 | ns | MAC and MII registers | 82 | ||
| CS Disable Time | TCSD | 50 | ns | 82 | |||
| Data Setup Time | TSU | 10 | ns | 82 | |||
| Data Hold Time | THD | 10 | ns | 82 | |||
| Output Valid from Clock Low | TV | 10 | ns | SO Load = 30 pF | 82 | ||
| Output Disable Time | TDIS | 10 | ns | SO Load = 30 pF | 82 | ||
| Storage temperature | -65 | 150 | °C | 79 | |||
| Ambient temperature under bias (Industrial) | -40 | 85 | °C | Industrial | 79 | ||
| Ambient temperature under bias (Commercial) | 0 | 70 | °C | Commercial | 79 | ||
| Voltage on VDD, VDDOSC, VDDPLL, VDDRX, VDDTX | -0.3 | 3.6 | V | with respect to VSS | 79 | ||
| Voltage on RESET, CS, SCK and SI | -0.3 | 6 | V | with respect to VSS | 79 | ||
| Voltage on CLKOUT, SO, OSC1, OSC2, LEDA, LEDB | -0.3 | V | with respect to VSS; max is VDD + 0.3V | 79 | |||
| Voltage on TPIN+/- and TPOUT+/- | -0.3 | 5 | V | with respect to VSS | 79 | ||
| VCAP with respect to VSS | -0.3 | 2.75 | V | Note 1 | 79 | ||
| ESD protection on all pins | 2 | kV | 79 | ||||
| Current sourced or sunk by LEDA, LEDB | 12 | mA | 79 | ||||
| Current sourced or sunk by CLKOUT | 8 | mA | 79 | ||||
| Current sourced or sunk by INT and SO | 4 | mA | 79 |
CAD (KiCad official)
- Symbol:
ENC28J60T - Footprint:
Package_SO:SSOP-28_5.3x10.2mm_P0.65mm - 3D model: SSOP-28-208mil (KiCad packages3D, STEP)
- 3D model files:
enc28j60t-etched.step/enc28j60t-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);enc28j60t.step/enc28j60t.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (102 pp, sha256
b52e8531a128c759, retrieved 2026-10-30, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).