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ENC28J60

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Microchip Tech Ethernet ICs, SSOP-28-208mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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ENC28J60

Microchip Tech · Ethernet ICs · SSOP-28-208mil

ENC28J60 from Microchip Tech, in a SSOP-28-208mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VCAP power_out 2.5V output from the internal regulator; requires a low-ESR capacitor with a typical value of 10 µF and a minimum of 1 µF to ground on this pin.
2 VSS power_in Ground reference.
3 CLKOUT output Programmable clock output pin with a maximum current capacity of 8 mA.
4 INT output INT interrupt output pin with a maximum current capacity of 4 mA.
5 NC unconnected Reserved function; always leave unconnected.
6 SO output Data out pin for the SPI interface with a maximum current capacity of 4 mA.
7 SI input Data in pin for the SPI interface; Schmitt-trigger input that is 5V tolerant.
8 SCK input Clock in pin for the SPI interface; Schmitt-trigger input that is 5V tolerant, supporting clock speeds up to 20 MHz.
9 CS input Chip select input pin for the SPI interface; Schmitt-trigger input that is 5V tolerant and has an internal weak pull-up to VDD.
10 RESET input Active-low device Reset input; Schmitt-trigger input that is 5V tolerant and has an internal weak pull-up to VDD.
11 VSSRX power_in Ground reference for PHY RX.
12 TPIN- input Differential signal input for the PHY (analog).
13 TPIN+ input Differential signal input for the PHY (analog).
14 RBIAS input Bias current pin for the PHY; must be tied to ground via a 2.32 k, 1% resistor.
15 VDDTX power_in Positive supply for PHY TX.
16 TPOUT- output Differential signal output of the PHY.
17 TPOUT+ output Differential signal output of the PHY.
18 VSSTX power_in Ground reference for PHY TX.
19 VDDRX power_in Positive 3.3V supply for PHY RX.
20 VDDPLL power_in Positive 3.3V supply for PHY PLL.
21 VSSPLL power_in Ground reference for PHY PLL.
22 VSSOSC power_in Ground reference for the oscillator.
23 OSC1 input Oscillator input, designed for a 25 MHz parallel-resonance crystal or an external clock source.
24 OSC2 output Oscillator output, connected to the crystal when one is used.
25 VDDOSC power_in Positive 3.3V supply for the oscillator.
26 LEDB output LEDB driver pin with a maximum current capacity of 12 mA.
27 LEDA output LEDA driver pin with a maximum current capacity of 12 mA.
28 VDD power_in Positive 3.3V supply.

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package SSOP-28-208mil
Category Interface ICs
Pins 28

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Storage temperature -65 150 °C 79
Ambient temperature under bias (Industrial) -40 85 °C Industrial 79
Ambient temperature under bias (Commercial) 0 70 °C Commercial 79
Voltage on VDD, VDDOSC, VDDPLL, VDDRX, VDDTX with respect to VSS -0.3 3.6 V 79
Voltage on RESET, CS, SCK and SI with respect to VSS -0.3 6 V 79
Voltage on TPIN+/- and TPOUT+/- with respect to VSS -0.3 5 V 79
VCAP with respect to VSS -0.3 2.75 V Note 1: VCAP not designed to supply an external load 79
ESD protection on all pins 2 kV 79
Current sourced or sunk by LEDA, LEDB 12 mA 79
Current sourced or sunk by CLKOUT 8 mA 79
Current sourced or sunk by INT and SO 4 mA 79
Ambient temperature, Industrial standard operating range TA -40 85 °C Industrial 80
Ambient temperature, Commercial standard operating range (SSOP only) TA 0 70 °C Commercial 80
VDD Supply Voltage VDD 3.1 3.3 3.6 V 80
VDD Power-on Reset Voltage VPOR 0.7 V See Section 11.1, Power-on Reset (POR) for details 80
VDD Rise Rate to Ensure Internal Power-on Reset Signal SVDD 0.05 V/ms See Section 11.1, Power-on Reset (POR) for details 80
Input High Voltage (SCK, CS, SI, RESET) VIH 2.25 5.5 V 80
Input Low Voltage (SCK, CS, SI, RESET) VIL 1 V 80
Output Low Voltage (LEDA, LEDB) VOL 0.4 V IOL = 12.0 mA 80
Output Low Voltage (CLKOUT) VOL 0.4 V IOL = 8.0 mA 80
Output Low Voltage (INT, SO) VOL 0.4 V IOL = 4.0 mA 80
Weak Pull-up Resistance RPU 74 173 K 80
Input Leakage Current (all input pins except OSC1) IIL -1 1 µA CS = RESET = VDD, VSS ≤ VPIN ≤ VDD, pins in high-impedance state (Note 1) 80
Input Leakage Current (OSC1 pin) IIL -200 200 µA OSC1 = VDD (Note 1) 80
Operating Current, Transmitting Ethernet Packets IDD 160 180 mA VDD = 3.30V, FSCK = 10 MHz, SO = Open, LEDA and LEDB Open, ECON2 = 0 80
Standby Current (Sleep mode) IDDS 1.2 2 mA CS = VDD, Inputs tied to VDD or VSS, VDD = 3.3V, TA = 25°C, ECON2 = 1 80
Operating Current, Active, not Transmitting Ethernet Packets IDD 120 mA VDD = 3.30V, LEDA and LEDB Open, ECON2 = 0 80
FOSC Clock In Frequency FOSC 25 25 MHz 81
TOSC Clock In Period TOSC 40 40 ns 81
TDUTY Duty Cycle (external clock input) TDUTY 40 60 % external clock input 81
Clock Tolerance f 50 ppm 81
RESET Pin High Time (between Reset events) trl 2 s between Reset events 81
RESET Pin Low Time to Trigger Reset tRSTLOW 400 ns 81
CLKOUT Pin High Time thCLKOUT 16.5 ns TDUTY = 50% (Note 1) 81
CLKOUT Pin Low Time tlCLKOUT 16.5 ns TDUTY = 50% (Note 1) 81
CLKOUT Pin Rise Time trCLKOUT 3 ns Measured from 0.1 VDD to 0.9 VDD, Load = 10 pF (Note 1) 81
CLKOUT Pin Fall Time tfCLKOUT 4 ns Measured from 0.9 VDD to 0.1 VDD, Load = 10 pF (Note 1) 81
Insertion Loss (external magnetics requirement) 0 0.6 1.1 dB 81
Primary Inductance (external magnetics requirement) 350 µH 8 mA bias 81
Differential to Common Mode Rejection (external magnetics requirement) 40 dB 0.1 to 10 MHz 81
Return Loss (external magnetics requirement) -16 dB 81
Transformer Isolation (external magnetics requirement) 1.5 kV 81
Clock Frequency (SPI) FSCK 20 MHz 82
CS Setup Time 1TCSS 50 ns 82
CS Hold Time (ETH registers and memory buffer) 2TCSH 10 ns ETH registers and memory buffer 82
CS Hold Time (MAC and MII registers) 2TCSH 210 ns MAC and MII registers 82
CS Disable Time 3TCSD 50 ns 82
Data Setup Time 4TSU 10 ns 82
Data Hold Time 5THD 10 ns 82
Output Valid from Clock Low 6TV 10 ns SO Load = 30 pF 82
Output Disable Time 7TDIS 10 ns SO Load = 30 pF 82

CAD (KiCad official)

  • Symbol: ENC28J60
  • Footprint: Package_SO:SSOP-28_5.3x10.2mm_P0.65mm
  • 3D model: SSOP-28-208mil (KiCad packages3D, STEP)
  • 3D model files: enc28j60-etched.step / enc28j60-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); enc28j60.step / enc28j60.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (102 pp, sha256 b52e8531a128c759, retrieved 2026-10-29, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF