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EL7156CSZ-T7

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RENESAS Gate Drivers, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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EL7156CSZ-T7

RENESAS · Gate Drivers · SOIC-8

EL7156CSZ-T7 from RENESAS, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VS+ power_in Positive supply voltage; the datasheet operating range is 4.5V to 16.5V with an absolute maximum of +18V (VS+ to VS-).
2 OE input Output enable; when OE is driven active low the output is placed in three-state mode and both output switches open.
3 IN input Logic input that selects the output level (IN=0 connects VH to OUT, IN=1 connects VL to OUT when OE is high), with VIH minimum 2.4V and VIL maximum 0.8V at VS+ = 15V.
4 GND power_in Ground reference; VS- must be between -5V and 0V relative to GND, and all voltages are referenced to it.
5 VS- power_in Negative supply voltage; VS+ to VS- must be 5V to 16.5V per the operating voltage range table.
6 VL power_in Lower output voltage input, an independent input that must remain below VH (VL to VS- range 0V to 16.5V) to avoid turning on the output body diode.
7 OUT output Output that drives VH or VL depending on IN; continuous output current is limited to 200mA with 3.5A peak drive.
8 VH power_in High output voltage input, which must be greater than VL and has a VS+ to VH range of 0V to 16.5V.

Key specifications

Parameter Value
Manufacturer RENESAS
Package SOIC-8
Category Motor Driver ICs
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage (VS+ to VS-) 18 V 2
Continuous Output Current 200 mA 2
Storage Temperature Range -65 150 °C 2
Ambient Operating Temperature -40 85 °C 2
Operating Junction Temperature 125 °C 2
VS- to GND -5 0 V 6
VS+ to VS- 5 16.5 V 6
VH to VL 0 16.5 V 6
VS+ to VH 0 16.5 V 6
VS+ to GND 5 16.5 V 6
VL to VS- 0 16.5 V 6
Logic '1' Input Voltage (VS+=15V set) VIH 2.4 V VS+ = +15V, VH = +15V, VL = 0V, VS- = 0V, TA = +25°C 2
Logic '0' Input Voltage (VS+=15V set) VIL 0.8 V VS+ = +15V, VH = +15V, VL = 0V, VS- = 0V, TA = +25°C 2
Logic '1' Input Current (VS+=15V set) IIH 0.1 10 µA VS+ = +15V, VH = +15V, VL = 0V, VS- = 0V, TA = +25°C; VIH = VS+ 2
Logic '0' Input Current (VS+=15V set) IIL 0.1 10 µA VS+ = +15V, VH = +15V, VL = 0V, VS- = 0V, TA = +25°C; VIL = 0V 2
ON-Resistance VH to OUT (VS+=15V set) ROVH 2.7 4.5 Ω VS+ = +15V, VH = +15V, VL = 0V, VS- = 0V, TA = +25°C; IOUT = -200 mA 2
ON-Resistance VL to OUT (VS+=15V set) ROVL 3.5 5.5 Ω VS+ = +15V, VH = +15V, VL = 0V, VS- = 0V, TA = +25°C; IOUT = +200 mA 2
Output Leakage Current (VS+=15V set) IOUT 0.1 10 µA VS+ = +15V, VH = +15V, VL = 0V, VS- = 0V, TA = +25°C; OE = 0V, OUT = VH/VL 2
Power Supply Current (VS+=15V set) IS 1.3 3 mA VS+ = +15V, VH = +15V, VL = 0V, VS- = 0V, TA = +25°C; Inputs = VS+ 2
Off Leakage at VH and VL (VS+=15V set) IVH 4 10 µA VS+ = +15V, VH = +15V, VL = 0V, VS- = 0V, TA = +25°C; VH, VL = 0V 2
Logic '1' Input Voltage (VS+=5V set) VIH 2 V VS+ = +5V, VH = +5V, VL = -5V, VS- = -5V, TA = +25°C 3
Logic '0' Input Voltage (VS+=5V set) VIL 0.8 V VS+ = +5V, VH = +5V, VL = -5V, VS- = -5V, TA = +25°C 3
Logic '1' Input Current (VS+=5V set) IIH 0.1 10 µA VS+ = +5V, VH = +5V, VL = -5V, VS- = -5V, TA = +25°C; VIH = VS+ 3
Logic '0' Input Current (VS+=5V set) IIL 0.1 10 µA VS+ = +5V, VH = +5V, VL = -5V, VS- = -5V, TA = +25°C; VIL = 0V 3
ON-Resistance VH to OUT (VS+=5V set) ROVH 3.4 5 Ω VS+ = +5V, VH = +5V, VL = -5V, VS- = -5V, TA = +25°C; IOUT = -200mA 3
ON-Resistance VL to OUT (VS+=5V set) ROVL 4 6 Ω VS+ = +5V, VH = +5V, VL = -5V, VS- = -5V, TA = +25°C; IOUT = +200mA 3
Output Leakage Current (VS+=5V set) IOUT 0.1 10 µA VS+ = +5V, VH = +5V, VL = -5V, VS- = -5V, TA = +25°C; OE = 0V, OUT = VH/VL 3
Power Supply Current (VS+=5V set) IS 1 2.5 mA VS+ = +5V, VH = +5V, VL = -5V, VS- = -5V, TA = +25°C; Inputs = VS+ 3
Off Leakage at VH and VL (VS+=5V set) VH 4 10 µA VS+ = +5V, VH = +5V, VL = -5V, VS- = -5V, TA = +25°C; VH, VL = 0V 3
Input Capacitance (VS+=15V set) CIN 3.5 pF VS+ = +15V, VH = +15V, VL = 0V, VS- = 0V, TA = +25°C 2
Input Resistance (VS+=15V set) RIN 50 MΩ VS+ = +15V, VH = +15V, VL = 0V, VS- = 0V, TA = +25°C 2
Peak Output Current (linear resistive operation), Source (VS+=15V set) IPK 3.5 A VS+ = +15V, VH = +15V, VL = 0V, VS- = 0V, TA = +25°C; linear resistive operation 2
Peak Output Current (linear resistive operation), Sink (VS+=15V set) IPK 3.5 A VS+ = +15V, VH = +15V, VL = 0V, VS- = 0V, TA = +25°C; linear resistive operation 2
Continuous Output Current, Source/Sink (VS+=15V set) IDC 200 mA VS+ = +15V, VH = +15V, VL = 0V, VS- = 0V, TA = +25°C; Source/Sink 2
Rise Time (VS+=15V set) tR 14.5 ns VS+ = +15V, VH = +15V, VL = 0V, VS- = 0V, TA = +25°C; CL = 2000pF 2
Fall Time (VS+=15V set) tF 15 ns VS+ = +15V, VH = +15V, VL = 0V, VS- = 0V, TA = +25°C; CL = 2000pF 2
tR, tF Mismatch (VS+=15V set) tRF 0.5 ns VS+ = +15V, VH = +15V, VL = 0V, VS- = 0V, TA = +25°C; CL = 2000pF 2
Turn-Off Delay Time (VS+=15V set) td-1 9.5 ns VS+ = +15V, VH = +15V, VL = 0V, VS- = 0V, TA = +25°C; CL = 2000pF 2
Turn-On Delay Time (VS+=15V set) td-2 10 ns VS+ = +15V, VH = +15V, VL = 0V, VS- = 0V, TA = +25°C; CL = 2000pF 2
td-1-td-2 Mismatch (VS+=15V set) td 0.5 ns VS+ = +15V, VH = +15V, VL = 0V, VS- = 0V, TA = +25°C; CL = 2000pF 2
Three-state Delay Enable (VS+=15V set) td-3 10 ns VS+ = +15V, VH = +15V, VL = 0V, VS- = 0V, TA = +25°C 2
Three-state Delay Disable (VS+=15V set) td-4 10 ns VS+ = +15V, VH = +15V, VL = 0V, VS- = 0V, TA = +25°C 2
Input Capacitance (VS+=5V set) CIN 3.5 pF VS+ = +5V, VH = +5V, VL = -5V, VS- = -5V, TA = +25°C 3
Input Resistance (VS+=5V set) RIN 50 MΩ VS+ = +5V, VH = +5V, VL = -5V, VS- = -5V, TA = +25°C 3
Peak Output Current (linear resistive operation), Source (VS+=5V set) IPK 3.5 A VS+ = +5V, VH = +5V, VL = -5V, VS- = -5V, TA = +25°C; linear resistive operation 3
Peak Output Current (linear resistive operation), Sink (VS+=5V set) IPK 3.5 A VS+ = +5V, VH = +5V, VL = -5V, VS- = -5V, TA = +25°C; linear resistive operation 3
Continuous Output Current, Source/Sink (VS+=5V set) IDC 200 mA VS+ = +5V, VH = +5V, VL = -5V, VS- = -5V, TA = +25°C; Source/Sink 3
Rise Time (VS+=5V set) tR 17 ns VS+ = +5V, VH = +5V, VL = -5V, VS- = -5V, TA = +25°C; CL = 2000pF 3
Fall Time (VS+=5V set) tF 17 ns VS+ = +5V, VH = +5V, VL = -5V, VS- = -5V, TA = +25°C; CL = 2000pF 3
tR, tF Mismatch (VS+=5V set) tRF 0 ns VS+ = +5V, VH = +5V, VL = -5V, VS- = -5V, TA = +25°C; CL = 2000pF 3
Turn-Off Delay Time (VS+=5V set) td-1 11.5 ns VS+ = +5V, VH = +5V, VL = -5V, VS- = -5V, TA = +25°C; CL = 2000pF 3
Turn-On Delay Time (VS+=5V set) td-2 12 ns VS+ = +5V, VH = +5V, VL = -5V, VS- = -5V, TA = +25°C; CL = 2000pF 3
td-1-td-2 Mismatch (VS+=5V set) td 0.5 ns VS+ = +5V, VH = +5V, VL = -5V, VS- = -5V, TA = +25°C; CL = 2000pF 3
Three-state Delay Enable (VS+=5V set) td-3 10 ns VS+ = +5V, VH = +5V, VL = -5V, VS- = -5V, TA = +25°C 3
Three-state Delay Disable (VS+=5V set) td-4 10 ns VS+ = +5V, VH = +5V, VL = -5V, VS- = -5V, TA = +25°C 3
Thermal resistance, junction to ambient (SOIC8) θJA 160 °C/W SOIC8 package, standard JEDEC JESD51-3 single-layer test board 8

CAD (KiCad official)

  • Symbol: EL7156CSZ-T7
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: el7156csz-t7-etched.step / el7156csz-t7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); el7156csz-t7.step / el7156csz-t7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: RENESAS datasheet (11 pp, sha256 a690221999699fd2, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF