component

EL7155CSZ

Public Made by Adom

by adom

RENESAS Pre-ordered Chips, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentinterface icsel7155cszfactory-2.0.0extractor-text

Verified EL7155CSZ

by Ray · last 30 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

30 Oct 2026RayPublished by the parts factory: tier mfr, 8 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: EL7155CSZ · SOIC-8 · 8 pins
  • ✓copper: 8 copper pads, none touching another net
  • ✓datasheet: all 8 pin names found in the 10-page datasheet
  • ✓distributor: lcsc C1549341, digikey EL7155CSZ-ND, mouser 968-EL7155CSZ
  • ✓family: SOIC-8_3.9x4.9mm_P1.27mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-bl4uifhp/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height and body within the datasheet's package drawing (datasheet p.10)
  • ✓pads: 8 pins = 8 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 8 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ el7155csz.kicad_sym✓ el7155csz.kicad_mod✓ el7155csz.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 10d ago
viewers el7155csz: viewers · Ray 10d ago
el7155csz-etched.glb Publish 0.1.0 · Ray 10d ago
el7155csz-etched.step el7155csz: factory component page (tier=mfr) · Ray 10d ago
el7155csz-hero.glb el7155csz: hero GLB from the etched model (keeps the MPN mark) · Ray 10d ago
el7155csz-hero.overlay.json Publish 0.1.0 · Ray 10d ago
el7155csz.glb Publish 0.1.0 · Ray 10d ago
el7155csz.kicad_mod Publish 0.1.0 · Ray 10d ago
el7155csz.kicad_sym Publish 0.1.0 · Ray 10d ago
el7155csz.lbr Publish 0.1.0 · Ray 10d ago
el7155csz.step Publish 0.1.0 · Ray 10d ago
package.json Publish 0.1.0 · Ray 10d ago
page.json Set visibility: public · Ray 10d ago
README.md Publish 0.1.0 · Ray 10d ago
verification.json Verified: Published by the parts factory: tier mfr, 8 pins · Ray 10d ago

EL7155CSZ

RENESAS · Pre-ordered Chips · SOIC-8

EL7155CSZ from RENESAS, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VS+ power_in Positive supply voltage; Table 2 limits VS+ to GND to 5 V to 16.5 V and VS+ to VL to 5 V to 16.5 V.
2 OE input Output enable; when OE is low, both output switches are opened and both outputs are in 3-state.
3 IN input Input reference that selects which output switch closes when OE is high; logic '1' input voltage is 2.4 V minimum and logic '0' input voltage is 0.8 V maximum at VS+ = 15 V.
4 GND power_in Ground reference; VL must be connected to a voltage equal to or lower than GND, and Table 2 gives VL to GND as -5 V to 0 V.
5 VL power_in Negative supply and lower output voltage; it must be at or below GND, with VL to GND limited to -5 V to 0 V per Table 2.
6 OUTL tri_state Lower switch output that connects to VL when OE and IN are both high; continuous output current is limited to 200 mA.
7 OUTH tri_state Upper switch output that connects to VH when OE is high and IN is low; continuous output current is limited to 200 mA and peak drive is 3.5 A.
8 VH power_in Upper output voltage; it may be set to any voltage between VL and VS+, with VH to VL limited to 0 V to 16.5 V per Table 2.

Key specifications

Parameter Value
Manufacturer RENESAS
Package SOIC-8
Category Interface ICs
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Logic '1' Input Voltage (VS+=15V table) VIH 2.4 V VS+=+15V, VH=+15V, VL=0V, TA=+25°C 3
Logic '0' Input Voltage (VS+=15V table) VIL 0.8 V VS+=+15V, VH=+15V, VL=0V, TA=+25°C 3
Logic '1' Input Current (VS+=15V table) IIH 0.1 10 µA VS+=+15V, VH=+15V, VL=0V; VIH = VS+ 3
Logic '0' Input Current (VS+=15V table) IIL 0.1 10 µA VS+=+15V, VH=+15V, VL=0V; VIL = 0V 3
ON-Resistance VH to OUTH (VS+=15V table) ROVH 2.7 4.5 Ω VS+=+15V, VH=+15V, VL=0V; IOUT = -200mA 3
ON-Resistance VL to OUTL (VS+=15V table) ROVL 3.5 5.5 Ω VS+=+15V, VH=+15V, VL=0V; IOUT = +200mA 3
Output Leakage Current (VS+=15V table) IOUT 0.1 10 µA VS+=+15V, VH=+15V, VL=0V; OE = 0V, OUTH = VL, OUTL = VS+ 3
Peak Output Current, Source (linear resistive operation) (VS+=15V table) IPK 3.5 A VS+=+15V, VH=+15V, VL=0V; Source 3
Peak Output Current, Sink (linear resistive operation) (VS+=15V table) IPK 3.5 A VS+=+15V, VH=+15V, VL=0V; Sink 3
Power Supply Current (VS+=15V table) IS 1.3 3 mA VS+=+15V, VH=+15V, VL=0V; Inputs = VS+ 3
Off Leakage at VH (VS+=15V table) IVH 4 10 µA VS+=+15V, VH=+15V, VL=0V; VH = 0V 3
Logic '1' Input Voltage (VS+=5V table) VIH 2 V VS+=+5V, VH=+5V, VL=-5V, TA=+25°C 4
Logic '0' Input Voltage (VS+=5V table) VIL 0.8 V VS+=+5V, VH=+5V, VL=-5V, TA=+25°C 4
Logic '1' Input Current (VS+=5V table) IIH 0.1 10 µA VS+=+5V, VH=+5V, VL=-5V; VIH = VS+ 4
Logic '0' Input Current (VS+=5V table) IIL 0.1 10 µA VS+=+5V, VH=+5V, VL=-5V; VIL = 0V 4
ON-Resistance VH to OUTH (VS+=5V table) ROVH 3.4 5 Ω VS+=+5V, VH=+5V, VL=-5V; IOUT = -200mA 4
ON-Resistance VL to OUTL (VS+=5V table) ROVL 4 6 Ω VS+=+5V, VH=+5V, VL=-5V; IOUT = +200mA 4
Output Leakage Current (VS+=5V table) IOUT 0.1 10 µA VS+=+5V, VH=+5V, VL=-5V; OE = 0V, OUTH = VL, OUTL = VS+ 4
Peak Output Current, Source (linear resistive operation) (VS+=5V table) IPK 3.5 A VS+=+5V, VH=+5V, VL=-5V; Source 4
Peak Output Current, Sink (linear resistive operation) (VS+=5V table) IPK 3.5 A VS+=+5V, VH=+5V, VL=-5V; Sink 4
Power Supply Current (VS+=5V table) IS 1 2.5 mA VS+=+5V, VH=+5V, VL=-5V; Inputs = VS+ 4
Off Leakage at VH (VS+=5V table) IVH 4 10 µA VS+=+5V, VH=+5V, VL=-5V; VH = 0V 4
VL - GND operating voltage range VL - GND -5 0 V Table 2, Operating Voltage Range 7
VS+ - VL operating voltage range VS+ - VL 5 16.5 V Table 2, Operating Voltage Range 7
VH - VL operating voltage range VH - VL 0 16.5 V Table 2, Operating Voltage Range 7
VS+ - VH operating voltage range VS+ - VH 0 16.5 V Table 2, Operating Voltage Range 7
VS+ - GND operating voltage range VS+ - GND 5 16.5 V Table 2, Operating Voltage Range 7
Supply Voltage (VS+ to VL) absolute maximum VS+ - VL 18 V TA = +25°C 3
Continuous Output Current IDC 200 mA TA = +25°C 3
Storage Temperature Range TSTG -65 150 °C 3
Ambient Operating Temperature TA -40 85 °C 3
Operating Junction Temperature TJ 125 °C 3
Thermal resistance junction to ambient, SO8 package θJA 160 °C/W JEDEC JESD51-3 single-layer test board 8

CAD (KiCad official)

  • Symbol: EL7155CSZ
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: el7155csz-etched.step / el7155csz-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); el7155csz.step / el7155csz.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: RENESAS datasheet (10 pp, sha256 e65c73c71a7f7a7c, retrieved 2026-10-30, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF