EL4543IUZ-T7 from RENESAS, in a QSOP-24. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	EN	input	Enable input that disables the video inputs and outputs; its threshold is a linear function of the supply voltage and is TTL/CMOS compatible.
2	VINA+	input	Non-inverting input of channel A, with a common-mode input range from 0V to 2.3V on a 0V to 5V supply.
3	VINA-	input	Inverting input of channel A, which should be kept close to the feedback network to minimize capacitance to ground.
4	NC	unconnected	Not connected.
5	VSYNC	input	Vertical sync logic input, with VLO max 0.8V and VHI min 2V at a +5V supply.
6	HSYNC	input	Horizontal sync logic input, with VLO max 0.8V and VHI min 2V at a +5V supply.
7	NC	unconnected	Not connected.
8	VINB+	input	Non-inverting input of channel B, with a common-mode input range from 0V to 2.3V on a 0V to 5V supply.
9	VINB-	input	Inverting input of channel B, which should be kept close to the feedback network to minimize capacitance to ground.
10	NC	unconnected	Not connected.
11	VINC+	input	Non-inverting input of channel C, with a common-mode input range from 0V to 2.3V on a 0V to 5V supply.
12	VINC-	input	Inverting input of channel C, which should be kept close to the feedback network to minimize capacitance to ground.
13	NC	unconnected	Not connected.
14	VOUTC-	output	Inverting output of channel C, forming the negative leg of the differential output pair.
15	VOUTC+	output	Non-inverting output of channel C, forming the positive leg of the differential output pair; output current should not exceed 60mA for reliability.
16	NC	unconnected	Not connected.
17	VOUTB-	output	Inverting output of channel B, forming the negative leg of the differential output pair.
18	VOUTB+	output	Non-inverting output of channel B, forming the positive leg of the differential output pair; output current should not exceed 60mA for reliability.
19	NC	unconnected	Not connected.
20	VS-	power_in	Negative supply pin; the input logic thresholds are referenced to this pin.
21	VS+	power_in	Positive supply pin; single supply operation from 5V to 12V is specified.
22	NC	unconnected	Not connected.
23	VOUTA-	output	Channel A output on the negative leg of the differential pair; the datasheet description column labels this pin non-inverting, which conflicts with its name.
24	VOUTA+	output	Channel A output on the positive leg of the differential pair; the datasheet description column labels this pin inverting, which conflicts with its name.

Key specifications

Parameter	Value
Manufacturer	RENESAS
Package	QSOP-24
Category	Amplifiers
Pins	24

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Input Referred Offset Voltage	VOS	-10	2	10	mV		3
Input Bias Current (VIN+, VIN+)	IIN	-30	-15	-10	µA		3
Differential Input Range	VDIFF	-0.75		0.75	V		3
Input Common Mode Voltage Range	VCM	0		2.3	V	VS+ = +5V, VS- = 0V	3
Input Common Mode Rejection Ratio	CMRR	60	80		dB	VCM = 0 to 2V	3
Differential Slew Rate	SR	600		1000	V/µs	RL = 200	3
Output Peak Current	IOUT	40	60		mA		3
Voltage Gain	AV	1.82	1.96	2.05	V/V	VIN = 0.8VP-P	3
Supply Operating Range	VSUPPLY	5		12	V	VS+ to VS-	3
Power Supply Current (per Channel)	IS	12.3	14.5	16.2	mA		3
Power Supply Rejection Ratio	PSRR	70	80		dB		3
Supply Voltage (VS+ & VS-)				12	V		3
Maximum Output Continuous Current		-70		70	mA		3
Storage Temperature Range		-65		150	°C		3
Operating Junction Temperature				135	°C		3
Ambient Operating Temperature		-40		85	°C		3
VIN- - VINB differential input voltage		-5		5	V		3
Maximum junction temperature for reliable operation	TJMAX			125	°C		13
Thermal resistance junction to ambient, QSOP24 (JEDEC JESD51-7 high effective thermal conductivity board)	JA		88		°C/W	JEDEC JESD51-7 high effective thermal conductivity test board	10
Thermal resistance junction to ambient, QSOP24 (JEDEC JESD51-3 low effective thermal conductivity board)	JA		115		°C/W	JEDEC JESD51-3 low effective thermal conductivity test board	10

CAD (KiCad official)

Symbol: EL4543IUZ-T7
Footprint: Package_SO:QSOP-24_3.9x8.7mm_P0.635mm
3D model: QSOP-24 (KiCad packages3D, STEP)
3D model files: el4543iuz-t7-etched.step / el4543iuz-t7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); el4543iuz-t7.step / el4543iuz-t7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: RENESAS datasheet (18 pp, sha256 f6b2b1582c54b00b, retrieved 2026-11-02, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

EL4543IUZ-T7

Verified EL4543IUZ-T7

Verification log 1 record

3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

README