EL1881CSZ from RENESAS, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	Composite Sync Out	output	Composite sync pulse output; sync pulses start on a falling edge and end on a rising edge.
2	Composite Video In	input	AC coupled composite video input; sync tip must be at the lowest potential (positive picture phase), with C1 nominally 0.1µF and the clamp charge current limiting the signal to about 1.5V sync tip reference.
3	Vertical Sync Out	output	Vertical sync pulse output; the falling edge of vertical sync is the start of the vertical period.
4	GND	power_in	Supply ground.
5	Burst/Back Porch Output	output	Burst/back porch output; low during burst portion of composite video.
6	RSET	passive	An external 1% resistor to ground sets all internal timing; a 681k 1% resistor provides correct timing for NTSC signals.
7	Odd/Even Output	output	Odd/even field output; high during odd fields, low during even fields, with transitions at the start of the vertical sync pulse.
8	VDD 5V	power_in	Positive supply, 5V (single +5V supply; absolute maximum VCC is 7V per the absolute maximum ratings).

Key specifications

Parameter	Value
Manufacturer	RENESAS
Package	SOIC-8
Category	Interface ICs
Pins	8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Quiescent supply current	IDD	0.75	1.5	3	mA	VDD = 5V	3
Clamp voltage		1.35	1.5	1.65	V	Pin 2, ILOAD = -100µA	3
Clamp discharge current		6	12	16	µA	Pin 2 = 2V	3
Clamp charge current		-1.3	-1	0.7	mA	Pin 2 = 1V	3
RSET pin reference voltage		1.1	1.22	1.35	V	Pin 6	3
Output low voltage	VOL	0.24		0.5	V	IOL = 1.6mA	3
Output high voltage	VOH	4		4.8	V	IOH = -40µA	3
Output high voltage	VOH	3		4.6	V	IOH = -1.6mA	3
Composite sync propagation delay	tCS	20	35	75	ns	See Figure 20	3
Vertical sync width	tVS	190	230	300	µs	Normal or Default Trigger, 50% to 50%	3
Vertical sync default delay	tVSD	35	62	85	µs	See Figure 21	3
Burst/back porch delay	tBD	120	200	300	ns	See Figure 20	3
Burst/back porch width	tB	2.5	3.5	4.5	µs	See Figure 20	3
Input dynamic range		0.5		2	VP-P	Video input amplitude to maintain 50% slice spec	3
Slice level	VSLICE/VCLAMP	55	70	85	mV		3
Pin voltages		-0.5			V	Upper limit printed as VCC +0.5V	3
Storage temperature		-65		150	°C		3
Operating junction temperature				150	°C		3
Power dissipation				400	mW		3
Operating ambient temperature range		-40		85	°C		3
Thermal resistance, junction to ambient, 8 Lead SOIC	θJA	95		120	°C/W	Typical, Note 5: component mounted on high effective thermal conductivity test board in free air	3

CAD (KiCad official)

Symbol: EL1881CSZ
Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
3D model: SOIC-8 (KiCad packages3D, STEP)
3D model files: el1881csz-etched.step / el1881csz-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); el1881csz.step / el1881csz.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: RENESAS datasheet (13 pp, sha256 12fe642040666d80, retrieved 2026-10-30, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

EL1881CSZ

Changed since verified EL1881CSZ

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3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

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