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EG3525S

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EG Micro AC-DC Controllers And Regulators, SOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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EG3525S

EG Micro · AC-DC Controllers And Regulators · SOP-16

EG3525S from EG Micro, in a SOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 INA- input Inverting input of the error amplifier, where the feedback signal is applied, with a common-mode input range of 1.5 V to 5.2 V.
2 INA+ input Non-inverting input of the error amplifier, which is tied to the reference voltage, with a common-mode input range of 1.5 V to 5.2 V.
3 SYNC input External oscillator synchronization input that locks the oscillator to an external sync pulse; sync threshold is 1.2 V to 2.8 V (2 V typ.).
4 OSC OUTPUT output Sync pulse output used to synchronize multiple devices operating together, with a clock amplitude of 3 V typ. and a pulse width of 0.5 µs typ.
5 CT input Oscillator timing capacitor pin; CT should be between 1 nF and 0.1 µF, and a sawtooth of 0.9 V to 3.5 V appears across it in normal operation.
6 RT input Oscillator timing resistor pin that sets the internal constant charging current into CT; RT should be between 2 kΩ and 150 kΩ.
7 DISCHARGE input Oscillator discharge pin; the dead-time resistor RD between pins 5 and 7 must be between 0 Ω and 500 Ω and sets the CT discharge time and dead time.
8 SOFT START input Soft-start control pin where an external soft-start capacitor is charged by an internal 50 µA constant current source.
9 COMP output Error amplifier compensation output feeding the PWM comparator; the feedback network between this pin and pin 1 sets proportional, PI or integral regulator behavior.
10 SHUTDOWN input External shutdown input where a high level disables the outputs and discharges the soft-start capacitor; it must not be left floating and should be tied to ground through a resistor.
11 OUTPUT A output Push-pull driver output A, complementary to OUTPUT B (pin 14), with source and sink peak currents up to 500 mA.
12 GND power_in Power and signal ground of the chip.
13 VC power_in Output-stage bias voltage input; the output stage collector voltage has an absolute maximum of 40 V.
14 OUTPUT B output Push-pull driver output B, complementary to OUTPUT A (pin 11), with source and sink peak currents up to 500 mA.
15 VCC power_in Supply input for internal logic, analog circuits and the reference, operating from 8 V to 35 V with an absolute maximum of 40 V; outputs are disabled by undervoltage lockout below 8 V.
16 Vref power_out 5.1 V ±1% reference output that can be divided down to set the error amplifier reference, with a maximum output current of 50 mA.

Key specifications

Parameter Value
Manufacturer EG Micro
Package SOP-16
Category Power Management (PMIC)
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply input voltage (absolute max) VCC 40 V 10
Collector voltage (absolute max) VC 40 V 10
Oscillator charging current (absolute max) IOSC 5 mA 10
Output current (absolute max) IO 500 mA 10
Reference output current (absolute max) IR 50 mA 10
Current flowing into CT pin (absolute max) IT 5 mA 10
Logic input voltage (absolute max) VL -0.3 5.5 V 10
Analog input voltage (absolute max) VA -0.3 V 10
Total power dissipation (absolute max) Ptot 1000 mW 10
Ambient temperature (absolute max) TA -45 85 ℃ 10
Storage temperature (absolute max) Tstr -65 125 ℃ 10
Soldering temperature (absolute max) TL 300 ℃ T=10S 10
Supply voltage Vcc 8 15 35 V 10
Static current Icc 14 20 mA 10
Reference voltage VREF 5 5.1 5.2 V VCC=15V 10
Line regulation ΔVREF 10 20 mV VCC=8 to 35V 10
Load regulation ΔVREF 20 50 mV IL=0 to 20mA 10
Reference temperature drift ΔVREF/ΔT 20 50 mV 10
Total output offset (line, load and temperature) 4.95 5.25 V Line, Load And Temprature 10
Short-circuit output current ISC 50 80 mA VREF=0 10
Initial frequency accuracy Δf -6 2 6 % VCC=15V 11
Frequency voltage rejection Δf/ΔVCC -2 1 2 % VCC=8 to 35V 11
Frequency temperature drift Δf/ΔT -6 3 6 % 11
Minimum frequency fMIN 120 Hz RT=200KΩ CT=0.1uF 11
Maximum frequency fMAX 400 KHz RT=2KΩ CT=470pF 11
Mirror current Imirror 1.7 2 2.2 mA IRT=2mA 11
Clock amplitude OSCAMP 3 3.5 V 11
Clock width OSCWIDTH 0.3 0.5 1 uS 11
Sync voltage threshold VSYNCTH 1.2 2 2.8 V 11
Sync input current ISYNC 1 2.5 mA Sync voltage=3.5V 11
Error amplifier input offset voltage VOS 2 10 mV VCC=15V 11
Error amplifier input bias current Ib 1 10 uA 11
Error amplifier input offset current IOS 1 uA 11
Open-loop gain AVOL 60 75 dB 11
Error amplifier output low level VOL 0.2 0.5 V 11
Error amplifier output high level VOH 3.8 5.6 V 11
Common-mode rejection ratio CMRR 60 75 dB VCM=1.5V to 5.2V 11
Power supply rejection ratio PSRR 50 60 dB VCC=8 to 35V 11
Minimum duty cycle Dmin 0 % VCOMP=0V, VSD=0V 11
Maximum duty cycle Dmax 45 49 % VCOMP=5V, VSD=0V 11
Input threshold voltage 1 Vth1 0.7 0.9 V 0% duty cycle 11
Input threshold voltage 2 Vth2 3.3 3.6 V 49% duty cycle 11
PWM comparator input bias current IIB 0.05 1 uA 11
Soft-start timing capacitor charge current ISST 25 50 80 uA VSD=0V, VSST=0V 11
Soft-start low level VOL(SST) 0.4 0.7 V VSD=2.5V 11
Shutdown pin threshold voltage VTH(SD) 0.7 1.3 1.7 V 11
Shutdown pin input current IN(SD) 0.3 1 mA VSD=2.5V 12
Shutdown delay time VSD(Delay) 0.2 0.5 uS 12
Output low level I VOL I 0.1 0.4 V ISINK=20mA 12
Output low level II VOL II 1 2 V ISINK=100mA 12
Output high level I VCH I 13 14 V ISOURCE=20mA 12
Output high level II VCH II 12 13 V ISOURCE=100mA 12
Undervoltage lockout threshold VUV 6 7 8 V V8 and V9=High 12
Collector leakage current ILKG 80 200 uA VC=35V 12
Rise time tR 100 500 nS CL=1nF, Tj=25℃ 12
Fall time tF 70 300 nS CL=1nF, Tj=25℃ 12

CAD (KiCad official)

  • Symbol: EG3525S
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOP-16 (KiCad packages3D, STEP)
  • 3D model files: eg3525s-etched.step / eg3525s-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); eg3525s.step / eg3525s.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: EG Micro datasheet (17 pp, sha256 c27579fe1f0edb3b, retrieved 2026-10-18, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF