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docs eg2131: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
viewers pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray
eg2131-etched.fit.json eg2131: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
eg2131-etched.glb eg2131: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
eg2131-etched.step eg2131: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
eg2131.glb Publish 0.1.0 · Ray
eg2131.kicad_mod Publish 0.1.0 · Ray
eg2131.kicad_sym Publish 0.1.0 · Ray
eg2131.lbr rebuild the library on adom-lbr 2.32.0. The published copy was built by 2.18.0, which imported every KiCad roundrect an… · Ray
eg2131.step Publish 0.1.0 · Ray
package.json Publish 0.2.0 · Ray
pads.json pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray
page.json eg2131: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray
README.md eg2131: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray

EG2131

EG Micro · Isolators - Gate Drivers · SOP-8-150mil

EG2131 from EG Micro, in a SOP-8-150mil. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VCC power_in Low-side supply input, 11V-20V operating range. Bypass with a 0.1uF high-frequency capacitor close to the pin to attenuate supply noise.
2 HIN input High-side logic input, active-high. '1' turns the high-side power MOSFET on, '0' turns it off. Internal 200k pull-down to GND ensures the high-side output stays off when the pin floats.
3 LIN input Low-side logic input, active-low (inverted). '0' turns the low-side power MOSFET on, '1' turns it off. Internal 200k pull-up to +5V holds the low-side output off when the pin floats.
4 GND power_in Device ground reference for VCC and the low-side driver return.
5 LO output Low-side gate drive output. Drives the gate of the low-side power MOSFET/IGBT referenced to GND with ±1A/1.5A source/sink capability.
6 VS power_in High-side floating return / switch-node reference. Connects to the source of the high-side MOSFET (or emitter of the IGBT) and is the negative rail for the bootstrap capacitor.
7 HO output High-side gate drive output. Drives the gate of the high-side power MOSFET/IGBT referenced to VS with ±1A/1.5A source/sink capability. Can swing up to 300V above GND.
8 VB power_in High-side floating bootstrap supply. Connect a bootstrap capacitor from VB to VS and a bootstrap diode from VCC to VB. Rated for up to ~300V above GND.

Key specifications

Parameter Value
Manufacturer EG Micro
Package SOP-8-150mil
Category PMIC
Pins 8

CAD (KiCad official)

  • Symbol: EG2131
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOP-8-150mil (KiCad packages3D, STEP)
  • 3D model files: eg2131-etched.step / eg2131-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); eg2131.step / eg2131.glb are the bare package body.

3D model downloads

Two STEP files. Same geometry, different body top:

File Size Use it when
eg2131.step 122 KB You want the bare part, or you mark your own boards.
eg2131-etched.step 1.4 MB You want the part with EG2131 already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 361 faces against 147 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: EG Micro datasheet (12 pp, sha256 392f5e32b0517c92, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF