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EG1269

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EG Micro AC-DC Controllers And Regulators, SOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentpower management (pmic)eg1269factory-2.0.0extractor-text
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Symbol & Footprint

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Datasheet

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Contents

README

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EG1269

EG Micro · AC-DC Controllers And Regulators · SOP-8

EG1269 from EG Micro, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GND power_in Chip power ground for the controller, the reference for the FB, RI, RT and CS networks.
2 FB input Feedback input whose voltage, together with the CS current-sense signal, sets the PWM duty cycle; FB open-circuit voltage is 5.3 V typ, the power-limit (OLP) threshold is 4.6 V, and the burst-mode voltage is 1.5 V.
3 VDD power_in Supply pin; the datasheet gives a UVLO turn-on threshold of 16 V typ, a 27.8 V typ overvoltage-protection entry level, a 32 V typ zener clamp at 10 mA, and a 30 V absolute maximum with 10 mA maximum clamp current.
4 RI passive Oscillator-frequency setting pin; a resistor from RI to GND sets the PWM frequency by Fosc(kHz)=1560/RI(kΩ), with the allowed RI range being 12 kΩ to 60 kΩ (24 kΩ typical).
5 RT passive Over-temperature protection pin, which connects to an NTC thermistor to GND; an internal 80 µA current source pulls RT, the controller shuts off when RT falls to 1 V and recovers when it rises above 1.1 V.
6 CS input Current-sense input that monitors the voltage across the external sense resistor for cycle-by-cycle current limiting, with a 0.88 V typ limit (0.8 V to 0.96 V) and 300 ns typ leading-edge blanking.
7 VDD power_in Supply pin, electrically the same supply node as pin 3 and carrying the same 30 V absolute maximum rating.
8 GATE output Gate-drive output for the external power MOSFET, rated at 13 V typ high-level output at 20 mA source, 0.3 V typ low-level output at 20 mA sink, and 110 ns rise / 40 ns fall times at 1 nF load.

Key specifications

Parameter Value
Manufacturer EG Micro
Package SOP-8
Category Power Management (PMIC)
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
VDD supply voltage VDD -0.3 30 V 7
VDD clamp current Iclamp 10 mA 7
FB, CS, RI, RT low-voltage pins 6 V 7
OUT output pin (max printed as VCC+0.3 V) OUT -0.3 V 7
Ambient operating temperature TA -45 125 ℃ 7
Storage temperature Tstr -65 150 ℃ 7
Soldering temperature TL 300 ℃ T=10S 7
VDD UVLO turn-on threshold UVLO_OFF 15 16 17 V 8
VDD UVLO turn-off threshold UVLO_ON 9.3 10.3 11.3 V 8
VDD overvoltage protection enter V_OVP_ON 26.8 27.8 28.8 V 8
VDD overvoltage protection exit V_OVP_OFF 26 27 28 V 8
VDD zener clamp voltage Vdd_Clamp 31 32 33 V I(VDD) = 10 mA 8
VDD start-up current Ivdd_start 6 10 uA 8
Operating current Ivdd 3 8 mA VFB=3V,GATE=1nF 8
CS current-limit threshold Vcs(max) 0.8 0.88 0.96 V 8
Normal oscillation frequency Fosx 60 65 70 KHz 8
Frequency shuffle range / FOSC ΔF(shuffle)/FOSC -4 4 % 8
RI selection range RI_range 12 24 60 KΩ 8
FB open-circuit voltage Vfb_Open 5.3 V 8
FB burst voltage Vfb_Open 1.5 V 8
FB short-circuit current Ifb_Short 1.2 mA FB 接地 8
PWM gain AVcs 2.8 V/V 8
Power-limit FB threshold voltage Vth_OLP 4.6 V 8
Overload delay time Td_PL 65 ms 8
Input leading-edge blanking time Tleb 300 ns 8
Overcurrent detection control delay Td_OCP 120 ns GATE=1nF 8
Frequency shuffle period T(shuffle) 32 ms 8
RI open-circuit voltage VRI_open 2 V 8
Maximum switching duty cycle Dmax 80 % 9
Burst-mode frequency Fburst 25 KHz 9
RT pin current I_RT 80 uA 9
Over-temperature protection enter voltage VTH_OTP 1 V 9
Over-temperature protection exit voltage VTH_OTP_off 1.1 V 9
GATE low-level output voltage Vol 0.3 V Igate_sink=-20mA 9
GATE high-level output voltage Voh 13 V Igate_source=20mA 9
GATE output rise time T_r 110 ns GATE=1nF 9
GATE output fall time T_f 40 ns GATE=1nF 9

CAD (KiCad official)

  • Symbol: EG1269
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOP-8 (KiCad packages3D, STEP)
  • 3D model files: eg1269-etched.step / eg1269-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); eg1269.step / eg1269.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: EG Micro datasheet (13 pp, sha256 5871c2432d31783c, retrieved 2026-10-17, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF