component
EG1192L
Public Made by Adomby adom
EG Micro DC-DC Converters, ESOP-8. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
← Commit history
symbol: the symbol numbered its pins 0-8 against pads 1-9, so pin "0" bound to no pad and the thermal pad had no pin at all. Renumbered to the datasheet's 1-9 with 9 = EP. Pinout taken from this part's datasheet for its own ordering suffix. The library failed validate because the symbol declared pins the footprint has no pad for (connect-pad-unresolved), which also blocked its orderable attributes. Rebuilds the .lbr, re-derives pin 1 and pads.json.
4 files changed
+110−83
eg1192l.kicad_sym+15−15@@ -1,17 +1,13 @@ (kicad_symbol_lib (version 20211014) (generator ds2sf_rect) (symbol "EG1192L" (in_bom yes) (on_board yes)- (property "Reference" "U" (at 0 10.16 0) (effects (font (size 1.27 1.27))))- (property "Value" "EG1192L" (at 0 -10.16 0) (effects (font (size 1.27 1.27))))+ (property "Reference" "U" (at 0 7.62 0) (effects (font (size 1.27 1.27))))+ (property "Value" "EG1192L" (at 0 -12.70 0) (effects (font (size 1.27 1.27)))) (property "Footprint" "" (at 0 0 0) (effects (font (size 1.27 1.27)) hide)) (symbol "EG1192L_0_1"- (rectangle (start -12.70 7.62) (end 12.70 -7.62)+ (rectangle (start -12.70 5.08) (end 12.70 -10.16) (stroke (width 0.254) (type default)) (fill (type background))) ) (symbol "EG1192L_1_1"- (pin power_in line (at -17.78 5.08 0) (length 5.08)- (name "VIN" (effects (font (size 1.27 1.27))))- (number "0" (effects (font (size 1.27 1.27))))- ) (pin power_in line (at -17.78 2.54 0) (length 5.08) (name "VIN" (effects (font (size 1.27 1.27)))) (number "1" (effects (font (size 1.27 1.27))))@@ -24,26 +20,30 @@ (name "EN" (effects (font (size 1.27 1.27)))) (number "3" (effects (font (size 1.27 1.27)))) )- (pin output line (at -17.78 -5.08 0) (length 5.08)+ (pin passive line (at -17.78 -5.08 0) (length 5.08) (name "VIA" (effects (font (size 1.27 1.27)))) (number "4" (effects (font (size 1.27 1.27)))) )- (pin input line (at 17.78 2.54 180) (length 5.08)+ (pin input line (at -17.78 -7.62 0) (length 5.08)+ (name "FB" (effects (font (size 1.27 1.27))))+ (number "5" (effects (font (size 1.27 1.27))))+ )+ (pin power_in line (at 17.78 2.54 180) (length 5.08)+ (name "EP" (effects (font (size 1.27 1.27))))+ (number "9" (effects (font (size 1.27 1.27))))+ )+ (pin passive line (at 17.78 0.00 180) (length 5.08) (name "IS" (effects (font (size 1.27 1.27)))) (number "8" (effects (font (size 1.27 1.27)))) )- (pin output line (at 17.78 0.00 180) (length 5.08)+ (pin passive line (at 17.78 -2.54 180) (length 5.08) (name "VS" (effects (font (size 1.27 1.27)))) (number "7" (effects (font (size 1.27 1.27)))) )- (pin passive line (at 17.78 -2.54 180) (length 5.08)+ (pin passive line (at 17.78 -5.08 180) (length 5.08) (name "VB" (effects (font (size 1.27 1.27)))) (number "6" (effects (font (size 1.27 1.27)))) )- (pin input line (at 17.78 -5.08 180) (length 5.08)- (name "FB" (effects (font (size 1.27 1.27))))- (number "5" (effects (font (size 1.27 1.27))))- ) ) ) )
eg1192l.lbr+51−33@@ -50,10 +50,10 @@ <layer number="98" name="Guide" color="6" fill="1" visible="yes" active="yes"/> </layers> <library>-<description>SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.3mm (symbol synthesized from footprint pads)</description>+<description></description> <packages>-<package name="SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.3mm">- <description>SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.3mm</description>+<package name="EG1192L">+ <description>EG1192L</description> <smd name="1" x="-2.4750" y="1.9050" dx="1.9500" dy="0.6000" layer="1"/> <smd name="2" x="-2.4750" y="0.6350" dx="1.9500" dy="0.6000" layer="1"/> <smd name="3" x="-2.4750" y="-0.6350" dx="1.9500" dy="0.6000" layer="1"/>@@ -63,6 +63,18 @@ <smd name="7" x="2.4750" y="0.6350" dx="1.9500" dy="0.6000" layer="1"/> <smd name="8" x="2.4750" y="1.9050" dx="1.9500" dy="0.6000" layer="1"/> <smd name="9" x="0.0000" y="-0.0000" dx="2.4100" dy="3.3000" layer="1"/>+ <polygon width="0.1200" layer="21">+ <vertex x="-2.6000" y="2.4700"/>+ <vertex x="-2.8400" y="2.8000"/>+ <vertex x="-2.3600" y="2.8000"/>+ </polygon>+ <polygon width="0.1000" layer="51">+ <vertex x="-0.9750" y="2.4500"/>+ <vertex x="1.9500" y="2.4500"/>+ <vertex x="1.9500" y="-2.4500"/>+ <vertex x="-1.9500" y="-2.4500"/>+ <vertex x="-1.9500" y="1.4750"/>+ </polygon> <wire x1="-2.0600" y1="2.5600" x2="2.0600" y2="2.5600" width="0.1200" layer="21"/> <wire x1="-2.0600" y1="2.4650" x2="-2.0600" y2="2.5600" width="0.1200" layer="21"/> <wire x1="-2.0600" y1="-2.5600" x2="-2.0600" y2="-2.4650" width="0.1200" layer="21"/>@@ -74,44 +86,50 @@ <!--adom-pin1--><polygon width="0.0500" layer="21"><vertex x="-2.6000" y="2.4700"/><vertex x="-2.8400" y="2.8000"/><vertex x="-2.3600" y="2.8000"/></polygon></package> </packages> <symbols>-<symbol name="SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.3mm">- <wire x1="-7.62" y1="7.619999999999999" x2="7.62" y2="7.619999999999999" width="0.254" layer="94"/>- <wire x1="7.62" y1="7.619999999999999" x2="7.62" y2="-7.619999999999999" width="0.254" layer="94"/>- <wire x1="7.62" y1="-7.619999999999999" x2="-7.62" y2="-7.619999999999999" width="0.254" layer="94"/>- <wire x1="-7.62" y1="-7.619999999999999" x2="-7.62" y2="7.619999999999999" width="0.254" layer="94"/>- <text x="0" y="10.16" size="1.27" layer="95" align="bottom-center">>NAME</text>- <text x="0" y="-10.16" size="1.27" layer="96" align="top-center">>VALUE</text>- <pin name="1" x="-12.7" y="6.35" length="short" direction="pas"/>- <pin name="2" x="-12.7" y="3.81" length="short" direction="pas"/>- <pin name="3" x="-12.7" y="1.27" length="short" direction="pas"/>- <pin name="4" x="-12.7" y="-1.27" length="short" direction="pas"/>- <pin name="5" x="-12.7" y="-3.81" length="short" direction="pas"/>- <pin name="6" x="12.7" y="6.35" length="short" direction="pas" rot="R180"/>- <pin name="7" x="12.7" y="3.81" length="short" direction="pas" rot="R180"/>- <pin name="8" x="12.7" y="1.27" length="short" direction="pas" rot="R180"/>- <pin name="9" x="12.7" y="-1.27" length="short" direction="pas" rot="R180"/>+<symbol name="EG1192L">+ <wire x1="-12.7" y1="5.08" x2="12.7" y2="5.08" width="0.254" layer="94"/>+ <wire x1="12.7" y1="5.08" x2="12.7" y2="-10.16" width="0.254" layer="94"/>+ <wire x1="12.7" y1="-10.16" x2="-12.7" y2="-10.16" width="0.254" layer="94"/>+ <wire x1="-12.7" y1="-10.16" x2="-12.7" y2="5.08" width="0.254" layer="94"/>+ <text x="0" y="7.62" size="1.27" layer="95" align="bottom-center">>NAME</text>+ <text x="0" y="-12.7" size="1.27" layer="96" align="top-center">>VALUE</text>+ <pin name="VIN" x="-17.78" y="2.54" length="middle" direction="pwr"/>+ <pin name="GND" x="-17.78" y="0" length="middle" direction="pwr"/>+ <pin name="EN" x="-17.78" y="-2.54" length="middle" direction="in"/>+ <pin name="VIA" x="-17.78" y="-5.08" length="middle" direction="pas"/>+ <pin name="FB" x="-17.78" y="-7.62" length="middle" direction="in"/>+ <pin name="EP" x="17.78" y="2.54" length="middle" direction="pwr" rot="R180"/>+ <pin name="IS" x="17.78" y="0" length="middle" direction="pas" rot="R180"/>+ <pin name="VS" x="17.78" y="-2.54" length="middle" direction="pas" rot="R180"/>+ <pin name="VB" x="17.78" y="-5.08" length="middle" direction="pas" rot="R180"/> </symbol> </symbols> <devicesets>-<deviceset name="SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.3mm" prefix="U">- <description>SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.3mm (symbol synthesized from footprint pads)</description>+<deviceset name="EG1192L" prefix="U">+ <description></description> <gates>- <gate name="G$1" symbol="SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.3mm" x="0" y="0"/>+ <gate name="G$1" symbol="EG1192L" x="0" y="0"/> </gates> <devices>- <device name="" package="SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.3mm">+ <device name="" package="EG1192L"> <connects>- <connect gate="G$1" pin="1" pad="1"/>- <connect gate="G$1" pin="2" pad="2"/>- <connect gate="G$1" pin="3" pad="3"/>- <connect gate="G$1" pin="4" pad="4"/>- <connect gate="G$1" pin="5" pad="5"/>- <connect gate="G$1" pin="6" pad="6"/>- <connect gate="G$1" pin="7" pad="7"/>- <connect gate="G$1" pin="8" pad="8"/>- <connect gate="G$1" pin="9" pad="9"/>+ <connect gate="G$1" pin="VIN" pad="1"/>+ <connect gate="G$1" pin="GND" pad="2"/>+ <connect gate="G$1" pin="EN" pad="3"/>+ <connect gate="G$1" pin="VIA" pad="4"/>+ <connect gate="G$1" pin="FB" pad="5"/>+ <connect gate="G$1" pin="EP" pad="9"/>+ <connect gate="G$1" pin="IS" pad="8"/>+ <connect gate="G$1" pin="VS" pad="7"/>+ <connect gate="G$1" pin="VB" pad="6"/> </connects>- <technologies><technology name=""/></technologies>+ <technologies>+ <technology name="">+ <attribute name="MPN" value="EG1192L" constant="no"/>+ <attribute name="MANUFACTURER" value="EG Micro" constant="no"/>+ <attribute name="LCSC_PN" value="C2987436" constant="no"/>+ </technology>+ </technologies> </device> </devices> </deviceset>
pads.json+18−18@@ -19,7 +19,6 @@ }, "pad_count": 9, "symbol_pins": [- "0", "1", "2", "3",@@ -27,7 +26,8 @@ "5", "6", "7",- "8"+ "8",+ "9" ], "paste_apertures": 4, "issues": [],@@ -54,7 +54,7 @@ "pin": "1", "name": "VIN", "type": "power_in",- "description": "Chip power-supply input. Wide-voltage range 10 V to 100 V; bypass with a low-ESR bulk capacitor and a 0.1 µF ceramic close to the pin.",+ "description": "Chip power supply input. Absolute maximum 100V; recommended operating range 10V to 100V. Place input decoupling capacitor close to this pin.", "is_pin1": true, "source": { "geometry": "SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.3mm.kicad_mod",@@ -84,7 +84,7 @@ "pin": "2", "name": "GND", "type": "power_in",- "description": "Device ground reference. Connect to the system ground plane; tie the exposed pad copper to this net for thermal performance.",+ "description": "Device ground reference.", "is_pin1": false, "source": { "geometry": "SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.3mm.kicad_mod",@@ -114,7 +114,7 @@ "pin": "3", "name": "EN", "type": "input",- "description": "Enable input, active high - drives the switching converter on. Pulling EN low fully shuts down the chip for zero standby current.",+ "description": "Enable input, active high. EN > 2.8V turns the switching converter on; EN < 1V places the chip in zero-power shutdown (Isd < 10 uA). Absolute maximum 7V.", "is_pin1": false, "source": { "geometry": "SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.3mm.kicad_mod",@@ -143,8 +143,8 @@ "thermal": false, "pin": "4", "name": "VIA",- "type": "output",- "description": "Input-voltage sense/divider output. Internally the VIN rail is fed through a resistor divider (≈450 kΩ / 15 kΩ) and brought out here for input-voltage sampling by an external MCU/ADC.",+ "type": "passive",+ "description": "Input supply resistor-divider output. Provides a scaled-down replica of VIN via an internal 450k/15k divider, used for input voltage sensing. Absolute maximum 7V.", "is_pin1": false, "source": { "geometry": "SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.3mm.kicad_mod",@@ -174,7 +174,7 @@ "pin": "5", "name": "FB", "type": "input",- "description": "Output-voltage feedback input to the internal error amplifier (VREF ≈ 1.25 V). Connect through an external resistor divider from VOUT to program the output voltage.",+ "description": "Output voltage feedback input. Regulates to an internal 1.25V reference (min 1.21V, typ 1.25V, max 1.29V). Set Vout via external divider: Vout = (1 + R1/R2) x 1.25V. Input current < 1 uA.", "is_pin1": false, "source": { "geometry": "SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.3mm.kicad_mod",@@ -204,7 +204,7 @@ "pin": "6", "name": "VB", "type": "passive",- "description": "Bootstrap (floating) supply for the high-side MOSFET gate driver. Connect a bootstrap capacitor (typ. 0.1 µF) between VB and VS.",+ "description": "Bootstrap (floating) supply for the high-side gate driver. Connect a bootstrap capacitor between VB and VS. Rated VS-0.3V to VS+7V.", "is_pin1": false, "source": { "geometry": "SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.3mm.kicad_mod",@@ -233,8 +233,8 @@ "thermal": false, "pin": "7", "name": "VS",- "type": "output",- "description": "Switch node - floating ground reference for the high-side driver and drain of the freewheeling path. Connect to the external inductor and the anode of the freewheeling Schottky (e.g. SS310); return of the bootstrap capacitor.",+ "type": "passive",+ "description": "Floating ground / switch node. Connects to the source of the internal high-side MOSFET and to the inductor / catch-diode node. Rated -0.3V to 100V.", "is_pin1": false, "source": { "geometry": "SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.3mm.kicad_mod",@@ -263,8 +263,8 @@ "thermal": false, "pin": "8", "name": "IS",- "type": "input",- "description": "MOS peak current-limit sense input (VREF ≈ 0.18 V). Sets cycle-by-cycle over-current protection via an external sense resistor.",+ "type": "passive",+ "description": "MOSFET peak current-limit sense input. Trips cycle-by-cycle current limit at 0.18V above VS. Rated VS-0.3V to VS+6V.", "is_pin1": false, "source": { "geometry": "SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.3mm.kicad_mod",@@ -287,15 +287,15 @@ ], "layers": [], "thermal": true,- "pin": "0",- "name": "VIN",+ "pin": "9",+ "name": "EP", "type": "power_in",- "description": "Chip power-supply input tied to the exposed thermal pad on the backside of the package. Connect to the same net as pin 1 VIN (10 V to 100 V input range) and to the ground/thermal copper pour for heat dissipation.",+ "description": "Exposed thermal pad on the chip backside, listed as pin 0 in the datasheet's pin description as an additional VIN input. Connect to a large copper pour tied to VIN for both power input and heat dissipation.", "is_pin1": false, "source": { "geometry": "SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.3mm.kicad_mod",- "meaning": null,- "correspondence": "derived: sole unmatched pin \"0\" to sole thermal pad \"9\""+ "meaning": "page.json:component.pins",+ "correspondence": "kicad: symbol pin number == pad name" } } ]
page.json+26−17@@ -30,59 +30,68 @@ "lcsc": "C2987436" }, "pins": [- {- "number": "0",- "name": "VIN",- "type": "power_in",- "description": "Chip power-supply input tied to the exposed thermal pad on the backside of the package. Connect to the same net as pin 1 VIN (10 V to 100 V input range) and to the ground/thermal copper pour for heat dissipation."- }, { "number": "1", "name": "VIN", "type": "power_in",- "description": "Chip power-supply input. Wide-voltage range 10 V to 100 V; bypass with a low-ESR bulk capacitor and a 0.1 \u00b5F ceramic close to the pin."+ "description": "Chip power supply input. Absolute maximum 100V; recommended operating range 10V to 100V. Place input decoupling capacitor close to this pin.",+ "group": "POWER" }, { "number": "2", "name": "GND", "type": "power_in",- "description": "Device ground reference. Connect to the system ground plane; tie the exposed pad copper to this net for thermal performance."+ "description": "Device ground reference.",+ "group": "GROUND" }, { "number": "3", "name": "EN", "type": "input",- "description": "Enable input, active high - drives the switching converter on. Pulling EN low fully shuts down the chip for zero standby current."+ "description": "Enable input, active high. EN > 2.8V turns the switching converter on; EN < 1V places the chip in zero-power shutdown (Isd < 10 uA). Absolute maximum 7V.",+ "group": "CONTROL" }, { "number": "4", "name": "VIA",- "type": "output",- "description": "Input-voltage sense/divider output. Internally the VIN rail is fed through a resistor divider (\u2248450 k\u03a9 / 15 k\u03a9) and brought out here for input-voltage sampling by an external MCU/ADC."+ "type": "passive",+ "description": "Input supply resistor-divider output. Provides a scaled-down replica of VIN via an internal 450k/15k divider, used for input voltage sensing. Absolute maximum 7V.",+ "group": "OTHER" }, { "number": "5", "name": "FB", "type": "input",- "description": "Output-voltage feedback input to the internal error amplifier (VREF \u2248 1.25 V). Connect through an external resistor divider from VOUT to program the output voltage."+ "description": "Output voltage feedback input. Regulates to an internal 1.25V reference (min 1.21V, typ 1.25V, max 1.29V). Set Vout via external divider: Vout = (1 + R1/R2) x 1.25V. Input current < 1 uA.",+ "group": "CONTROL" }, { "number": "6", "name": "VB", "type": "passive",- "description": "Bootstrap (floating) supply for the high-side MOSFET gate driver. Connect a bootstrap capacitor (typ. 0.1 \u00b5F) between VB and VS."+ "description": "Bootstrap (floating) supply for the high-side gate driver. Connect a bootstrap capacitor between VB and VS. Rated VS-0.3V to VS+7V.",+ "group": "POWER" }, { "number": "7", "name": "VS",- "type": "output",- "description": "Switch node - floating ground reference for the high-side driver and drain of the freewheeling path. Connect to the external inductor and the anode of the freewheeling Schottky (e.g. SS310); return of the bootstrap capacitor."+ "type": "passive",+ "description": "Floating ground / switch node. Connects to the source of the internal high-side MOSFET and to the inductor / catch-diode node. Rated -0.3V to 100V.",+ "group": "OTHER" }, { "number": "8", "name": "IS",- "type": "input",- "description": "MOS peak current-limit sense input (VREF \u2248 0.18 V). Sets cycle-by-cycle over-current protection via an external sense resistor."+ "type": "passive",+ "description": "MOSFET peak current-limit sense input. Trips cycle-by-cycle current limit at 0.18V above VS. Rated VS-0.3V to VS+6V.",+ "group": "CONTROL"+ },+ {+ "number": "9",+ "name": "EP",+ "type": "power_in",+ "description": "Exposed thermal pad on the chip backside, listed as pin 0 in the datasheet's pin description as an additional VIN input. Connect to a large copper pour tied to VIN for both power input and heat dissipation.",+ "group": "POWER" } ], "provenance": {