component
EG0001
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EG Micro Special Purpose Amplifiers, SOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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EG0001
EG Micro · Special Purpose Amplifiers · SOP-16
EG0001 from EG Micro, in a SOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | A | input | Retriggerable/non-retriggerable mode select: when A is "1" retriggering is allowed, when A is "0" retriggering is inhibited. |
| 2 | VO | output | Control signal output, driven high only on a rising edge of VS and held low outside the delay time Tx; high level is valid output. |
| 3 | RR1 | passive | Adjustment terminal for the output delay time Tx, where Tx ≈ 49152·R1·C1 with RR1 and RC1 as the timing network. |
| 4 | RC1 | passive | Adjustment terminal for the output delay time Tx, where Tx ≈ 49152·R1·C1 with RR1 and RC1 as the timing network. |
| 5 | RC2 | passive | Adjustment terminal for the trigger blocking time Ti, where Ti ≈ 24·R2·C2 with RR2 and RC2 as the timing network. |
| 6 | RR2 | passive | Adjustment terminal for the trigger blocking time Ti, where Ti ≈ 24·R2·C2 with RR2 and RC2 as the timing network. |
| 7 | VSS | power_in | Negative operating power supply terminal (ground). |
| 8 | VRF/RESET | input | Reference voltage and reset input, normally connected to VDD; pulling it to "0" resets the timers. |
| 9 | VC | input | Trigger inhibit input: triggering is inhibited when VC < VR and enabled when VC > VR, with VR ≈ 0.2·VDD. |
| 10 | IB | passive | Op-amp bias current setting terminal, connected to VSS through RB of about 1 MΩ. |
| 11 | VDD | power_in | Positive operating power supply terminal; the device operates from +3 V to +5 V. |
| 12 | 2OUT | output | Output of the second-stage operational amplifier OP2. |
| 13 | 2IN- | input | Inverting input of the second-stage operational amplifier OP2. |
| 14 | 1IN+ | input | Non-inverting input of the first-stage operational amplifier OP1. |
| 15 | 1IN- | input | Inverting input of the first-stage operational amplifier OP1. |
| 16 | 1OUT | output | Output of the first-stage operational amplifier OP1. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | EG Micro |
| Package | SOP-16 |
| Category | Amplifiers |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| 工作电压 | VDD | -0.5 | 6 | V | 8 | ||
| 输入电压 | VI | -0.5 | 6 | V | VDD=6V | 8 | |
| 各引出端最大电流 | IMAX | -10 | 10 | mA | VDD=5V | 8 | |
| 工作温度 | TA | -25 | 85 | ℃ | VDD=5V | 8 | |
| 存储温度 | TSTG | -65 | 150 | ℃ | 8 | ||
| 焊接温度 | TSLD | 300 | ℃ | 5 秒 | 8 | ||
| 工作电压 | VDD | 3 | 5 | V | 8 | ||
| 工作电流 | IDD | 50 | uA | 输出空载; VDD=3.0V | 8 | ||
| 工作电流 | IDD | 100 | uA | 输出空载; VDD=5.0V | 8 | ||
| 输入失调电压 | VOS | 50 | mV | VDD=5.0V | 8 | ||
| 输入失调电流 | IOS | 50 | nA | VDD=5.0V | 8 | ||
| 开环电压增益 | AVO | 60 | dB | VDD=5.0V RL=1.5MΩ | 8 | ||
| 共模抑制比 | CMRR | 60 | dB | VDD=5.0V RL=1.5MΩ | 8 | ||
| 运放输出高电平 | VYH | 4.25 | V | VDD=5.0V RL=500KΩ 接 1/2VDD | 8 | ||
| 运放输出低电平 | VYL | 0.75 | V | 8 | |||
| VC 端输入高电平 | VRH | 1.1 | V | VRF=VDD=5.0V | 8 | ||
| VC 端输入低电平 | VRL | 0.9 | V | 8 | |||
| VO 端输出高电平 | VOH | 4 | V | VDD=5.0V IOH=0.5mA | 8 | ||
| VO 端输出低电平 | VOL | 0.4 | V | VDD=5.0V IOL=0.1mA | 9 | ||
| A 端输出高电平 | VAH | 3.5 | V | VDD=5.0V | 9 | ||
| A 端输出低电平 | VAL | 1.5 | V | VDD=5.0V | 9 |
CAD (KiCad official)
- Symbol:
EG0001 - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SOP-16 (KiCad packages3D, STEP)
- 3D model files:
eg0001-etched.step/eg0001-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);eg0001.step/eg0001.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: EG Micro datasheet (10 pp, sha256
78273e0722a71c5b, retrieved 2026-10-28, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# EG0001
**EG Micro** · Special Purpose Amplifiers · SOP-16
EG0001 from EG Micro, in a SOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | A | input | Retriggerable/non-retriggerable mode select: when A is "1" retriggering is allowed, when A is "0" retriggering is inhibited. |
| 2 | VO | output | Control signal output, driven high only on a rising edge of VS and held low outside the delay time Tx; high level is valid output. |
| 3 | RR1 | passive | Adjustment terminal for the output delay time Tx, where Tx ≈ 49152·R1·C1 with RR1 and RC1 as the timing network. |
| 4 | RC1 | passive | Adjustment terminal for the output delay time Tx, where Tx ≈ 49152·R1·C1 with RR1 and RC1 as the timing network. |
| 5 | RC2 | passive | Adjustment terminal for the trigger blocking time Ti, where Ti ≈ 24·R2·C2 with RR2 and RC2 as the timing network. |
| 6 | RR2 | passive | Adjustment terminal for the trigger blocking time Ti, where Ti ≈ 24·R2·C2 with RR2 and RC2 as the timing network. |
| 7 | VSS | power_in | Negative operating power supply terminal (ground). |
| 8 | VRF/RESET | input | Reference voltage and reset input, normally connected to VDD; pulling it to "0" resets the timers. |
| 9 | VC | input | Trigger inhibit input: triggering is inhibited when VC < VR and enabled when VC > VR, with VR ≈ 0.2·VDD. |
| 10 | IB | passive | Op-amp bias current setting terminal, connected to VSS through RB of about 1 MΩ. |
| 11 | VDD | power_in | Positive operating power supply terminal; the device operates from +3 V to +5 V. |
| 12 | 2OUT | output | Output of the second-stage operational amplifier OP2. |
| 13 | 2IN- | input | Inverting input of the second-stage operational amplifier OP2. |
| 14 | 1IN+ | input | Non-inverting input of the first-stage operational amplifier OP1. |
| 15 | 1IN- | input | Inverting input of the first-stage operational amplifier OP1. |
| 16 | 1OUT | output | Output of the first-stage operational amplifier OP1. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | EG Micro |
| Package | SOP-16 |
| Category | Amplifiers |
| Pins | 16 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| 工作电压 | VDD | -0.5 | | 6 | V | | 8 |
| 输入电压 | VI | -0.5 | | 6 | V | VDD=6V | 8 |
| 各引出端最大电流 | IMAX | -10 | | 10 | mA | VDD=5V | 8 |
| 工作温度 | TA | -25 | | 85 | ℃ | VDD=5V | 8 |
| 存储温度 | TSTG | -65 | | 150 | ℃ | | 8 |
| 焊接温度 | TSLD | | | 300 | ℃ | 5 秒 | 8 |
| 工作电压 | VDD | 3 | | 5 | V | | 8 |
| 工作电流 | IDD | | | 50 | uA | 输出空载; VDD=3.0V | 8 |
| 工作电流 | IDD | | | 100 | uA | 输出空载; VDD=5.0V | 8 |
| 输入失调电压 | VOS | | | 50 | mV | VDD=5.0V | 8 |
| 输入失调电流 | IOS | | | 50 | nA | VDD=5.0V | 8 |
| 开环电压增益 | AVO | 60 | | | dB | VDD=5.0V RL=1.5MΩ | 8 |
| 共模抑制比 | CMRR | 60 | | | dB | VDD=5.0V RL=1.5MΩ | 8 |
| 运放输出高电平 | VYH | 4.25 | | | V | VDD=5.0V RL=500KΩ 接 1/2VDD | 8 |
| 运放输出低电平 | VYL | | | 0.75 | V | | 8 |
| VC 端输入高电平 | VRH | 1.1 | | | V | VRF=VDD=5.0V | 8 |
| VC 端输入低电平 | VRL | | | 0.9 | V | | 8 |
| VO 端输出高电平 | VOH | 4 | | | V | VDD=5.0V IOH=0.5mA | 8 |
| VO 端输出低电平 | VOL | | | 0.4 | V | VDD=5.0V IOL=0.1mA | 9 |
| A 端输出高电平 | VAH | 3.5 | | | V | VDD=5.0V | 9 |
| A 端输出低电平 | VAL | | | 1.5 | V | VDD=5.0V | 9 |
## CAD (KiCad official)
- Symbol: `EG0001`
- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`
- 3D model: SOP-16 (KiCad packages3D, STEP)
- 3D model files: `eg0001-etched.step` / `eg0001-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `eg0001.step` / `eg0001.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [EG Micro datasheet](docs/eg0001-datasheet.pdf) (10 pp, sha256 `78273e0722a71c5b`, retrieved 2026-10-28, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/eg0001-datasheet.pdf)