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EFR32MG24B020F1536IM40-B

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SILICON LABS RF Transceiver ICs, QFN-40(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentradio frequency chip-antennaefr32mg24b020f1536im40-bfactory-2.0.0extractor-text

Verified EFR32MG24B020F1536IM40-B

by Ray · last 31 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

31 Oct 2026RayPublished by the parts factory: tier lcsc, 41 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: EFR32MG24B020F1536IM40-B · QFN-40(5x5) · 41 pins
  • ✓copper: 41 copper pads, none touching another net
  • ✓datasheet: all 41 pin names found in the 132-page datasheet
  • ✓distributor: lcsc C7271968, digikey 336-EFR32MG24B020F1536IM40-B-ND, mouser 634-32MGB020F153640B
  • ✓family: QFN-40-1EP_5x5mm_P0.4mm_EP3.6x3.6mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-f6dy9bnc/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height within the datasheet's package drawing (datasheet p.122)
  • ✓pads: 41 pins = 41 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 41 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ efr32mg24b020f1536im40-b.kicad_sym✓ efr32mg24b020f1536im40-b.kicad_mod✓ efr32mg24b020f1536im40-b.step
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Ray Publish 0.1.0 c3a3b64 3d ago

EFR32MG24B020F1536IM40-B

SILICON LABS · RF Transceiver ICs · QFN-40(5x5)

EFR32MG24B020F1536IM40-B from SILICON LABS, in a QFN-40(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PC00 bidirectional GPIO; alternate function EM4 wakeup (GPIO.EM4WU6).
2 PC01 bidirectional GPIO; alternate function GPIO.EFP_TX_SDA.
3 PC02 bidirectional GPIO; alternate function GPIO.EFP_TX_SCL.
4 PC03 bidirectional GPIO.
5 PC04 bidirectional GPIO.
6 PC05 bidirectional GPIO; alternate functions GPIO.EFP_INT and EM4 wakeup (GPIO.EM4WU7).
7 PC06 bidirectional GPIO.
8 PC07 bidirectional GPIO.
9 HFXTAL_I input High Frequency Crystal Input.
10 HFXTAL_O output High Frequency Crystal Output.
11 RESETn input Reset pin, internally pulled up to DVDD.
12 RFVDD power_in Radio power supply.
13 RFVSS power_in Radio ground.
14 RF2G4_IO bidirectional 2.4 GHz RF input/output (single-ended antenna interface).
15 PAVDD power_in Power Amplifier (PA) power supply.
16 PB04 bidirectional GPIO.
17 PB03 bidirectional GPIO; alternate functions EM4 wakeup (GPIO.EM4WU4) and VDAC1 channel 1 main output.
18 PB02 bidirectional GPIO; alternate function VDAC1 channel 0 main output.
19 PB01 bidirectional GPIO; alternate functions EM4 wakeup (GPIO.EM4WU3) and VDAC0 channel 1 main output.
20 PB00 bidirectional GPIO; alternate function VDAC0 channel 0 main output.
21 PA00 bidirectional GPIO.
22 PA01 bidirectional GPIO; alternate function debug GPIO.SWCLK.
23 PA02 bidirectional GPIO; alternate function debug GPIO.SWDIO.
24 PA03 bidirectional GPIO; alternate functions GPIO.SWV, GPIO.TDO and GPIO.TRACEDATA0.
25 PA04 bidirectional GPIO; alternate functions GPIO.TDI and GPIO.TRACECLK.
26 PA05 bidirectional GPIO; alternate functions GPIO.TRACEDATA1 and EM4 wakeup (GPIO.EM4WU0).
27 PA06 bidirectional GPIO; alternate function GPIO.TRACEDATA2.
28 PA07 bidirectional GPIO; alternate function GPIO.TRACEDATA3.
29 PA08 bidirectional GPIO.
30 DECOUPLE power_out Decouple output for on-chip voltage regulator; an external decoupling capacitor is required at this pin.
31 VREGSW passive DCDC regulator switching node.
32 VREGVDD power_in DCDC regulator input supply.
33 VREGVSS power_in DCDC ground.
34 DVDD power_in Digital power supply.
35 AVDD power_in Analog power supply.
36 IOVDD power_in I/O power supply.
37 PD03 bidirectional GPIO.
38 PD02 bidirectional GPIO; alternate function EM4 wakeup (GPIO.EM4WU9).
39 PD01 bidirectional GPIO; alternate functions LFXO.LFXTAL_I and LFXO.LF_EXTCLK.
40 PD00 bidirectional GPIO; alternate function LFXO.LFXTAL_O.
41 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer SILICON LABS
Package QFN-40(5x5)
Category Radio Frequency Chip/Antenna
Pins 41

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Storage temperature range TSTG -50 150 °C 23
Voltage on any supply pin VDDMAX -0.3 3.8 V 23
Junction temperature TJMAX 125 °C -I grade 23
Voltage ramp rate on any supply pin VDDRAMPMAX 1 V/µs 23
Voltage on HFXO pins VHFXOPIN -0.3 1.2 V 23
DC voltage on RESETn pin VRESETn -0.3 3.8 V 23
DC voltage on RF pin RF2G4_IO VMAX2G4 -0.3 1.2 V 23
Total current into VDD power lines IVDDMAX 200 mA Source 23
Total current into VSS ground lines IVSSMAX 200 mA Sink 23
Current per I/O pin (sink) IIOMAX 50 mA Sink 23
Current per I/O pin (source) IIOMAX 50 mA Source 23
Current for all I/O pins (sink) IIOALLMAX 200 mA Sink 23
Current for all I/O pins (source) IIOALLMAX 200 mA Source 23
Operating ambient temperature range TA -40 125 °C -I temperature grade 24
DVDD supply voltage VDVDD 1.71 3 3.8 V EM0/1 24
AVDD supply voltage VAVDD 1.71 3 3.8 V AVDDBODEN=0 24
IOVDDx operating supply voltage VIOVDDx 1.71 3 3.8 V IOVDDxBODEN=0 24
RFVDD operating supply voltage VRFVDD 1.71 3 V 24
VREGVDD operating supply voltage VVREGVDD 2.2 3 3.8 V DC-DC in regulation 24
VREGVDD operating supply voltage VVREGVDD 1.8 3 3.8 V DC-DC in bypass 60 mA load 24
VREGVDD operating supply voltage VVREGVDD 1.71 3 3.8 V DC-DC not in use. DVDD externally shorted to VREGVDD 24
PAVDD operating supply voltage VPAVDD 1.71 3 3.8 V 24
DECOUPLE output capacitor CDECOUPLE 1 2.75 µF 1.0 µF ± 10% X8L capacitor used for performance characterization. 24
HCLK and SYSCLK frequency fHCLK 78 MHz VSCALE2, MODE = WS1 24
External Clock Input fCLKIN 40 MHz VSCALE2 or VSCALE1, IOVDD ≥ 2.7 V 24
DC-DC input voltage range at VREGVDD VVREGVDD 2.2 3.8 V DCDC in regulation, ILOAD = ILOAD MAX, EM0/EM1 mode 26
DC-DC regulation DC accuracy ACCDC -2.5 4 % VVREGVDD ≥ 2.2 V, Steady state in EM0/EM1 mode or EM2/EM3 mode 26
DC-DC regulation total accuracy ACCTOT -5 7 % All error sources (including DC errors, overshoot, undershoot) 26
DC-DC output load current ILOAD 60 mA EM0/EM1 mode, DCDC in regulation, DCDC_EM01CTRL0.IPKVAL = 9, Radio not transmitting 26
DC-DC output capacitor CDCDC 4.7 10 µF 4.7 µF ± 10% X7R capacitor used for performance characterization 26
Resistance in bypass mode RBYP 0.45 0.69 Ω Bypass switch from VREGVDD to DVDD, VVREGVDD = 1.8 V 27
Powertrain PFET switch resistance RBYP 0.6 0.9 Ω Powertrain PFET switch from VREGVDD to VREGSW, VVREGVDD = 1.8 V 27
Supply monitor threshold programming range VCMP_RNG 2 2.3 V Programmable in 0.1 V steps 27
Supply monitor threshold accuracy VCMP_ACC -5 5 % Supply falling edge trip point 27
Thermal resistance, junction to ambient (40QFN) ΘJA 29.2 °C/W JEDEC 2s2p, Still Air 28
Thermal resistance, junction to board (40QFN) ΘJB 15.2 °C/W JEDEC 2s2p 28
Thermal resistance, junction to top center (40QFN) ѰJT 0.3 °C/W JEDEC 2s2p 28
Thermal resistance, junction to board (40QFN) ѰJB 11.2 °C/W JEDEC 2s2p 28
Thermal resistance, junction to case (40QFN) ΘJC 24.6 °C/W No Board, temperature controlled heat sink on top of package, all other sides of package insulated to prevent heat flow. 28
Flash supply voltage during write or erase VFLASH 1.71 3.8 V 44
Flash data retention RETFLASH 10 years TA ≤ 125 °C 44
Flash erase cycles before failure ECFLASH 10000 cycles TA ≤ 125 °C 44
Program time tPROG 41.9 43.4 45 µs TA = 25 °C, one word (32-bits) 44
Page erase time tPERASE 11.6 12.9 14 ms TA = 25 °C 44
Mass erase time tMERASE 144.3 150.5 156.8 ms TA = 25 °C, 1536kB 44
Program current IWRITE 2.8 mA 44
Page erase current IPERASE 1.9 mA Page Erase 44
Mass erase current IMERASE 2 mA Mass Erase 44
HFXO crystal frequency FHFXO 38 39 40 MHz see note 60
HFXO supported crystal max ESR ESRHFXO 60 Ω Crystal Frequency = 39.0 MHz 60
HFRCO frequency accuracy FHFRCO_ACC -3 3 % For all production calibrated frequencies 62
FSRCO frequency FFSRCO 17.2 20 21.2 MHz 63
LFRCO frequency accuracy FLFRCO_ACC -3 3 % Normal mode 64
LFRCO frequency accuracy FLFRCO_ACC -500 500 ppm Precision mode, across operating temperature range 64
ULFRCO oscillation frequency FULFRCO 0.944 1 1.095 kHz 64
GPIO leakage current ILEAK_IO 250 nA MODEx = DISABLED, IOVDD = 3.8 V TA = 125 °C, PB00-PB03, PC06-PC09, PA00 65
GPIO leakage current ILEAK_IO 200 nA MODEx = DISABLED, IOVDD = 3.8 V TA = 125 °C, All Other Pins 65
GPIO pull up/down resistance RPULL 35 44 55 kΩ Any GPIO pin. Pull-up to IOVDD: MODEn = DISABLE DOUT=1. Pull-down to VSS: MODEn = WIREDORPULLDOWN DOUT = 0. 65

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
housing PC 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. 122

CAD (KiCad official)

  • Symbol: EFR32MG24B020F1536IM40-B
  • Footprint: Package_DFN_QFN:QFN-40-1EP_5x5mm_P0.4mm_EP3.6x3.6mm
  • 3D model: QFN-40(5x5) (KiCad packages3D, STEP)
  • 3D model files: efr32mg24b020f1536im40-b-etched.step / efr32mg24b020f1536im40-b-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); efr32mg24b020f1536im40-b.step / efr32mg24b020f1536im40-b.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: SILICON LABS datasheet (132 pp, sha256 c2555e008ba4c47a, retrieved 2026-10-31, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF