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EFR32MG24B010F1536IM48-B

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SKYWORKS/SILICON LABS RF Transceiver ICs, QFN-48(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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EFR32MG24B010F1536IM48-B

SKYWORKS/SILICON LABS · RF Transceiver ICs · QFN-48(6x6)

EFR32MG24B010F1536IM48-B from SKYWORKS/SILICON LABS, in a QFN-48(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PC00 bidirectional General purpose I/O pin; alternate functions are listed in the Alternate Function Table (6.5).
2 PC01 bidirectional General purpose I/O pin; alternate functions are listed in the Alternate Function Table (6.5).
3 PC02 bidirectional General purpose I/O pin; alternate functions are listed in the Alternate Function Table (6.5).
4 PC03 bidirectional General purpose I/O pin; alternate functions are listed in the Alternate Function Table (6.5).
5 PC04 bidirectional General purpose I/O pin; alternate functions are listed in the Alternate Function Table (6.5).
6 PC05 bidirectional General purpose I/O pin; alternate functions are listed in the Alternate Function Table (6.5).
7 PC06 bidirectional General purpose I/O pin; alternate functions are listed in the Alternate Function Table (6.5).
8 PC07 bidirectional General purpose I/O pin; alternate functions are listed in the Alternate Function Table (6.5).
9 PC08 bidirectional General purpose I/O pin; alternate functions are listed in the Alternate Function Table (6.5).
10 PC09 bidirectional General purpose I/O pin; alternate functions are listed in the Alternate Function Table (6.5).
11 HFXTAL_I input High Frequency Crystal Input.
12 HFXTAL_O output High Frequency Crystal Output.
13 RESETn input Reset pin, internally pulled up to DVDD; RESETn low time of at least 100 ns ensures pin reset.
14 RFVDD power_in Radio power supply.
15 RFVSS power_in Radio Ground.
16 RF2G4_IO bidirectional 2.4 GHz RF input/output, the single-ended antenna interface.
17 PAVDD power_in Power Amplifier (PA) power supply.
18 PB05 bidirectional General purpose I/O pin; alternate functions are listed in the Alternate Function Table (6.5).
19 PB04 bidirectional General purpose I/O pin; alternate functions are listed in the Alternate Function Table (6.5).
20 PB03 bidirectional General purpose I/O pin; alternate functions are listed in the Alternate Function Table (6.5).
21 PB02 bidirectional General purpose I/O pin; alternate functions are listed in the Alternate Function Table (6.5).
22 PB01 bidirectional General purpose I/O pin; alternate functions are listed in the Alternate Function Table (6.5).
23 PB00 bidirectional General purpose I/O pin; alternate functions are listed in the Alternate Function Table (6.5).
24 VREFN input Dedicated ADC VREF Negative Input.
25 VREFP input Dedicated ADC VREF Positive Input.
26 PA00 bidirectional General purpose I/O pin; alternate functions are listed in the Alternate Function Table (6.5).
27 PA01 bidirectional General purpose I/O pin; alternate functions are listed in the Alternate Function Table (6.5).
28 PA02 bidirectional General purpose I/O pin; alternate functions are listed in the Alternate Function Table (6.5).
29 PA03 bidirectional General purpose I/O pin; alternate functions are listed in the Alternate Function Table (6.5).
30 PA04 bidirectional General purpose I/O pin; alternate functions are listed in the Alternate Function Table (6.5).
31 PA05 bidirectional General purpose I/O pin; alternate functions are listed in the Alternate Function Table (6.5).
32 PA06 bidirectional General purpose I/O pin; alternate functions are listed in the Alternate Function Table (6.5).
33 PA07 bidirectional General purpose I/O pin; alternate functions are listed in the Alternate Function Table (6.5).
34 PA08 bidirectional General purpose I/O pin; alternate functions are listed in the Alternate Function Table (6.5).
35 PA09 bidirectional General purpose I/O pin; alternate functions are listed in the Alternate Function Table (6.5).
36 DECOUPLE passive Decouple output for on-chip voltage regulator; an external decoupling capacitor is required at this pin.
37 VREGSW passive DCDC regulator switching node.
38 VREGVDD power_in DCDC regulator input supply.
39 VREGVSS power_in DCDC ground.
40 DVDD power_in Digital power supply.
41 AVDD power_in Analog power supply.
42 IOVDD power_in I/O power supply; GPIO input thresholds are proportional to the IOVDD pin.
43 PD05 bidirectional General purpose I/O pin; alternate functions are listed in the Alternate Function Table (6.5).
44 PD04 bidirectional General purpose I/O pin; alternate functions are listed in the Alternate Function Table (6.5).
45 PD03 bidirectional General purpose I/O pin; alternate functions are listed in the Alternate Function Table (6.5).
46 PD02 bidirectional General purpose I/O pin; alternate functions are listed in the Alternate Function Table (6.5).
47 PD01 bidirectional General purpose I/O pin; alternate functions are listed in the Alternate Function Table (6.5).
48 PD00 bidirectional General purpose I/O pin; alternate functions are listed in the Alternate Function Table (6.5).
49 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer SKYWORKS/SILICON LABS
Package QFN-48(6x6)
Category Radio Frequency Chip/Antenna
Pins 49

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Storage temperature range TSTG -50 150 °C 23
Voltage on any supply pin VDDMAX -0.3 3.8 V 23
Junction temperature TJMAX 125 °C -I grade 23
Voltage ramp rate on any supply pin VDDRAMPMAX 1 V / µs 23
Voltage on HFXO pins VHFXOPIN -0.3 1.2 V 23
DC voltage on RESETn pin VRESETn -0.3 3.8 V 23
DC voltage on RF pin RF2G4_IO VMAX2G4 -0.3 1.2 V 23
Total current into VDD power lines IVDDMAX 200 mA Source 23
Total current into VSS ground lines IVSSMAX 200 mA Sink 23
Current per I/O pin (sink) IIOMAX 50 mA Sink 23
Current per I/O pin (source) IIOMAX 50 mA Source 23
Current for all I/O pins (sink) IIOALLMAX 200 mA Sink 23
Current for all I/O pins (source) IIOALLMAX 200 mA Source 23
Operating ambient temperature range TA -40 125 °C -I temperature grade 24
DVDD supply voltage VDVDD 1.71 3 3.8 V EM0/1 24
AVDD supply voltage VAVDD 1.71 3 3.8 V AVDDBODEN=0 24
IOVDDx operating supply voltage VIOVDDx 1.71 3 3.8 V IOVDDxBODEN=0 24
RFVDD operating supply voltage VRFVDD 1.71 3 V max is VPAVDD 24
VREGVDD operating supply voltage VVREGVDD 2.2 3 3.8 V DC-DC in regulation 24
VREGVDD operating supply voltage VVREGVDD 1.8 3 3.8 V DC-DC in bypass 60 mA load 24
VREGVDD operating supply voltage VVREGVDD 1.71 3 3.8 V DC-DC not in use. DVDD externally shorted to VREGVDD 24
PAVDD operating supply voltage VPAVDD 1.71 3 3.8 V 24
DECOUPLE output capacitor CDECOUPLE 1 2.75 µF 1.0 µF ± 10% X8L capacitor used for performance characterization. 24
HCLK and SYSCLK frequency fHCLK 78 MHz VSCALE2, MODE = WS1 24
PCLK frequency fPCLK 40 MHz VSCALE2 or VSCALE1 24
External Clock Input fCLKIN 40 MHz VSCALE2 or VSCALE1, IOVDD ≥ 2.7 V 24
Input voltage range at VREGVDD pin VVREGVDD 2.2 3.8 V DCDC in regulation, ILOAD = ILOAD MAX, EM0/EM1 mode 26
Regulation DC accuracy ACCDC -2.5 4 % VVREGVDD ≥ 2.2 V, Steady state in EM0/EM1 mode or EM2/EM3 mode 26
Regulation total accuracy ACCTOT -5 7 % All error sources (including DC errors, overshoot, undershoot) 26
Nominal output capacitor CDCDC 4.7 10 µF 4.7 µF ± 10% X7R capacitor used for performance characterization 26
Resistance in bypass mode RBYP 0.45 0.69 Ω Bypass switch from VREGVDD to DVDD, VVREGVDD = 1.8 V 27
Powertrain PFET switch resistance RBYP 0.6 0.9 Ω Powertrain PFET switch from VREGVDD to VREGSW, VVREGVDD = 1.8 V 27
Supply monitor threshold accuracy VCMP_ACC -5 5 % Supply falling edge trip point 27
Thermal resistance junction to ambient, 48QFN ΘJA 27.7 °C/W JEDEC 2s2p, Still Air 28
Thermal resistance junction to board, 48QFN ΘJB 14.6 °C/W JEDEC 2s2p 28
Thermal resistance junction to case, 48QFN ΘJC 23 °C/W No Board, temperature controlled heat sink on top of package 28
Flash supply voltage during write or erase VFLASH 1.71 3.8 V 44
Flash data retention RETFLASH 10 years TA ≤ 125 °C 44
Flash erase cycles before failure ECFLASH 10000 cycles TA ≤ 125 °C 44
Program Time tPROG 41.9 43.4 45 µs TA = 25 °C, one word (32-bits) 44
Page Erase Time tPERASE 11.6 12.9 14 ms TA = 25 °C 44
Mass Erase Time tMERASE 144.3 150.5 156.8 ms TA = 25 °C, 1536kB 44
Program Current IWRITE 2.8 mA 44
Page Erase Current IPERASE 1.9 mA Page Erase 44
Mass Erase Current IMERASE 2 mA Mass Erase 44
RF tuning frequency range (TX) FRANGE 2400 2483.5 MHz 46
Crystal Frequency FHFXO 38 39 40 MHz see note 60
Supported crystal maximum ESR ESRHFXO 60 Ω Crystal Frequency = 39.0 MHz 60
HFRCO frequency accuracy FHFRCO_ACC -3 3 % For all production calibrated frequencies 62
FSRCO frequency FFSRCO 17.2 20 21.2 MHz 63
LFRCO frequency accuracy FLFRCO_ACC -3 3 % Normal mode 64
LFRCO frequency accuracy, precision mode FLFRCO_ACC -500 500 ppm Precision mode, across operating temperature range 64
ULFRCO oscillation frequency FULFRCO 0.944 1 1.095 kHz 64
Input low voltage VIL 0.3 V Any GPIO pin, max is 0.3 * IOVDD 65
Input high voltage VIH 0.7 V Any GPIO pin, min is 0.7 * IOVDD 65
Pull up/down resistance RPULL 35 44 55 kΩ Any GPIO pin 65
GPIO leakage current ILEAK_IO 200 nA MODEx = DISABLED, IOVDD = 3.8 V TA = 125 °C, All Other Pins 65

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
housing PC 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. 122

CAD (KiCad official)

  • Symbol: EFR32MG24B010F1536IM48-B
  • Footprint: Package_DFN_QFN:QFN-48-1EP_6x6mm_P0.4mm_EP4.2x4.2mm
  • 3D model: QFN-48(6x6), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.9 mm nominal QFN height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
  • 3D model files: efr32mg24b010f1536im48-b-etched.step / efr32mg24b010f1536im48-b-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); efr32mg24b010f1536im48-b.step / efr32mg24b010f1536im48-b.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: SKYWORKS/SILICON LABS datasheet (132 pp, sha256 c2555e008ba4c47a, retrieved 2026-10-31, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF