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EFR32MG22C224F512IM40-CR

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SILICON LABS RF Transceiver ICs, QFN-40-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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EFR32MG22C224F512IM40-CR

SILICON LABS · RF Transceiver ICs · QFN-40-EP(5x5)

EFR32MG22C224F512IM40-CR from SILICON LABS, in a QFN-40-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PC00 bidirectional General-purpose I/O pin on port PC00, with alternate functions GPIO.EM4WU6, GPIO.THMSW_EN and GPIO.THMSW_HAL listed in the Alternate Function Table.
2 PC01 bidirectional General-purpose I/O pin on port PC01 (no alternate functions listed in the Alternate Function Table).
3 PC02 bidirectional General-purpose I/O pin on port PC02 (no alternate functions listed in the Alternate Function Table).
4 PC03 bidirectional General-purpose I/O pin on port PC03 (no alternate functions listed in the Alternate Function Table).
5 PC04 bidirectional General-purpose I/O pin on port PC04 (no alternate functions listed in the Alternate Function Table).
6 PC05 bidirectional General-purpose I/O pin on port PC05, with alternate function GPIO.EM4WU7 listed in the Alternate Function Table.
7 PC06 bidirectional General-purpose I/O pin on port PC06 (no alternate functions listed in the Alternate Function Table).
8 PC07 bidirectional General-purpose I/O pin on port PC07, with alternate function GPIO.EM4WU8 listed in the Alternate Function Table.
9 HFXTAL_I input High-frequency crystal oscillator input for the HFXO (38.4 MHz crystal in the typical application circuit).
10 HFXTAL_O output High-frequency crystal oscillator output for the HFXO.
11 RESETn input Active-low reset input; the pin is internally pulled up to DVDD (pull-up resistance 35 to 55 kΩ, typ. 44 kΩ).
12 RFVDD power_in Radio power supply input.
13 RFVSS power_in Radio ground.
14 RF2G4_IO bidirectional Single-ended 2.4 GHz RF input/output connected to the antenna interface through the external matching network.
15 PAVDD power_in Power amplifier (PA) power supply.
16 PB04 bidirectional General-purpose I/O pin on port PB04 (no alternate functions listed in the Alternate Function Table).
17 PB03 bidirectional General-purpose I/O pin on port PB03, with alternate function GPIO.EM4WU4 listed in the Alternate Function Table.
18 PB02 bidirectional General-purpose I/O pin on port PB02 (no alternate functions listed in the Alternate Function Table).
19 PB01 bidirectional General-purpose I/O pin on port PB01, with alternate function GPIO.EM4WU3 listed in the Alternate Function Table.
20 PB00 bidirectional General-purpose I/O pin on port PB00, with alternate function IADC0.VREFN listed in the Alternate Function Table.
21 PA00 bidirectional General-purpose I/O pin on port PA00, with alternate function IADC0.VREFP listed in the Alternate Function Table.
22 PA01 bidirectional General-purpose I/O pin on port PA01, with alternate function GPIO.SWCLK listed in the Alternate Function Table.
23 PA02 bidirectional General-purpose I/O pin on port PA02, with alternate function GPIO.SWDIO listed in the Alternate Function Table.
24 PA03 bidirectional General-purpose I/O pin on port PA03, with alternate functions GPIO.SWV, GPIO.TDO and GPIO.TRACEDATA0 listed in the Alternate Function Table.
25 PA04 bidirectional General-purpose I/O pin on port PA04, with alternate functions GPIO.TDI and GPIO.TRACECLK listed in the Alternate Function Table.
26 PA05 bidirectional General-purpose I/O pin on port PA05, with alternate function GPIO.EM4WU0 listed in the Alternate Function Table.
27 PA06 bidirectional General-purpose I/O pin on port PA06 (no alternate functions listed in the Alternate Function Table).
28 PA07 bidirectional General-purpose I/O pin on port PA07 (no alternate functions listed in the Alternate Function Table).
29 PA08 bidirectional General-purpose I/O pin on port PA08 (no alternate functions listed in the Alternate Function Table).
30 DECOUPLE passive Decouple output for the on-chip voltage regulator; an external decoupling capacitor is required at this pin.
31 VREGSW output DC-DC regulator switching node.
32 VREGVDD power_in DC-DC regulator input supply.
33 VREGVSS power_in DC-DC ground.
34 DVDD power_in Digital power supply; the DVDD BOD supply-rising threshold is 1.64 to 1.71 V (typ. 1.71 V) in EM0 and EM1.
35 AVDD power_in Analog power supply for the IADC; main analog supply range is 1.71 to 3.8 V.
36 IOVDD power_in I/O power supply; GPIO input thresholds are proportional to IOVDD.
37 PD03 bidirectional General-purpose I/O pin on port PD03 (no alternate functions listed in the Alternate Function Table).
38 PD02 bidirectional General-purpose I/O pin on port PD02, with alternate function GPIO.EM4WU9 listed in the Alternate Function Table.
39 PD01 bidirectional General-purpose I/O pin on port PD01, with alternate functions LFXO.LFXTAL_I and LFXO.LF_EXTCLK listed in the Alternate Function Table.
40 PD00 bidirectional General-purpose I/O pin on port PD00, with alternate function LFXO.LFXTAL_O listed in the Alternate Function Table.
41 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer SILICON LABS
Package QFN-40-EP(5x5)
Category RF & Radio
Pins 41

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Storage temperature range TSTG -50 150 °C 18
Voltage on any supply pin VDDMAX -0.3 3.8 V 18
Junction temperature TJMAX 125 °C -I grade 18
Voltage ramp rate on any supply pin VDDRAMPMAX 1 V / µs 18
Voltage on HFXO pins VHFXOPIN -0.3 1.4 V 18
DC voltage on RESETn pin VRESETn -0.3 3.8 V 18
Total current into VDD power lines IVDDMAX 200 mA Source 18
Total current into VSS ground lines IVSSMAX 200 mA Sink 18
Current per I/O pin IIOMAX 50 mA Sink 18
Current for all I/O pins IIOALLMAX 200 mA Sink 18
Operating ambient temperature range TA -40 125 °C -I temperature grade 19
DVDD supply voltage VDVDD 1.71 3 3.8 V EM0/1 19
AVDD supply voltage VAVDD 1.71 3 3.8 V 19
IOVDDx operating supply voltage (All IOVDD pins) VIOVDDx 1.71 3 3.8 V 19
PAVDD operating supply voltage VPAVDD 1.71 3 3.8 V 19
VREGVDD operating supply voltage VVREGVDD 2.2 3 3.8 V DC-DC in regulation 19
VREGVDD operating supply voltage VVREGVDD 1.8 3 3.8 V DC-DC in bypass 60 mA load 19
VREGVDD operating supply voltage VVREGVDD 1.71 3 3.8 V DC-DC not in use. DVDD externally shorted to VREGVDD 19
RFVDD operating supply voltage VRFVDD 1.71 3 V 19
HCLK and SYSCLK frequency fHCLK 76.8 MHz VSCALE2, MODE = WS1 19
HCLK and SYSCLK frequency fHCLK 40 MHz VSCALE2, MODE = WS0 19
PCLK frequency fPCLK 50 MHz VSCALE2 19
PCLK frequency fPCLK 40 MHz VSCALE1 19
EM01 Group A clock frequency fEM01GRPACLK 76.8 MHz VSCALE2 19
EM01 Group A clock frequency fEM01GRPACLK 40 MHz VSCALE1 19
Regulation DC accuracy ACCDC -2.5 3.3 % VVREGVDD ≥ 2.2 V, Steady state in EM0/EM1 mode or EM2/EM3 mode 21
Regulation total accuracy ACCTOT -5 7 % With mode transitions between EM0/EM1 and EM2/EM3 modes 21
Output load current ILOAD 60 mA EM0/EM1 mode, DCDC in regulation 21
Output load current ILOAD 5 mA EM2/EM3 mode, DCDC in regulation 21
Nominal output capacitor CDCDC 4.7 10 µF X7R capacitor used for performance characterization 21
Resistance in bypass mode RBYP 1.75 3 Ω Bypass switch from VREGVDD to DVDD, VVREGVDD = 1.8 V 21
Supply monitor threshold programming range VCMP_RNG 2 2.3 V Programmable in 0.1 V steps 21
RF level above which RFSENSE will detect signal THRESTRIG -28 dBm Threshold set to -34 dBm 35
RF level above which RFSENSE will detect signal THRESTRIG -19 dBm Threshold set to -22 dBm 35
RF level below which RFSENSE will not detect signal THRESNOTRIG -40 dBm Threshold set to -34 dBm 35
RF level below which RFSENSE will not detect signal THRESNOTRIG -26 dBm Threshold set to -22 dBm 35
Sensitivity in selective OOK mode SENSOOK -28 dBm Sensitivity for >90% probability of OOK detection, threshold set to -34 dBm 35
Sensitivity in selective OOK mode SENSOOK -19 dBm Sensitivity for >90% probability of OOK detection, threshold set to -22 dBm 35
Flash Supply voltage during write or erase VFLASH 1.71 3.8 V 33
Flash erase cycles before failure ECFLASH 10000 cycles TA ≤ 125 °C 33
Flash data retention RETFLASH 10 years TA ≤ 125 °C 33
Program Time tPROG 42.1 44 45.6 uSec one word (32-bits) 33
Page Erase Time tPERASE 11.4 12.9 14.4 ms 33
Mass Erase Time tMERASE 11.7 13 14.3 ms Erases all of User Code area 33
Program Current IPROG 1.45 mA 33
RF tuning frequency range FRANGE 2400 2483.5 MHz 36
Frequency Accuracy FHFRCO_ACC -3 3 % For all production calibrated frequencies 51
FSRCO frequency FFSRCO 17.2 20 21.2 MHz 52
Frequency accuracy FLFRCO_ACC -3 3 % Normal mode 53
Frequency accuracy FLFRCO_ACC -500 500 ppm Precision mode, across operating temperature range 53
Oscillation Frequency FULFRCO 0.944 1 1.095 kHz 53
Pull up/down resistance RPULL 35 44 55 kΩ Any GPIO pin. Pull-up to IOVDD: MODEn = DISABLE, DOUT=1. Pull-down to VSS: MODEn = WIREDORPULLDOWN, DOUT = 0 54
Leakage current ILEAK_IO 200 nA MODEx = DISABLED, IOVDD = 3.8 V, TA = 125 °C; pins other than PA00, PA03, PB00, PC03, PC04, PD00 54
Thermal Resistance, Junction to Ambient, QFN40 (5x5mm) Package THETAJA_QFN40_5X5 32.6 °C/W 4-Layer PCB, Natural Convection 24

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
housing PC 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. 86

CAD (KiCad official)

  • Symbol: EFR32MG22C224F512IM40-CR
  • Footprint: Package_DFN_QFN:QFN-40-1EP_5x5mm_P0.4mm_EP3.6x3.6mm
  • 3D model: QFN-40-EP(5x5) (KiCad packages3D, STEP)
  • 3D model files: efr32mg22c224f512im40-cr-etched.step / efr32mg22c224f512im40-cr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); efr32mg22c224f512im40-cr.step / efr32mg22c224f512im40-cr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: SILICON LABS datasheet (101 pp, sha256 acb5d9e330431af4, retrieved 2026-10-29, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF