component

EFR32MG21A020F1024IM32-BR

Public Made by Adom

by adom

SKYWORKS SILICON LABS RF Transceiver ICs, QFN-32-EP(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentrf and wirelessefr32mg21a020f1024im32-brfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
efr32mg21a020f1024im32-br / README.md
History Download
Ray Publish 0.1.0 e7384b0 7d ago

EFR32MG21A020F1024IM32-BR

SKYWORKS SILICON LABS · RF Transceiver ICs · QFN-32-EP(4x4)

EFR32MG21A020F1024IM32-BR from SKYWORKS SILICON LABS, in a QFN-32-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PC00 bidirectional General-purpose I/O pin on Port C; Table 6.2 lists its alternate function as GPIO.EM4WU6 (EM4 wakeup).
2 PC01 bidirectional General-purpose I/O pin on Port C.
3 PC02 bidirectional General-purpose I/O pin on Port C.
4 PC03 bidirectional General-purpose I/O pin on Port C.
5 PC04 bidirectional General-purpose I/O pin on Port C.
6 PC05 bidirectional General-purpose I/O pin on Port C; Table 6.2 lists its alternate function as GPIO.EM4WU7 (EM4 wakeup).
7 HFXTAL_I input High-frequency crystal oscillator input for the HFXO.
8 HFXTAL_O output High-frequency crystal oscillator output for the HFXO.
9 RESETn input Active-low reset pin; its input thresholds are proportional to DVDD and its internal pull-up connects to DVDD (Section 4.1.9 note 2).
10 RFVDD power_in Radio power supply.
11 RFVSS power_in Radio ground.
12 RF2G4_IO2 bidirectional 2.4 GHz single-ended RF input/output; one of two antenna pins that interface to the LNAs and PAs, with integrated switches selecting the active path (Section 3.2.1).
13 RF2G4_IO1 bidirectional 2.4 GHz single-ended RF input/output; one of two antenna pins that interface to the LNAs and PAs, with integrated switches selecting the active path (Section 3.2.1).
14 PAVDD power_in Power amplifier (PA) power supply.
15 PB01 bidirectional General-purpose I/O pin on Port B; Table 6.2 lists its alternate function as GPIO.EM4WU3 (EM4 wakeup).
16 PB00 bidirectional General-purpose I/O pin on Port B.
17 PA00 bidirectional General-purpose I/O pin on Port A.
18 PA01 bidirectional General-purpose I/O pin on Port A; Table 6.2 lists its alternate function as GPIO.SWCLK (serial wire clock).
19 PA02 bidirectional General-purpose I/O pin on Port A; Table 6.2 lists its alternate function as GPIO.SWDIO (serial wire data).
20 PA03 bidirectional General-purpose I/O pin on Port A; Table 6.2 lists alternate functions as GPIO.SWV, GPIO.TDO and GPIO.TRACEDATA0.
21 PA04 bidirectional General-purpose I/O pin on Port A; Table 6.2 lists alternate functions as GPIO.TDI and GPIO.TRACECLK.
22 PA05 bidirectional General-purpose I/O pin on Port A; Table 6.2 lists its alternate function as GPIO.EM4WU0 (EM4 wakeup).
23 PA06 bidirectional General-purpose I/O pin on Port A.
24 DECOUPLE passive Decouple output for the on-chip voltage regulator; an external decoupling capacitor is required at this pin.
25 DVDD power_in Digital power supply; DVDD BOD threshold is 1.62 V (falling) to 1.71 V (rising) in EM0 and EM1 (Section 4.1.13.1).
26 AVDD power_in Analog power supply; main analog supply range is 1.71 V to 3.8 V for the ADC (Table 4.29).
27 IOVDD power_in Digital I/O power supply; GPIO input thresholds are proportional to IOVDD (Section 4.1.9 note 1).
28 PD04 bidirectional General-purpose I/O pin on Port D.
29 PD03 bidirectional General-purpose I/O pin on Port D.
30 PD02 bidirectional General-purpose I/O pin on Port D; Table 6.2 lists its alternate function as GPIO.EM4WU9 (EM4 wakeup).
31 PD01 bidirectional General-purpose I/O pin on Port D; Table 6.2 lists alternate functions as LFXO.LFXTAL_I and LFXO.LF_EXTCLK.
32 PD00 bidirectional General-purpose I/O pin on Port D; Table 6.2 lists its alternate function as LFXO.LFXTAL_O.
33 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer SKYWORKS SILICON LABS
Package QFN-32-EP(4x4)
Category RF And Wireless
Pins 33

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Storage temperature range TSTG -50 150 °C 14
Junction temperature TJMAX 135 °C I grade 14
Voltage on any supply pin VDDMAX -0.3 3.8 V 14
Voltage ramp rate on any supply pin VDDRAMPMAX 1 V / µs 14
Voltage on HFXO pins VHFXOPIN -0.3 1.2 V 14
DC voltage on any GPIO pin VDIGPIN -0.3 V Printed max is VIOVDD + 0.3 (expression, not a number) 14
Input RF level on pins RF2G4_IO1 and RF2G4_IO2 PRFMAX2G4 10 dBm 14
Absolute voltage on RF pins RF2G4_IOx VMAX2G4 -0.3 V Printed max is VPAVDD (expression, not a number) 14
Total current into VDD power lines IVDDMAX 200 mA Source 14
Total current into VSS ground lines IVSSMAX 200 mA Sink 14
Current per I/O pin IIOMAX 50 mA Sink 14
Current for all I/O pins IIOALLMAX 200 mA Sink 14
Operating ambient temperature range TA -40 125 °C -I temperature grade 15
DVDD supply voltage VDVDD 1.71 3 3.8 V EM0/1 15
AVDD supply voltage VAVDD 1.71 3 3.8 V 15
IOVDDx operating supply voltage (All IOVDD pins) VIOVDDx 1.71 3 3.8 V All IOVDD pins 15
PAVDD operating supply voltage VPAVDD 1.71 3 3.8 V 15
RFVDD operating supply voltage VRFVDD 1.71 3 V Printed max is VPAVDD (expression, not a number) 15
DECOUPLE output capacitor CDECOUPLE 0.75 1 2.75 µF 15
HCLK and Core frequency fHCLK 80 MHz MODE = WS1, RAMWSEN = 1 15
HCLK and Core frequency fHCLK 50 MHz MODE = WS1, RAMWSEN = 0 15
HCLK and Core frequency fHCLK 39 MHz MODE = WS0, RAMWSEN = 0 15
PCLK frequency fPCLK 50 MHz 15
EM01 Group A clock frequency fEM01GRPACLK 80 MHz 15
HCLK Radio frequency fHCLKRADIO 38 38.4 40 MHz 15
Flash erase cycles before failure ECFLASH 10000 cycles TA ≤ 125 °C 37
Flash data retention RETFLASH 10 years TA ≤ 125 °C 37
Program time tPROG 40.2 44 47.9 uSec one word (32-bits) 37
Program time, average per word tPROG 9.97 10.9 11.9 uSec average per word over 128 words 37
Page Erase Time tPERASE 11.6 12.7 13.9 ms 37
Mass Erase Time tMERASE 11.7 12.8 14.1 ms 37
Page Erase Current IERASE 2.13 mA TA = 25 °C 37
Program Current IWRITE 2.73 mA TA = 25 °C 37
Mass Erase Current IMERASE 2.3 mA TA = 25 °C 37
Flash Supply voltage during write or erase VFLASH 1.71 3.8 V 37
Supported crystal equivalent series resistance (ESR) ESRHFXO_38M4 40 Ω 38.4 MHz, CL = 10 pF 39
Supported crystal equivalent series resistance (ESR) ESRLFXO 80 kΩ GAIN=0 40
Supported crystal equivalent series resistance (ESR) ESRLFXO 100 kΩ GAN=1 to 3 40
Supported range of crystal load capacitance CLFXO_CL 4 6 pF GAIN = 0 40
Supported range of crystal load capacitance CLFXO_CL 6 10 pF GAIN = 1 40
Supported range of crystal load capacitance CLFXO_CL 10 12.5 pF GAIN = 2 40
Supported range of crystal load capacitance CLFXO_CL 12.5 18 pF GAIN = 3 40
Frequency Accuracy FHFRCO_ACC -3 3 % For all production calibrated frequencies 41
FSRCO frequency FREQFSRCO 17.2 20 21.2 MHz 42
Nominal oscillation frequency (LFRCO) FLFRCO 31.785 32.768 33.751 kHz 43
Oscillation Frequency (ULFRCO) FULFRCO 0.944 1 1.095 kHz 43
RF tuning frequency range FRANGE 2400 2483.5 MHz 22
Thermal Resistance Junction to Ambient QFN32 (4x4mm) Package THETAJA_QFN32_4X4 94.3 °C/W 2-Layer PCB, Natural Convection 16
Thermal Resistance Junction to Ambient QFN32 (4x4mm) Package THETAJA_QFN32_4X4 35.4 °C/W 4-Layer PCB, Natural Convection 16
Thermal Resistance Junction to Case QFN32 (4x4mm) Package THETAJC_QFN32_4X4 36.3 °C/W 2-Layer PCB, Natural Convection 16
Thermal Resistance Junction to Case QFN32 (4x4mm) Package THETAJC_QFN32_4X4 23.5 °C/W 4-Layer PCB, Natural Convection 16

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
housing PC 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. 70

CAD (KiCad official)

  • Symbol: EFR32MG21A020F1024IM32-BR
  • Footprint: Package_DFN_QFN:QFN-32-1EP_4x4mm_P0.4mm_EP2.9x2.9mm
  • 3D model: QFN-32-EP(4x4) (KiCad packages3D, STEP)
  • 3D model files: efr32mg21a020f1024im32-br-etched.step / efr32mg21a020f1024im32-br-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); efr32mg21a020f1024im32-br.step / efr32mg21a020f1024im32-br.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: SKYWORKS SILICON LABS datasheet (76 pp, sha256 cf5d9c7d572ffdb5, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF