EFR32BG24B220F1024IM48-B from SKYWORKS/SILICON LABS, in a QFN-48(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	PC00	bidirectional	General-purpose I/O on port PC00; Table 6.4 lists GPIO.EM4WU6 as an alternate function.
2	PC01	bidirectional	General-purpose I/O on port PC01; Table 6.4 lists GPIO.EFP_TX_SDA as an alternate function.
3	PC02	bidirectional	General-purpose I/O on port PC02; Table 6.4 lists GPIO.EFP_TX_SCL as an alternate function.
4	PC03	bidirectional	General-purpose I/O on port PC03 with output state retention and asynchronous interrupt support per the Feature List.
5	PC04	bidirectional	General-purpose I/O on port PC04 with output state retention and asynchronous interrupt support per the Feature List.
6	PC05	bidirectional	General-purpose I/O on port PC05; Table 6.4 lists GPIO.EFP_INT and GPIO.EM4WU7 as alternate functions.
7	PC06	bidirectional	General-purpose I/O on port PC06 with output state retention and asynchronous interrupt support per the Feature List.
8	PC07	bidirectional	General-purpose I/O on port PC07; Table 6.4 lists GPIO.EM4WU8 as an alternate function.
9	PC08	bidirectional	General-purpose I/O on port PC08 with output state retention and asynchronous interrupt support per the Feature List.
10	PC09	bidirectional	General-purpose I/O on port PC09; Table 6.4 lists GPIO.THMSW_EN and GPIO.THMSW_HALFSWITCH as alternate functions.
11	HFXTAL_I	input	High-frequency crystal oscillator input (HFXO).
12	HFXTAL_O	output	High-frequency crystal oscillator output (HFXO).
13	RESETn	input	Active-low reset; internally pulled up to DVDD and requires a low time of at least 100 ns to ensure a pin reset.
14	RFVDD	power_in	Radio power supply.
15	RFVSS	power_in	Radio ground.
16	RF2G4_IO	bidirectional	2.4 GHz RF input/output (single-ended antenna interface).
17	PAVDD	power_in	Power amplifier (PA) power supply.
18	PB05	bidirectional	General-purpose I/O on port PB05.
19	PB04	bidirectional	General-purpose I/O on port PB04.
20	PB03	bidirectional	General-purpose I/O on port PB03; Table 6.4 lists GPIO.EM4WU4 and VDAC1.VDAC_CH1_MAIN_OUTPUT as alternate functions.
21	PB02	bidirectional	General-purpose I/O on port PB02; Table 6.4 lists VDAC1.VDAC_CH0_MAIN_OUTPUT as an alternate function.
22	PB01	bidirectional	General-purpose I/O on port PB01; Table 6.4 lists GPIO.EM4WU3 and VDAC0.VDAC_CH1_MAIN_OUTPUT as alternate functions.
23	PB00	bidirectional	General-purpose I/O on port PB00; Table 6.4 lists VDAC0.VDAC_CH0_MAIN_OUTPUT as an alternate function.
24	VREFN	input	Dedicated ADC VREF negative input.
25	VREFP	input	Dedicated ADC VREF positive input; external reference voltage range is 1.0 V to AVDD per the IADC specification.
26	PA00	bidirectional	General-purpose I/O on port PA00; Table 6.4 lists IADC0.VREFP as an alternate function.
27	PA01	bidirectional	General-purpose I/O on port PA01; Table 6.4 lists GPIO.SWCLK as an alternate function.
28	PA02	bidirectional	General-purpose I/O on port PA02; Table 6.4 lists GPIO.SWDIO as an alternate function.
29	PA03	bidirectional	General-purpose I/O on port PA03; Table 6.4 lists GPIO.SWV, GPIO.TDO and GPIO.TRACEDATA0 as alternate functions.
30	PA04	bidirectional	General-purpose I/O on port PA04; Table 6.4 lists GPIO.TDI and GPIO.TRACECLK as alternate functions.
31	PA05	bidirectional	General-purpose I/O on port PA05; Table 6.4 lists GPIO.TRACEDATA1 and GPIO.EM4WU0 as alternate functions.
32	PA06	bidirectional	General-purpose I/O on port PA06; Table 6.4 lists GPIO.TRACEDATA2 as an alternate function.
33	PA07	bidirectional	General-purpose I/O on port PA07; Table 6.4 lists GPIO.TRACEDATA3 as an alternate function.
34	PA08	bidirectional	General-purpose I/O on port PA08 with output state retention and asynchronous interrupt support per the Feature List.
35	PA09	bidirectional	General-purpose I/O on port PA09 with output state retention and asynchronous interrupt support per the Feature List.
36	DECOUPLE	passive	Decouple output for the on-chip voltage regulator; an external decoupling capacitor is required at this pin.
37	VREGSW	output	DCDC regulator switching node.
38	VREGVDD	power_in	DCDC regulator input supply.
39	VREGVSS	power_in	DCDC ground.
40	DVDD	power_in	Digital power supply; the DVDD brown-out detector rising threshold is 1.67 V (typ) to 1.71 V (max) per Table 4.36.
41	AVDD	power_in	Analog power supply; the IADC main analog supply range is 1.71 V to 3.8 V.
42	IOVDD	power_in	I/O power supply; GPIO input thresholds are proportional to IOVDD.
43	PD05	bidirectional	General-purpose I/O on port PD05; Table 6.4 lists GPIO.EM4WU10 as an alternate function.
44	PD04	bidirectional	General-purpose I/O on port PD04 with output state retention and asynchronous interrupt support per the Feature List.
45	PD03	bidirectional	General-purpose I/O on port PD03 with output state retention and asynchronous interrupt support per the Feature List.
46	PD02	bidirectional	General-purpose I/O on port PD02; Table 6.4 lists GPIO.EM4WU9 as an alternate function.
47	PD01	bidirectional	General-purpose I/O on port PD01; Table 6.4 lists LFXO.LFXTAL_I and LFXO.LF_EXTCLK as alternate functions.
48	PD00	bidirectional	General-purpose I/O on port PD00; Table 6.4 lists LFXO.LFXTAL_O as an alternate function.
49	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	SKYWORKS/SILICON LABS
Package	QFN-48(6x6)
Category	Radio Frequency Chip/Antenna
Pins	49

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Storage temperature range	TSTG	-50		150	°C		23
Voltage on any supply pin	VDDMAX	-0.3		3.8	V		23
Junction temperature	TJMAX			125	°C	-I grade	23
Voltage ramp rate on any supply pin	VDDRAMPMAX			1	V/µs		23
Voltage on HFXO pins	VHFXOPIN	-0.3		1.2	V		23
DC voltage on any GPIO pin	VDIGPIN	-0.3			V	max printed as VIOVDD + 0.3	23
DC voltage on RESETn pin	VRESETn	-0.3		3.8	V		23
DC voltage on RF pin RF2G4_IO	VMAX2G4	-0.3		1.2	V		23
Total current into VDD power lines	IVDDMAX			200	mA	Source	23
Total current into VSS ground lines	IVSSMAX			200	mA	Sink	23
Current per I/O pin	IIOMAX			50	mA	Sink	23
Current for all I/O pins	IIOALLMAX			200	mA	Sink	23
Thermal resistance, junction to ambient (48QFN 6x6mm)	ΘJA		27.7		°C/W	JEDEC High Thermal Cond. (2s2p); Still Air	28
Thermal resistance, junction to board (48QFN 6x6mm)	ΘJB		14.6		°C/W	JEDEC High Thermal Cond. (2s2p)	28
Thermal resistance, junction to top center (48QFN 6x6mm)	ѰJT		0.69		°C/W	JEDEC High Thermal Cond. (2s2p)	28
Thermal resistance, junction to board (48QFN 6x6mm)	ѰJB		11.85		°C/W	JEDEC High Thermal Cond. (2s2p)	28
Thermal resistance, junction to case (48QFN 6x6mm)	ΘJC		23		°C/W	Temperature controlled heat sink on top of package, all other sides insulated	28
Operating ambient temperature range	TA	-40		125	°C	-I temperature grade	24
DVDD supply voltage	VDVDD	1.71	3	3.8	V	EM0/1	24
AVDD supply voltage	VAVDD	1.71	3	3.8	V	AVDDBODEN=0	24
IOVDDx operating supply voltage (All IOVDD pins)	VIOVDDx	1.71	3	3.8	V	IOVDDxBODEN=0	24
RFVDD operating supply voltage	VRFVDD	1.71	3		V	max printed as VPAVDD	24
VREGVDD operating supply voltage	VVREGVDD	2.2	3	3.8	V	DC-DC in regulation	24
VREGVDD operating supply voltage	VVREGVDD	1.8	3	3.8	V	DC-DC in bypass 60 mA load	24
VREGVDD operating supply voltage	VVREGVDD	1.71	3	3.8	V	DC-DC not in use. DVDD externally shorted to VREGVDD	24
PAVDD operating supply voltage	VPAVDD	1.71	3	3.8	V		24
DECOUPLE output capacitor	CDECOUPLE	1		2.75	µF	1.0 µF ± 10% X8L capacitor used for performance characterization	24
HCLK and SYSCLK frequency	fHCLK			78	MHz	VSCALE2, MODE = WS1	24
HCLK and SYSCLK frequency	fHCLK			40	MHz	VSCALE2, MODE = WS0	24
HCLK and SYSCLK frequency	fHCLK			20	MHz	VSCALE1, MODE = WS0	24
Input voltage range at VREGVDD pin	VVREGVDD	2.2		3.8	V	DCDC in regulation, ILOAD = ILOAD MAX, EM0/EM1 mode	26
Input voltage range at VREGVDD pin	VVREGVDD	1.8		3.8	V	DCDC in regulation, ILOAD = 5 mA, EM0/EM1 or EM2/EM3 mode	26
Input voltage range at VREGVDD pin	VVREGVDD	1.9		3.8	V	Bypass Mode, ILOAD ≤ 120 mA	26
Regulation DC accuracy	ACCDC	-2.5		4	%	VVREGVDD ≥ 2.2 V, Steady state in EM0/EM1 mode or EM2/EM3 mode	26
Regulation total accuracy	ACCTOT	-5		7	%	All error sources (including DC errors, overshoot, undershoot)	26
Output load current	ILOAD			60	mA	EM0/EM1 mode, DCDC in regulation, DCDC_EM01CTRL0.IPKVAL = 9, Radio not transmitting	26
Output load current	ILOAD			36	mA	EM0/EM1 mode, DCDC in regulation, Radio in receive mode	26
Output load current	ILOAD			120	mA	EM0/EM1 mode, DCDC in regulation, Radio transmitting	26
Output load current	ILOAD			5	mA	EM2/EM3 mode, DCDC in regulation	26
Nominal output capacitor	CDCDC		4.7	10	µF	4.7 µF ± 10% X7R capacitor used for performance characterization	26
Resistance in bypass mode	RBYP		0.45	0.69	Ω	Bypass switch from VREGVDD to DVDD, VVREGVDD = 1.8 V	27
Powertrain PFET switch resistance			0.6	0.9	Ω	PFET switch from VREGVDD to VREGSW, VVREGVDD = 1.8 V	27
Supply monitor threshold programming range	VCMP_RNG	2		2.3	V	Programmable in 0.1 V steps	27
Supply monitor threshold accuracy	VCMP_ACC	-5		5	%	Supply falling edge trip point	27
Crystal Frequency	FHFXO	38	39	40	MHz	see note 1	60
RF tuning frequency range	FRANGE	2400		2483.5	MHz		46
FSRCO frequency	FFSRCO	17.2	20	21.2	MHz		63
Oscillation Frequency (ULFRCO)	FULFRCO	0.944	1	1.095	kHz		64
Frequency Accuracy (HFRCO)	FHFRCO_ACC	-3		3	%	For all production calibrated frequencies	62
Leakage current	ILEAK_IO			200	nA	MODEx = DISABLED, IOVDD = 3.8 V TA = 125 °C, All Other Pins	65
Pull up/down resistance	RPULL	35	44	55	kΩ	Any GPIO pin; pull-up to IOVDD (MODEn = DISABLE, DOUT = 1) or pull-down to VSS (MODEn = WIREDORPULLDOWN, DOUT = 0)	65
Pull up/down resistance (RESETn)	RPULL	35	44	55	kΩ	RESETn pin, pull-up to DVDD	65

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part	Material	Colour / plating	Datasheet says	Page
housing	PC		4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.	120

CAD (KiCad official)

Symbol: EFR32BG24B220F1024IM48-B
Footprint: Package_DFN_QFN:QFN-48-1EP_6x6mm_P0.4mm_EP4.2x4.2mm
3D model: QFN-48(6x6), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.9 mm nominal QFN height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
3D model files: efr32bg24b220f1024im48-b-etched.step / efr32bg24b220f1024im48-b-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); efr32bg24b220f1024im48-b.step / efr32bg24b220f1024im48-b.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: SKYWORKS/SILICON LABS datasheet (129 pp, sha256 df98b018cb011d3f, retrieved 2026-10-30, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

EFR32BG24B220F1024IM48-B

Verified EFR32BG24B220F1024IM48-B

Verification log 1 record

3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

README