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EFR32BG24B110F1536IM48-BR

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SKYWORKS SILICON LABS RF Transceiver ICs, QFN-48(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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EFR32BG24B110F1536IM48-BR

SKYWORKS SILICON LABS · RF Transceiver ICs · QFN-48(6x6)

EFR32BG24B110F1536IM48-BR from SKYWORKS SILICON LABS, in a QFN-48(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PC00 bidirectional General purpose I/O pin on port PC00 with output state retention and asynchronous interrupts.
2 PC01 bidirectional General purpose I/O pin on port PC01 with output state retention and asynchronous interrupts.
3 PC02 bidirectional General purpose I/O pin on port PC02 with output state retention and asynchronous interrupts.
4 PC03 bidirectional General purpose I/O pin on port PC03 with output state retention and asynchronous interrupts.
5 PC04 bidirectional General purpose I/O pin on port PC04 with output state retention and asynchronous interrupts.
6 PC05 bidirectional General purpose I/O pin on port PC05 with output state retention and asynchronous interrupts.
7 PC06 bidirectional General purpose I/O pin on port PC06 with output state retention and asynchronous interrupts.
8 PC07 bidirectional General purpose I/O pin on port PC07 with output state retention and asynchronous interrupts.
9 PC08 bidirectional General purpose I/O pin on port PC08 with output state retention and asynchronous interrupts.
10 PC09 bidirectional General purpose I/O pin on port PC09 with output state retention and asynchronous interrupts.
11 HFXTAL_I input High frequency crystal oscillator input, used with the 39.0 MHz crystal in the typical application circuit.
12 HFXTAL_O output High frequency crystal oscillator output, used with the 39.0 MHz crystal in the typical application circuit.
13 RESETn input Active-low reset pin, internally pulled up to DVDD (35 to 55 kΩ, 44 kΩ typical), with a minimum low time of 100 ns to ensure a pin reset.
14 RFVDD power_in Radio power supply; the device operates from a single 1.71 V to 3.8 V supply.
15 RFVSS power_in Radio ground.
16 RF2G4_IO passive 2.4 GHz RF input/output, a single-ended antenna interface pin.
17 PAVDD power_in Power amplifier (PA) power supply, which may be fed from the DC-DC output in typical applications.
18 PB03 bidirectional General purpose I/O pin on port PB03 with output state retention and asynchronous interrupts.
19 PB02 bidirectional General purpose I/O pin on port PB02 with output state retention and asynchronous interrupts.
20 PB01 bidirectional General purpose I/O pin on port PB01 with output state retention and asynchronous interrupts.
21 PB00 bidirectional General purpose I/O pin on port PB00 with output state retention and asynchronous interrupts.
22 VREFN input Dedicated ADC VREF negative input for the external reference, whose range is 1.0 V to AVDD.
23 AIN3 passive Dedicated ADC analog input 3, with the maximum allowable input voltage limited to AVDD.
24 AIN2 passive Dedicated ADC analog input 2, with the maximum allowable input voltage limited to AVDD.
25 AIN1 passive Dedicated ADC analog input 1, with the maximum allowable input voltage limited to AVDD.
26 AIN0 passive Dedicated ADC analog input 0, with the maximum allowable input voltage limited to AVDD.
27 VREFP input Dedicated ADC VREF positive input for the external reference, whose range is 1.0 V to AVDD.
28 PA00 bidirectional General purpose I/O pin on port PA00 with output state retention and asynchronous interrupts.
29 PA01 bidirectional General purpose I/O pin on port PA01 with output state retention and asynchronous interrupts.
30 PA02 bidirectional General purpose I/O pin on port PA02 with output state retention and asynchronous interrupts.
31 PA03 bidirectional General purpose I/O pin on port PA03 with output state retention and asynchronous interrupts.
32 PA04 bidirectional General purpose I/O pin on port PA04 with output state retention and asynchronous interrupts.
33 PA05 bidirectional General purpose I/O pin on port PA05 with output state retention and asynchronous interrupts.
34 PA06 bidirectional General purpose I/O pin on port PA06 with output state retention and asynchronous interrupts.
35 PA07 bidirectional General purpose I/O pin on port PA07 with output state retention and asynchronous interrupts.
36 DECOUPLE passive Decouple output for the on-chip voltage regulator; an external decoupling capacitor is required at this pin.
37 VREGSW output DC-DC regulator switching node.
38 VREGVDD power_in DC-DC regulator input supply.
39 VREGVSS power_in DC-DC converter ground.
40 DVDD power_in Digital power supply; DVDD is the supply for the digital domain and the reference for the RESETn pull-up.
41 AVDD power_in Analog power supply; the main analog supply range for the IADC is 1.71 V to 3.8 V.
42 IOVDD power_in I/O power supply; GPIO input thresholds are proportional to IOVDD.
43 PD05 bidirectional General purpose I/O pin on port PD05 with output state retention and asynchronous interrupts.
44 PD04 bidirectional General purpose I/O pin on port PD04 with output state retention and asynchronous interrupts.
45 PD03 bidirectional General purpose I/O pin on port PD03 with output state retention and asynchronous interrupts.
46 PD02 bidirectional General purpose I/O pin on port PD02 with output state retention and asynchronous interrupts.
47 PD01 bidirectional General purpose I/O pin on port PD01 with output state retention and asynchronous interrupts.
48 PD00 bidirectional General purpose I/O pin on port PD00 with output state retention and asynchronous interrupts.
49 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer SKYWORKS SILICON LABS
Package QFN-48(6x6)
Category RF And Wireless
Pins 49

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Storage temperature range TSTG -50 150 °C 23
Voltage on any supply pin VDDMAX -0.3 3.8 V 23
Junction temperature TJMAX 125 °C -I grade 23
Voltage ramp rate on any supply pin VDDRAMPMAX 1 V / µs 23
Voltage on HFXO pins VHFXOPIN -0.3 1.2 V 23
DC voltage on any GPIO pin VDIGPIN -0.3 V 23
DC voltage on RESETn pin VRESETn -0.3 3.8 V 23
DC voltage on RF pin RF2G4_IO VMAX2G4 -0.3 1.2 V 23
Total current into VDD power lines IVDDMAX 200 mA Source 23
Total current into VSS ground lines IVSSMAX 200 mA Sink 23
Current per I/O pin IIOMAX 50 mA Sink 23
Current for all I/O pins IIOALLMAX 200 mA Sink 23
Operating ambient temperature range TA -40 125 °C -I temperature grade 24
DVDD supply voltage VDVDD 1.71 3 3.8 V EM0/1 24
AVDD supply voltage VAVDD 1.71 3 3.8 V AVDDBODEN=0 24
IOVDDx operating supply voltage (All IOVDD pins) VIOVDDx 1.71 3 3.8 V IOVDDxBODEN=0 24
RFVDD operating supply voltage VRFVDD 1.71 3 V 24
VREGVDD operating supply voltage VVREGVDD 2.2 3 3.8 V DC-DC in regulation 24
VREGVDD operating supply voltage VVREGVDD 1.8 3 3.8 V DC-DC in bypass 60 mA load 24
VREGVDD operating supply voltage VVREGVDD 1.71 3 3.8 V DC-DC not in use. DVDD externally shorted to VREGVDD 24
PAVDD operating supply voltage VPAVDD 1.71 3 3.8 V 24
DECOUPLE output capacitor CDECOUPLE 1 2.75 µF 1.0 µF ± 10% X8L capacitor used for performance characterization 24
HCLK and SYSCLK frequency fHCLK 78 MHz VSCALE2, MODE = WS1 24
HCLK and SYSCLK frequency fHCLK 40 MHz VSCALE2, MODE = WS0 24
HCLK and SYSCLK frequency fHCLK 20 MHz VSCALE1, MODE = WS0 24
EM01 Group A clock frequency fEM01GRPACLK 78 MHz VSCALE2 24
EM01 Group A clock frequency fEM01GRPACLK 40 MHz VSCALE1 24
Regulation DC accuracy ACCDC -2.5 4 % VVREGVDD ≥ 2.2 V, Steady state in EM0/EM1 mode or EM2/EM3 mode 26
Regulation total accuracy ACCTOT -5 7 % All error sources (including DC errors, overshoot, undershoot) 26
Output load current ILOAD 60 mA EM0/EM1 mode, DCDC in regulation, DCDC_EM01CTRL0.IPKVAL = 9, Radio not transmitting 26
Output load current ILOAD 36 mA EM0/EM1 mode, DCDC in regulation, Radio in receive mode 26
Output load current ILOAD 120 mA EM0/EM1 mode, DCDC in regulation, Radio transmitting 26
Output load current ILOAD 5 mA EM2/EM3 mode, DCDC in regulation 26
Nominal output capacitor CDCDC 4.7 10 µF 4.7 µF ± 10% X7R capacitor used for performance characterization 26
Nominal inductor tolerance LDCDC -20 20 % ± 20% tolerance 26
Resistance in bypass mode RBYP 0.45 0.69 Ω Bypass switch from VREGVDD to DVDD, VVREGVDD = 1.8 V 27
Powertrain PFET switch resistance from VREGVDD to VREGSW 0.6 0.9 Ω VVREGVDD = 1.8 V 27
Supply monitor threshold programming range VCMP_RNG 2 2.3 V Programmable in 0.1 V steps 27
Supply monitor threshold accuracy VCMP_ACC -5 5 % Supply falling edge trip point 27
Thermal resistance, junction to ambient (48QFN 6x6mm) ΘJA 27.7 °C/W Still Air; JEDEC High Thermal Cond. (2s2p) 28
Thermal resistance, junction to board (48QFN 6x6mm) ΘJB 14.6 °C/W JEDEC High Thermal Cond. (2s2p) 28
Thermal resistance, junction to case (48QFN 6x6mm) ΘJC 23 °C/W Temperature controlled heat sink on top of package, all other sides of package insulated to prevent heat flow 28
Flash supply voltage during write or erase VFLASH 1.71 3.8 V 44
Flash data retention RETFLASH 10 years TA ≤ 125 °C 44
Flash erase cycles before failure ECFLASH 10000 cycles TA ≤ 125 °C 44
Program time, one word (32-bits) tPROG 41.9 43.4 45 µs TA = 25 °C, one word (32-bits) 44
Page erase time tPERASE 11.6 12.9 14 ms TA = 25 °C 44
Mass erase time tMERASE 144.3 150.5 156.8 ms TA = 25 °C, 1536kB 44
Program current IWRITE 2.8 mA 44
Page erase current IPERASE 1.9 mA Page Erase 44
Mass erase current IMERASE 2 mA Mass Erase 44
Frequency (HFXO crystal) FHFXO 38 39 40 MHz see note 1 60
Pull up/down resistance (any GPIO pin) RPULL 35 44 55 kΩ Pull-up to IOVDD: MODEn = DISABLE, DOUT = 1; pull-down to VSS: MODEn = WIREDORPULLDOWN, DOUT = 0 65

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
housing PC 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. 120

CAD (KiCad official)

  • Symbol: EFR32BG24B110F1536IM48-BR
  • Footprint: Package_DFN_QFN:QFN-48-1EP_6x6mm_P0.4mm_EP4.4x4.4mm
  • 3D model: QFN-48(6x6), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.9 mm nominal QFN height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
  • 3D model files: efr32bg24b110f1536im48-br-etched.step / efr32bg24b110f1536im48-br-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); efr32bg24b110f1536im48-br.step / efr32bg24b110f1536im48-br.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: SKYWORKS SILICON LABS datasheet (129 pp, sha256 df98b018cb011d3f, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF