component
EFR32BG22C224F512IM40-CR
Public Made by Adomby adom
SILICON LABS RF Transceiver ICs, QFN-40-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownEFR32BG22C224F512IM40-CR
SILICON LABS · RF Transceiver ICs · QFN-40-EP(5x5)
EFR32BG22C224F512IM40-CR from SILICON LABS, in a QFN-40-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PC00 | bidirectional | General purpose I/O pin; Table 6.4 lists its alternate functions as GPIO.EM4WU6 and GPIO.THMSW_EN. |
| 2 | PC01 | bidirectional | General purpose I/O pin; alternate function options are given in the Alternate Function Table. |
| 3 | PC02 | bidirectional | General purpose I/O pin; alternate function options are given in the Alternate Function Table. |
| 4 | PC03 | bidirectional | General purpose I/O pin; alternate function options are given in the Alternate Function Table. |
| 5 | PC04 | bidirectional | General purpose I/O pin; alternate function options are given in the Alternate Function Table. |
| 6 | PC05 | bidirectional | General purpose I/O pin; Table 6.4 lists its alternate function as GPIO.EM4WU7. |
| 7 | PC06 | bidirectional | General purpose I/O pin; alternate function options are given in the Alternate Function Table. |
| 8 | PC07 | bidirectional | General purpose I/O pin; Table 6.4 lists its alternate function as GPIO.EM4WU8. |
| 9 | HFXTAL_I | input | High frequency crystal input for the HFXO, typically 38.4 MHz per the typical application circuit. |
| 10 | HFXTAL_O | output | High frequency crystal output for the HFXO. |
| 11 | RESETn | input | Reset pin, internally pulled up to DVDD. |
| 12 | RFVDD | power_in | Radio power supply. |
| 13 | RFVSS | power_in | Radio ground. |
| 14 | RF2G4_IO | bidirectional | 2.4 GHz single-ended RF input/output. |
| 15 | PAVDD | power_in | Power amplifier (PA) power supply. |
| 16 | PB04 | bidirectional | General purpose I/O pin; alternate function options are given in the Alternate Function Table. |
| 17 | PB03 | bidirectional | General purpose I/O pin; Table 6.4 lists its alternate function as GPIO.EM4WU4. |
| 18 | PB02 | bidirectional | General purpose I/O pin; alternate function options are given in the Alternate Function Table. |
| 19 | PB01 | bidirectional | General purpose I/O pin; Table 6.4 lists its alternate function as GPIO.EM4WU3. |
| 20 | PB00 | bidirectional | General purpose I/O pin; Table 6.4 lists its alternate function as IADC0.VREFN. |
| 21 | PA00 | bidirectional | General purpose I/O pin; Table 6.4 lists its alternate function as IADC0.VREFP. |
| 22 | PA01 | bidirectional | General purpose I/O pin; Table 6.4 lists its alternate function as GPIO.SWCLK. |
| 23 | PA02 | bidirectional | General purpose I/O pin; Table 6.4 lists its alternate function as GPIO.SWDIO. |
| 24 | PA03 | bidirectional | General purpose I/O pin; Table 6.4 lists its alternate functions as GPIO.SWV, GPIO.TDO and GPIO.TRACEDATA0. |
| 25 | PA04 | bidirectional | General purpose I/O pin; Table 6.4 lists its alternate functions as GPIO.TDI and GPIO.TRACECLK. |
| 26 | PA05 | bidirectional | General purpose I/O pin; Table 6.4 lists its alternate function as GPIO.EM4WU0. |
| 27 | PA06 | bidirectional | General purpose I/O pin; alternate function options are given in the Alternate Function Table. |
| 28 | PA07 | bidirectional | General purpose I/O pin; alternate function options are given in the Alternate Function Table. |
| 29 | PA08 | bidirectional | General purpose I/O pin; alternate function options are given in the Alternate Function Table. |
| 30 | DECOUPLE | passive | Decouple output for the on-chip voltage regulator; an external decoupling capacitor is required at this pin. |
| 31 | VREGSW | output | DCDC regulator switching node. |
| 32 | VREGVDD | power_in | DCDC regulator input supply. |
| 33 | VREGVSS | power_in | DCDC ground. |
| 34 | DVDD | power_in | Digital power supply; the RESETn pin is pulled up to DVDD. |
| 35 | AVDD | power_in | Analog power supply. |
| 36 | IOVDD | power_in | I/O power supply; GPIO input thresholds are proportional to IOVDD. |
| 37 | PD03 | bidirectional | General purpose I/O pin; alternate function options are given in the Alternate Function Table. |
| 38 | PD02 | bidirectional | General purpose I/O pin; Table 6.4 lists its alternate function as GPIO.EM4WU9. |
| 39 | PD01 | bidirectional | General purpose I/O pin; Table 6.4 lists its alternate functions as LFXO.LFXTAL_I and LFXO.LF_EXTCLK. |
| 40 | PD00 | bidirectional | General purpose I/O pin; Table 6.4 lists its alternate function as LFXO.LFXTAL_O. |
| 41 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | SILICON LABS |
| Package | QFN-40-EP(5x5) |
| Category | RF & Radio |
| Pins | 41 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Storage temperature range | TSTG | -50 | 150 | °C | 18 | ||
| Voltage on any supply pin | VDDMAX | -0.3 | 3.8 | V | 18 | ||
| Junction temperature | TJMAX | 125 | °C | -I grade | 18 | ||
| Voltage ramp rate on any supply pin | VDDRAMPMAX | 1 | V / µs | 18 | |||
| Voltage on HFXO pins | VHFXOPIN | -0.3 | 1.4 | V | 18 | ||
| DC voltage on RESETn pin | VRESETn | -0.3 | 3.8 | V | 18 | ||
| Input RF level on RF pins RF2G4_IO | PRFMAX2G4 | 10 | dBm | 18 | |||
| Total current into VDD power lines | IVDDMAX | 200 | mA | Source | 18 | ||
| Total current into VSS ground lines | IVSSMAX | 200 | mA | Sink | 18 | ||
| Current per I/O pin (sink) | IIOMAX | 50 | mA | Sink | 18 | ||
| Current per I/O pin (source) | IIOMAX | 50 | mA | Source | 18 | ||
| Current for all I/O pins (sink) | IIOALLMAX | 200 | mA | Sink | 18 | ||
| Current for all I/O pins (source) | IIOALLMAX | 200 | mA | Source | 18 | ||
| Operating ambient temperature range (I grade) | TA | -40 | 125 | °C | -I temperature grade | 19 | |
| DVDD supply voltage EM0/1 | VDVDD | 1.71 | 3 | 3.8 | V | EM0/1 | 19 |
| DVDD supply voltage EM2/3/4 | VDVDD | 1.71 | 3 | 3.8 | V | EM2/3/4 | 19 |
| AVDD supply voltage | VAVDD | 1.71 | 3 | 3.8 | V | 19 | |
| IOVDDx operating supply voltage (All IOVDD pins) | VIOVDDx | 1.71 | 3 | 3.8 | V | 19 | |
| PAVDD operating supply voltage | VPAVDD | 1.71 | 3 | 3.8 | V | 19 | |
| VREGVDD operating supply voltage | VVREGVDD | 2.2 | 3 | 3.8 | V | DC-DC in regulation | 19 |
| VREGVDD operating supply voltage | VVREGVDD | 1.8 | 3 | 3.8 | V | DC-DC in bypass 60 mA load | 19 |
| VREGVDD operating supply voltage | VVREGVDD | 1.71 | 3 | 3.8 | V | DC-DC not in use. DVDD externally shorted to VREGVDD | 19 |
| RFVDD operating supply voltage | VRFVDD | 1.71 | 3 | V | 19 | ||
| DECOUPLE output capacitor | CDECOUPLE | 1 | 2.75 | µF | X8L capacitor used for performance characterization | 19 | |
| HCLK and SYSCLK frequency | fHCLK | 76.8 | MHz | VSCALE2, MODE = WS1 | 19 | ||
| HCLK and SYSCLK frequency | fHCLK | 40 | MHz | VSCALE2, MODE = WS0 | 19 | ||
| PCLK frequency | fPCLK | 50 | MHz | VSCALE2 | 19 | ||
| PCLK frequency | fPCLK | 40 | MHz | VSCALE1 | 19 | ||
| Radio HCLK frequency | fRHCLK | 38.4 | MHz | VSCALE2 or VSCALE1 | 19 | ||
| Input voltage range at VREGVDD pin | VVREGVDD | 2.2 | 3 | 3.8 | V | DCDC in regulation, ILOAD = 60 mA, EM0/EM1 mode | 21 |
| Input voltage range at VREGVDD pin | VVREGVDD | 1.8 | 3 | 3.8 | V | DCDC in regulation, ILOAD = 5 mA, EM0/EM1 or EM2/EM3 mode | 21 |
| Regulation DC accuracy | ACCDC | -2.5 | 3.3 | % | VVREGVDD ≥ 2.2 V, Steady state in EM0/EM1 mode or EM2/EM3 mode | 21 | |
| Regulation total accuracy | ACCTOT | -5 | 7 | % | With mode transitions between EM0/EM1 and EM2/EM3 modes | 21 | |
| Output load current EM0/EM1 mode, DCDC in regulation | ILOAD | 60 | mA | EM0/EM1 mode, DCDC in regulation | 21 | ||
| Output load current EM2/EM3 mode, DCDC in regulation | ILOAD | 5 | mA | EM2/EM3 mode, DCDC in regulation | 21 | ||
| Output load current in bypass mode | ILOAD | 60 | mA | Bypass mode | 21 | ||
| Nominal output capacitor | CDCDC | 4.7 | 10 | µF | 4.7 µF ± 10% X7R capacitor used for performance characterization | 21 | |
| Nominal inductor | LDCDC | 2.2 | µH | 21 | |||
| Nominal inductor tolerance | LDCDC | -20 | 20 | % | ± 20% tolerance | 21 | |
| Resistance in bypass mode | RBYP | 1.75 | 3 | Ω | Bypass switch from VREGVDD to DVDD, VVREGVDD = 1.8 V | 21 | |
| Powertrain PFET switch resistance | 0.86 | 1.5 | Ω | PFET switch from VREGVDD to VREGSW, VVREGVDD = 1.8 V | 21 | ||
| Supply monitor threshold programming range | VCMP_RNG | 2 | 2.3 | V | Programmable in 0.1 V steps | 21 | |
| Supply monitor threshold accuracy | VCMP_ACC | -5 | 5 | % | Supply falling edge trip point | 21 | |
| Thermal resistance junction to ambient QFN40 (5x5mm) | THETAJA_QFN40_5X5 | 32.6 | °C/W | 4-Layer PCB, Natural Convection | 24 | ||
| Flash supply voltage during write or erase | VFLASH | 1.71 | 3.8 | V | 33 | ||
| Flash erase cycles before failure | ECFLASH | 10000 | cycles | TA ≤ 125 °C | 33 | ||
| Flash data retention | RETFLASH | 10 | years | TA ≤ 125 °C | 33 | ||
| Frequency accuracy HFRCO | FHFRCO_ACC | -3 | 3 | % | For all production calibrated frequencies | 51 | |
| FSRCO frequency | FFSRCO | 17.2 | 20 | 21.2 | MHz | 52 | |
| Crystal frequency HFXO | FHFXO | 38.4 | MHz | see note1 | 49 | ||
| Supported crystal equivalent series resistance (ESR) HFXO | ESRHFXO_38M4 | 40 | 60 | Ω | 38.4 MHz, CL = 10 pF | 49 | |
| Frequency accuracy LFRCO | FLFRCO_ACC | -3 | 3 | % | Normal mode | 53 | |
| Precision mode frequency tolerance LFRCO | FLFRCO_ACC | -500 | 500 | ppm | Precision mode, across operating temperature range | 53 | |
| Ultra Low Frequency RC oscillation frequency | FULFRCO | 0.944 | 1 | 1.095 | kHz | 53 | |
| RF tuning frequency range | FRANGE | 2400 | 2483.5 | MHz | 36 | ||
| Maximum TX power | POUTMAX | 6 | dBm | 6 dBm PA | 36 | ||
| Radio-only current consumption while transmitting | ITX_RADIO | 7.5 | mA | f = 2.4 GHz, CW, 6 dBm PA, 6 dBm output power | 36 | ||
| Radio-only current consumption in receive mode | IRX_RADIO | 2.5 | mA | 43 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | PC | 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. | 86 |
CAD (KiCad official)
- Symbol:
EFR32BG22C224F512IM40-CR - Footprint:
Package_DFN_QFN:QFN-40-1EP_5x5mm_P0.4mm_EP3.6x3.6mm - 3D model: QFN-40-EP(5x5) (KiCad packages3D, STEP)
- 3D model files:
efr32bg22c224f512im40-cr-etched.step/efr32bg22c224f512im40-cr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);efr32bg22c224f512im40-cr.step/efr32bg22c224f512im40-cr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: SILICON LABS datasheet (101 pp, sha256
9dc49fc97500e829, retrieved 2026-10-26, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).