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EFR32BG22C224F512IM40-C

Public Made by Adom

by adom

SILICON LABS RF Transceiver ICs, QFN-40-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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EFR32BG22C224F512IM40-C

SILICON LABS · RF Transceiver ICs · QFN-40-EP(5x5)

EFR32BG22C224F512IM40-C from SILICON LABS, in a QFN-40-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PC00 bidirectional GPIO pin with alternate functions GPIO.EM4WU6 and GPIO.THMSW_EN.
2 PC01 bidirectional General purpose I/O pin.
3 PC02 bidirectional General purpose I/O pin.
4 PC03 bidirectional General purpose I/O pin.
5 PC04 bidirectional General purpose I/O pin.
6 PC05 bidirectional GPIO pin with alternate function GPIO.EM4WU7.
7 PC06 bidirectional General purpose I/O pin.
8 PC07 bidirectional GPIO pin with alternate function GPIO.EM4WU8.
9 HFXTAL_I input High frequency crystal input.
10 HFXTAL_O output High frequency crystal output.
11 RESETn input Reset pin, internally pulled up to DVDD.
12 RFVDD power_in Radio power supply.
13 RFVSS power_in Radio ground.
14 RF2G4_IO bidirectional 2.4 GHz single-ended RF input/output.
15 PAVDD power_in Power amplifier (PA) power supply.
16 PB04 bidirectional General purpose I/O pin.
17 PB03 bidirectional GPIO pin with alternate function GPIO.EM4WU4.
18 PB02 bidirectional General purpose I/O pin.
19 PB01 bidirectional GPIO pin with alternate function GPIO.EM4WU3.
20 PB00 bidirectional GPIO pin with alternate function IADC0.VREFN.
21 PA00 bidirectional GPIO pin with alternate function IADC0.VREFP.
22 PA01 bidirectional GPIO pin with alternate function GPIO.SWCLK (serial wire debug clock).
23 PA02 bidirectional GPIO pin with alternate function GPIO.SWDIO (serial wire debug data).
24 PA03 bidirectional GPIO pin with alternate functions GPIO.SWV, GPIO.TDO and GPIO.TRACEDATA0.
25 PA04 bidirectional GPIO pin with alternate functions GPIO.TDI and GPIO.TRACECLK.
26 PA05 bidirectional GPIO pin with alternate function GPIO.EM4WU0.
27 PA06 bidirectional General purpose I/O pin.
28 PA07 bidirectional General purpose I/O pin.
29 PA08 bidirectional General purpose I/O pin.
30 DECOUPLE passive Decouple output for on-chip voltage regulator; an external decoupling capacitor is required at this pin.
31 VREGSW passive DCDC regulator switching node.
32 VREGVDD power_in DCDC regulator input supply.
33 VREGVSS power_in DCDC ground.
34 DVDD power_in Digital power supply.
35 AVDD power_in Analog power supply.
36 IOVDD power_in I/O power supply.
37 PD03 bidirectional General purpose I/O pin.
38 PD02 bidirectional GPIO pin with alternate function GPIO.EM4WU9.
39 PD01 bidirectional GPIO pin with alternate functions LFXO.LFXTAL_I and LFXO.LF_EXTCLK.
40 PD00 bidirectional GPIO pin with alternate function LFXO.LFXTAL_O.
41 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer SILICON LABS
Package QFN-40-EP(5x5)
Category RF & Radio
Pins 41

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Storage temperature range TSTG -50 150 °C 18
Voltage on any supply pin VDDMAX -0.3 3.8 V 18
Junction temperature TJMAX 125 °C -I grade 18
Voltage ramp rate on any supply pin VDDRAMPMAX 1 V / µs 18
Voltage on HFXO pins VHFXOPIN -0.3 1.4 V 18
DC voltage on RESETn pin VRESETn -0.3 3.8 V 18
Input RF level on RF2G4_IO PRFMAX2G4 10 dBm 18
Total current into VDD power lines IVDDMAX 200 mA Source 18
Total current into VSS ground lines IVSSMAX 200 mA Sink 18
Current per I/O pin IIOMAX 50 mA Sink 18
Current for all I/O pins IIOALLMAX 200 mA Sink 18
Operating ambient temperature range TA -40 125 °C -I temperature grade 19
DVDD supply voltage VDVDD 1.71 3 3.8 V EM0/1 19
AVDD supply voltage VAVDD 1.71 3 3.8 V 19
IOVDDx operating supply voltage VIOVDDx 1.71 3 3.8 V 19
PAVDD operating supply voltage VPAVDD 1.71 3 3.8 V 19
VREGVDD operating supply voltage VVREGVDD 2.2 3 3.8 V DC-DC in regulation 19
VREGVDD operating supply voltage VVREGVDD 1.71 3 3.8 V DC-DC not in use. DVDD externally shorted to VREGVDD 19
DECOUPLE output capacitor CDECOUPLE 1 2.75 µF 1.0 µF ± 10% X8L capacitor used for performance characterization. 19
HCLK and SYSCLK frequency fHCLK 76.8 MHz VSCALE2, MODE = WS1 19
Thermal resistance junction to ambient QFN40 (5x5mm) THETAJA_QFN40_5X5 32.6 °C/W 4-Layer PCB, Natural Convection 24
DC-DC regulation DC accuracy ACCDC -2.5 3.3 % VVREGVDD ≥ 2.2 V, Steady state in EM0/EM1 mode or EM2/EM3 mode 21
DC-DC regulation total accuracy ACCTOT -5 7 % With mode transitions between EM0/EM1 and EM2/EM3 modes 21
DC-DC output load current ILOAD 60 mA EM0/EM1 mode, DCDC in regulation 21
Bypass switch resistance RBYP 1.75 3 Ω Bypass switch from VREGVDD to DVDD, VVREGVDD = 1.8 V 21
Flash erase cycles before failure ECFLASH 10000 cycles TA ≤ 125 °C 33
Flash data retention RETFLASH 10 years TA ≤ 125 °C 33
Program time tPROG 42.1 44 45.6 uSec one word (32-bits) 33
Page erase time tPERASE 11.4 12.9 14.4 ms 33
Mass erase time tMERASE 11.7 13 14.3 ms Erases all of User Code area 33
HFXO crystal ESR ESRHFXO_38M4 40 60 Ω 38.4 MHz, CL = 10 pF 49
HFRCO frequency accuracy FHFRCO_ACC -3 3 % For all production calibrated frequencies 51
FSRCO frequency FFSRCO 17.2 20 21.2 MHz 52
LFRCO frequency accuracy FLFRCO_ACC -3 3 % Normal mode 53
LFRCO frequency accuracy FLFRCO_ACC -500 500 ppm Precision mode, across operating temperature range 53
ULFRCO oscillation frequency FULFRCO 0.944 1 1.095 kHz 53
GPIO leakage current ILEAK_IO 200 nA Pins other than PA00, PA03, PB00, PC03, PC04 and PD00; MODEx = DISABLED, IOVDD = 3.8 V TA = 125 °C 54
GPIO input low voltage VIL 0.3 V Any GPIO pin (0.3*IOVDD) 54
GPIO input high voltage VIH 0.7 V Any GPIO pin (0.7*IOVDD) 54
GPIO output high voltage VOH 0.8 V Sourcing 20mA, IOVDD = 3.0 V (0.8*IOVDD) 54
GPIO output low voltage VOL 0.2 V Sinking 20mA, IOVDD = 3.0 V (0.2*IOVDD) 54

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
housing PC 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. 86

CAD (KiCad official)

  • Symbol: EFR32BG22C224F512IM40-C
  • Footprint: Package_DFN_QFN:QFN-40-1EP_5x5mm_P0.4mm_EP3.6x3.6mm
  • 3D model: QFN-40-EP(5x5) (KiCad packages3D, STEP)
  • 3D model files: efr32bg22c224f512im40-c-etched.step / efr32bg22c224f512im40-c-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); efr32bg22c224f512im40-c.step / efr32bg22c224f512im40-c.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: SILICON LABS datasheet (101 pp, sha256 9dc49fc97500e829, retrieved 2026-10-23, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF