Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity

3D Model

Open in new tab ↗

Loads when you scroll to it. Unloads after 5 minutes in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗

Loads when you scroll to it. Unloads after 5 minutes in the background.

PCB Footprint

Open full view ↗

Loads when you scroll to it. Unloads after 5 minutes in the background.

Datasheet

Open in new tab ↗

Loads when you scroll to it. Unloads after 5 minutes in the background.

Download PDF

Contents

Pinout
Key specifications
Electrical characteristics
Materials and finish
CAD (KiCad official)
Provenance

README

markdown

EFR32BG22C224F512GM40-CR

SKYWORKS SILICON LABS · RF Transceiver ICs · QFN-40-EP(5x5)

EFR32BG22C224F512GM40-CR from SKYWORKS SILICON LABS, in a QFN-40-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	PC00	bidirectional	GPIO pin on Port C; alternate functions (GPIO.EM4WU6, GPIO.THMSW_EN) are listed in Table 6.4.
2	PC01	bidirectional	GPIO pin on Port C; alternate functions are routed per the Digital Peripheral Connectivity table (6.6).
3	PC02	bidirectional	GPIO pin on Port C; alternate functions are routed per the Digital Peripheral Connectivity table (6.6).
4	PC03	bidirectional	GPIO pin on Port C; listed in the datasheet among the pins with the 550 nA maximum leakage at 3.8 V and 125 °C (Table 4.30).
5	PC04	bidirectional	GPIO pin on Port C; listed in the datasheet among the pins with the 550 nA maximum leakage at 3.8 V and 125 °C (Table 4.30).
6	PC05	bidirectional	GPIO pin on Port C; alternate function GPIO.EM4WU7 is listed in Table 6.4.
7	PC06	bidirectional	GPIO pin on Port C; alternate functions are routed per the Digital Peripheral Connectivity table (6.6).
8	PC07	bidirectional	GPIO pin on Port C; alternate function GPIO.EM4WU8 is listed in Table 6.4.
9	HFXTAL_I	input	High-frequency crystal oscillator input (38.4 MHz crystal in the typical application circuit, Figure 5.1/5.2).
10	HFXTAL_O	output	High-frequency crystal oscillator output.
11	RESETn	input	Active-low reset pin, internally pulled up to DVDD (typical pull-up 44 kΩ, range 35-55 kΩ per Table 4.30/4.30 RESETn row); input low threshold 0.3DVDD and high threshold 0.7DVDD.
12	RFVDD	power_in	Radio power supply input.
13	RFVSS	power_in	Radio ground.
14	RF2G4_IO	bidirectional	Single-ended 2.4 GHz RF input/output pin that connects to the antenna through the matching network in Section 5.2.
15	PAVDD	power_in	Power amplifier (PA) power supply input.
16	PB04	bidirectional	GPIO pin on Port B; alternate functions are routed per the Digital Peripheral Connectivity table (6.6).
17	PB03	bidirectional	GPIO pin on Port B; alternate function GPIO.EM4WU4 is listed in Table 6.4.
18	PB02	bidirectional	GPIO pin on Port B; alternate functions are routed per the Digital Peripheral Connectivity table (6.6).
19	PB01	bidirectional	GPIO pin on Port B; alternate function GPIO.EM4WU3 is listed in Table 6.4.
20	PB00	bidirectional	GPIO pin on Port B; alternate function IADC0.VREFN is listed in Table 6.4, and it is among the pins with the 550 nA maximum leakage at 3.8 V and 125 °C.
21	PA00	bidirectional	GPIO pin on Port A; alternate function IADC0.VREFP is listed in Table 6.4, and it is among the pins with the 550 nA maximum leakage at 3.8 V and 125 °C.
22	PA01	bidirectional	GPIO pin on Port A; alternate function GPIO.SWCLK is listed in Table 6.4.
23	PA02	bidirectional	GPIO pin on Port A; alternate function GPIO.SWDIO is listed in Table 6.4.
24	PA03	bidirectional	GPIO pin on Port A; alternate functions GPIO.SWV, GPIO.TDO and GPIO.TRACEDATA0 are listed in Table 6.4, and it is among the pins with the 550 nA maximum leakage at 3.8 V and 125 °C.
25	PA04	bidirectional	GPIO pin on Port A; alternate functions GPIO.TDI and GPIO.TRACECLK are listed in Table 6.4.
26	PA05	bidirectional	GPIO pin on Port A; alternate function GPIO.EM4WU0 is listed in Table 6.4.
27	PA06	bidirectional	GPIO pin on Port A; alternate functions are routed per the Digital Peripheral Connectivity table (6.6).
28	PA07	bidirectional	GPIO pin on Port A; alternate functions are routed per the Digital Peripheral Connectivity table (6.6).
29	PA08	bidirectional	GPIO pin on Port A; alternate functions are routed per the Digital Peripheral Connectivity table (6.6).
30	DECOUPLE	passive	Decouple output for the on-chip voltage regulator; an external decoupling capacitor is required at this pin.
31	VREGSW	output	DC-DC regulator switching node; connects to the DC-DC inductor in the DCDC configuration (Figure 5.2).
32	VREGVDD	power_in	DC-DC regulator input supply.
33	VREGVSS	power_in	DC-DC converter ground.
34	DVDD	power_in	Digital power supply; the RESETn pin is pulled up to this supply and the DVDD BOD thresholds apply (Section 4.15).
35	AVDD	power_in	Analog power supply.
36	IOVDD	power_in	I/O power supply; GPIO input thresholds and output levels are proportional to this supply.
37	PD03	bidirectional	GPIO pin on Port D; alternate functions are routed per the Digital Peripheral Connectivity table (6.6).
38	PD02	bidirectional	GPIO pin on Port D; alternate function GPIO.EM4WU9 is listed in Table 6.4.
39	PD01	bidirectional	GPIO pin on Port D; alternate functions LFXO.LFXTAL_I and LFXO.LF_EXTCLK are listed in Table 6.4.
40	PD00	bidirectional	GPIO pin on Port D; alternate function LFXO.LFXTAL_O is listed in Table 6.4, and it is among the pins with the 550 nA maximum leakage at 3.8 V and 125 °C.
41	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	SKYWORKS SILICON LABS
Package	QFN-40-EP(5x5)
Category	RF And Wireless
Pins	41

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Storage temperature range	TSTG	-50		150	°C		18
Voltage on any supply pin	VDDMAX	-0.3		3.8	V		18
Junction temperature (-G grade)	TJMAX			105	°C	-G grade	18
Voltage ramp rate on any supply pin	VDDRAMPMAX			1	V/µs		18
Voltage on HFXO pins	VHFXOPIN	-0.3		1.4	V		18
DC voltage on any GPIO pin	VDIGPIN	-0.3			V	max printed as VIOVDD + 0.3	18
DC voltage on RESETn pin	VRESETn	-0.3		3.8	V		18
Input RF level on RF pin RF2G4_IO	PRFMAX2G4			10	dBm		18
Absolute voltage on RF pin RF2G4_IO	VMAX2G4	-0.3			V	max printed as VPAVDD + 0.3	18
Total current into VDD power lines	IVDDMAX			200	mA	Source	18
Total current into VSS ground lines	IVSSMAX			200	mA	Sink	18
Current per I/O pin	IIOMAX			50	mA	Sink	18
Current for all I/O pins	IIOALLMAX			200	mA	Sink	18
Operating ambient temperature range	TA	-40		85	°C	-G temperature grade	19
DVDD supply voltage	VDVDD	1.71	3	3.8	V	EM0/1	19
AVDD supply voltage	VAVDD	1.71	3	3.8	V		19
IOVDDx operating supply voltage (All IOVDD pins)	VIOVDDx	1.71	3	3.8	V		19
PAVDD operating supply voltage	VPAVDD	1.71	3	3.8	V		19
VREGVDD operating supply voltage	VVREGVDD	2.2	3	3.8	V	DC-DC in regulation	19
VREGVDD operating supply voltage	VVREGVDD	1.8	3	3.8	V	DC-DC in bypass, 60 mA load	19
VREGVDD operating supply voltage	VVREGVDD	1.71	3	3.8	V	DC-DC not in use, DVDD externally shorted to VREGVDD	19
RFVDD operating supply voltage	VRFVDD	1.71	3		V	max printed as VPAVDD	19
DECOUPLE output capacitor	CDECOUPLE	1		2.75	µF	X8L 1.0 µF ±10% capacitor used for performance characterization	19
HCLK and SYSCLK frequency	fHCLK			76.8	MHz	VSCALE2, MODE = WS1	19
Input voltage range at VREGVDD pin	VVREGVDD	2.2	3	3.8	V	DCDC in regulation, ILOAD = 60 mA, EM0/EM1 mode	21
Input voltage range at VREGVDD pin	VVREGVDD	1.8	3	3.8	V	DCDC in regulation, ILOAD = 5 mA, EM0/EM1 or EM2/EM3 mode	21
Regulation DC accuracy	ACCDC	-2.5		3.3	%	VVREGVDD ≥ 2.2 V, steady state in EM0/EM1 or EM2/EM3 mode	21
Regulation total accuracy	ACCTOT	-5		7	%	With mode transitions between EM0/EM1 and EM2/EM3 modes	21
Output load current	ILOAD			60	mA	EM0/EM1 mode, DCDC in regulation	21
Output load current	ILOAD			5	mA	EM2/EM3 mode, DCDC in regulation	21
Nominal output capacitor	CDCDC	4.7		10	µF	4.7 µF ± 10% X7R capacitor used for performance characterization	21
Resistance in bypass mode	RBYP		1.75	3	Ω	Bypass switch from VREGVDD to DVDD, VVREGVDD = 1.8 V	21
Powertrain PFET switch resistance			0.86	1.5	Ω	PFET switch from VREGVDD to VREGSW, VVREGVDD = 1.8 V	21
Supply monitor threshold programming range	VCMP_RNG	2		2.3	V	Programmable in 0.1 V steps	21
Flash supply voltage during write or erase	VFLASH	1.71		3.8	V		33
Flash erase cycles before failure	ECFLASH	10000			cycles	TA ≤ 125 °C	33
Flash data retention	RETFLASH	10			years	TA ≤ 125 °C	33
Program time	tPROG	42.1	44	45.6	uSec	one word (32-bits)	33
Page erase time	tPERASE	11.4	12.9	14.4	ms		33
Mass erase time	tMERASE	11.7	13	14.3	ms	Erases all of User Code area	33
RF tuning frequency range	FRANGE	2400		2483.5	MHz		36
RF level above which RFSENSE will detect signal	THRESTRIG	-28			dBm	Threshold set to -34 dBm	35
RF level above which RFSENSE will detect signal	THRESTRIG	-19			dBm	Threshold set to -22 dBm	35
RF level below which RFSENSE will not detect signal	THRESNOTRIG			-40	dBm	Threshold set to -34 dBm	35
RF level below which RFSENSE will not detect signal	THRESNOTRIG			-26	dBm	Threshold set to -22 dBm	35
Sensitivity in selective OOK mode	SENSOOK	-28			dBm	> 90% probability of OOK detection, threshold set to -34 dBm	35
Sensitivity in selective OOK mode	SENSOOK	-19			dBm	> 90% probability of OOK detection, threshold set to -22 dBm	35
Supported crystal equivalent series resistance (ESR)	ESRHFXO_38M4		40	60	Ω	38.4 MHz, CL = 10 pF	49
Supported range of crystal load capacitance	CLFXO_CL	4		6	pF	GAIN = 0	50
Supported range of crystal load capacitance	CLFXO_CL	6		10	pF	GAIN = 1	50
Supported range of crystal load capacitance	CLFXO_CL	10		12.5	pF	GAIN = 2	50
Supported range of crystal load capacitance	CLFXO_CL	12.5		18	pF	GAIN = 3	50
Frequency accuracy	FHFRCO_ACC	-3		3	%	For all production calibrated frequencies	51
FSRCO frequency	FFSRCO	17.2	20	21.2	MHz		52
Ultra low frequency RC oscillator frequency	FULFRCO	0.944	1	1.095	kHz		53
Thermal resistance junction to ambient, QFN40 (5x5 mm) package	THETAJA_QFN40_5X5		32.6		°C/W	4-layer PCB, natural convection (JESD51-2A)	24

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part	Material	Colour / plating	Datasheet says	Page
housing	PC		4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.	86

CAD (KiCad official)

Symbol: EFR32BG22C224F512GM40-CR
Footprint: Package_DFN_QFN:QFN-40-1EP_5x5mm_P0.4mm_EP3.6x3.6mm
3D model: QFN-40-EP(5x5) (KiCad packages3D, STEP)
3D model files: efr32bg22c224f512gm40-cr-etched.step / efr32bg22c224f512gm40-cr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); efr32bg22c224f512gm40-cr.step / efr32bg22c224f512gm40-cr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: SKYWORKS SILICON LABS datasheet (101 pp, sha256 9dc49fc97500e829, retrieved 2026-10-18, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF