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EFR32BG22C222F352GM40-C

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SILICON LABS RF Transceiver ICs, QFN-40-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentrf & radioefr32bg22c222f352gm40-cfactory-2.0.0extractor-text

Verified EFR32BG22C222F352GM40-C

by Ray · last 30 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

30 Oct 2026RayPublished by the parts factory: tier lcsc, 41 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: EFR32BG22C222F352GM40-C · QFN-40-EP(5x5) · 41 pins
  • ✓copper: 41 copper pads, none touching another net
  • ✓datasheet: all 41 pin names found in the 103-page datasheet
  • ✓distributor: lcsc C1015258, digikey 336-EFR32BG22C222F352GM40-C-ND, mouser 634-ER32BG22352GM40C
  • ✓family: QFN-40-1EP_5x5mm_P0.4mm_EP3.6x3.6mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-slhhloaa/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height within the datasheet's package drawing (datasheet p.97)
  • ✓pads: 41 pins = 41 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 41 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ efr32bg22c222f352gm40-c.kicad_sym✓ efr32bg22c222f352gm40-c.kicad_mod✓ efr32bg22c222f352gm40-c.step
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Ray Publish 0.1.0 ae90670

EFR32BG22C222F352GM40-C

SILICON LABS · RF Transceiver ICs · QFN-40-EP(5x5)

EFR32BG22C222F352GM40-C from SILICON LABS, in a QFN-40-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PC00 bidirectional General-purpose I/O pin PC00 (also EM4 wakeup input GPIO.EM4WU6 and GPIO.THMSW_EN per Table 6.4); GPIO input thresholds are set by IOVDD per Table 4.30.
2 PC01 bidirectional General-purpose I/O pin; the datasheet gives no further per-pin limits, so IOVDD-referenced GPIO thresholds from Table 4.30 apply.
3 PC02 bidirectional General-purpose I/O pin; the datasheet gives no further per-pin limits, so IOVDD-referenced GPIO thresholds from Table 4.30 apply.
4 PC03 bidirectional General-purpose I/O pin; the datasheet gives no further per-pin limits, so IOVDD-referenced GPIO thresholds from Table 4.30 apply.
5 PC04 bidirectional General-purpose I/O pin; the datasheet gives no further per-pin limits, so IOVDD-referenced GPIO thresholds from Table 4.30 apply.
6 PC05 bidirectional General-purpose I/O pin; also EM4 wakeup input GPIO.EM4WU7 per Table 6.4.
7 PC06 bidirectional General-purpose I/O pin; the datasheet gives no further per-pin limits, so IOVDD-referenced GPIO thresholds from Table 4.30 apply.
8 PC07 bidirectional General-purpose I/O pin; also EM4 wakeup input GPIO.EM4WU8 per Table 6.4.
9 HFXTAL_I input High-frequency crystal oscillator input, used with the 38.4 MHz crystal in the typical application circuits.
10 HFXTAL_O output High-frequency crystal oscillator output, used with the 38.4 MHz crystal in the typical application circuits.
11 RESETn input Active-low reset pin, internally pulled up to DVDD (35/44/55 kΩ per Table 4.30), with a minimum low time of 100 ns to ensure pin reset.
12 RFVDD power_in Radio power supply input for the 2.4 GHz radio subsystem.
13 RFVSS power_in Radio ground return for the 2.4 GHz radio subsystem.
14 RF2G4_IO bidirectional Single-ended 2.4 GHz RF input/output, connected to the external matching network with a 50 Ω antenna interface.
15 PAVDD power_in Power amplifier (PA) power supply input for the integrated PA, which provides up to 6 dBm output power.
16 PB04 bidirectional General-purpose I/O pin; the datasheet gives no further per-pin limits, so IOVDD-referenced GPIO thresholds from Table 4.30 apply.
17 PB03 bidirectional General-purpose I/O pin; also EM4 wakeup input GPIO.EM4WU4 per Table 6.4.
18 PB02 bidirectional General-purpose I/O pin; the datasheet gives no further per-pin limits, so IOVDD-referenced GPIO thresholds from Table 4.30 apply.
19 PB01 bidirectional General-purpose I/O pin; also EM4 wakeup input GPIO.EM4WU3 per Table 6.4.
20 PB00 bidirectional General-purpose I/O pin; the datasheet gives no further per-pin limits, so IOVDD-referenced GPIO thresholds from Table 4.30 apply.
21 PA00 bidirectional General-purpose I/O pin; also IADC0.VREFP per Table 6.4.
22 PA01 bidirectional General-purpose I/O pin; also GPIO.SWCLK debug clock per Table 6.4.
23 PA02 bidirectional General-purpose I/O pin; also GPIO.SWDIO debug data per Table 6.4.
24 PA03 bidirectional General-purpose I/O pin; also GPIO.SWV, GPIO.TDO and GPIO.TRACEDATA0 per Table 6.4.
25 PA04 bidirectional General-purpose I/O pin; also GPIO.TDI and GPIO.TRACECLK per Table 6.4.
26 PA05 bidirectional General-purpose I/O pin; also EM4 wakeup input GPIO.EM4WU0 per Table 6.4.
27 PA06 bidirectional General-purpose I/O pin; the datasheet gives no further per-pin limits, so IOVDD-referenced GPIO thresholds from Table 4.30 apply.
28 PA07 bidirectional General-purpose I/O pin; the datasheet gives no further per-pin limits, so IOVDD-referenced GPIO thresholds from Table 4.30 apply.
29 PA08 bidirectional General-purpose I/O pin; the datasheet gives no further per-pin limits, so IOVDD-referenced GPIO thresholds from Table 4.30 apply.
30 DECOUPLE power_out Decouple output for the on-chip voltage regulator; an external decoupling capacitor is required at this pin.
31 VREGSW output DC-DC regulator switching node, connected to the external DC-DC inductor (LDCDC) in the DCDC configurations.
32 VREGVDD power_in DC-DC regulator input supply.
33 VREGVSS power_in DC-DC converter ground.
34 DVDD power_in Digital power supply; it is the reference for the RESETn input thresholds (0.3×DVDD low, 0.7×DVDD high).
35 AVDD power_in Analog power supply; the datasheet gives the main analog supply range of 1.71 V to 3.8 V for the IADC in Table 4.31.
36 IOVDD power_in I/O power supply; GPIO input thresholds and output levels are referenced to this supply per Table 4.30.
37 PD03 bidirectional General-purpose I/O pin; the datasheet gives no further per-pin limits, so IOVDD-referenced GPIO thresholds from Table 4.30 apply.
38 PD02 bidirectional General-purpose I/O pin; also EM4 wakeup input GPIO.EM4WU9 per Table 6.4.
39 PD01 bidirectional General-purpose I/O pin; also LFXO.LFXTAL_I and LFXO.LF_EXTCLK per Table 6.4.
40 PD00 bidirectional General-purpose I/O pin; also LFXO.LFXTAL_O per Table 6.4.
41 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer SILICON LABS
Package QFN-40-EP(5x5)
Category RF & Radio
Pins 41

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Storage temperature range TSTG -50 150 °C 18
Voltage on any supply pin VDDMAX -0.3 3.8 V 18
Junction temperature TJMAX 105 °C -G grade 18
Voltage ramp rate on any supply pin VDDRAMPMAX 1 V/µs 18
Voltage on HFXO pins VHFXOPIN -0.3 1.4 V 18
DC voltage on any GPIO pin VDIGPIN -0.3 V Max printed as VIOVDD + 0.3 (not numeric) 18
DC voltage on RESETn pin VRESETn -0.3 3.8 V 18
Input RF level on RF pins RF2G4_IO PRFMAX2G4 10 dBm 18
Absolute voltage on RF pin RF2G4_IO VMAX2G4 -0.3 V Max printed as VPAVDD + 0.3 (not numeric) 18
Total current into VDD power lines IVDDMAX 200 mA Source 18
Total current into VSS ground lines IVSSMAX 200 mA Sink 18
Current per I/O pin IIOMAX 50 mA Sink 18
Current for all I/O pins IIOALLMAX 200 mA Sink 18
Operating ambient temperature range TA -40 85 °C -G temperature grade 19
DVDD supply voltage VDVDD 1.71 3 3.8 V EM0/1 19
AVDD supply voltage VAVDD 1.71 3 3.8 V 19
IOVDDx operating supply voltage (All IOVDD pins) VIOVDDx 1.71 3 3.8 V 19
PAVDD operating supply voltage VPAVDD 1.71 3 3.8 V 19
VREGVDD operating supply voltage VVREGVDD 2.2 3 3.8 V DC-DC in regulation 19
VREGVDD operating supply voltage VVREGVDD 1.8 3 3.8 V DC-DC in bypass 60 mA load 19
VREGVDD operating supply voltage VVREGVDD 1.71 3 3.8 V DC-DC not in use. DVDD externally shorted to VREGVDD 19
RFVDD operating supply voltage VRFVDD 1.71 3 V Max printed as VPAVDD (not numeric) 19
DECOUPLE output capacitor CDECOUPLE 1 2.75 µF 1.0 µF ± 10% X8L capacitor used for performance characterization. 19
HCLK and SYSCLK frequency fHCLK 76.8 MHz VSCALE2, MODE = WS1 19
HCLK and SYSCLK frequency fHCLK 40 MHz VSCALE2, MODE = WS0 19
PCLK frequency fPCLK 50 MHz VSCALE2 19
PCLK frequency fPCLK 40 MHz VSCALE1 19
EM01 Group A clock frequency fEM01GRPACLK 76.8 MHz VSCALE2 19
EM01 Group A clock frequency fEM01GRPACLK 40 MHz VSCALE1 19
EM01 Group B clock frequency fEM01GRPBCLK 76.8 MHz VSCALE2 19
EM01 Group B clock frequency fEM01GRPBCLK 40 MHz VSCALE1 19
Input voltage range at VREGVDD pin VVREGVDD 2.2 3 3.8 V DCDC in regulation, ILOAD = 60 mA, EM0/EM1 mode 21
Input voltage range at VREGVDD pin VVREGVDD 1.8 3 3.8 V DCDC in regulation, ILOAD = 5 mA, EM0/EM1 or EM2/EM3 mode 21
Regulation DC accuracy ACCDC -2.5 3.3 % VVREGVDD ≥ 2.2 V, Steady state in EM0/EM1 mode or EM2/EM3 mode 21
Regulation total accuracy ACCTOT -5 7 % With mode transitions between EM0/EM1 and EM2/EM3 modes 21
Output load current ILOAD 60 mA EM0/EM1 mode, DCDC in regulation 21
Output load current ILOAD 5 mA EM2/EM3 mode, DCDC in regulation 21
Nominal output capacitor CDCDC 4.7 10 µF 4.7 µF ± 10% X7R capacitor used for performance characterization 21
Resistance in bypass mode RBYP 1.75 3 Ω Bypass switch from VREGVDD to DVDD, VVREGVDD = 1.8 V 21
Powertrain PFET switch resistance 0.86 1.5 Ω PFET switch from VREGVDD to VREGSW, VVREGVDD = 1.8 V 21
Supply monitor threshold programming range VCMP_RNG 2 2.3 V Programmable in 0.1 V steps 21
Supply monitor threshold accuracy VCMP_ACC -5 5 % Supply falling edge trip point 21
Flash supply voltage during write or erase VFLASH 1.71 3.8 V 33
Flash erase cycles before failure ECFLASH 10000 cycles TA ≤ 125 °C 33
Flash data retention RETFLASH 10 years TA ≤ 125 °C 33
Program time tPROG 42.1 44 45.6 uSec one word (32-bits) 33
Page erase time tPERASE 11.4 12.9 14.4 ms 33
Mass erase time tMERASE 11.7 13 14.3 ms Erases all of User Code area 33
Program current IPROG 1.45 mA 33
HFRCO frequency accuracy FHFRCO_ACC -3 3 % For all production calibrated frequencies 51
Leakage current ILEAK_IO 150 nA MODEx = DISABLED, IOVDD = 3.8 V TA = 85 °C 54
Leakage current ILEAK_IO 200 nA Pins other than PA00, PA03, PB00, PC03, PC04 and PD00; MODEx = DISABLED, IOVDD = 3.8 V TA = 125 °C 54
Leakage current ILEAK_IO 550 nA Pins PA00, PA03, PB00, PC03, PC04 and PD00; MODEx = DISABLED, IOVDD = 3.8 V TA = 125 °C 54
Thermal resistance, junction to ambient, QFN40 (5x5mm) package THETAJA_QFN40_5X5 32.6 °C/W 4-Layer PCB, Natural Convection 24

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
housing PC 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. 87

CAD (KiCad official)

  • Symbol: EFR32BG22C222F352GM40-C
  • Footprint: Package_DFN_QFN:QFN-40-1EP_5x5mm_P0.4mm_EP3.6x3.6mm
  • 3D model: QFN-40-EP(5x5) (KiCad packages3D, STEP)
  • 3D model files: efr32bg22c222f352gm40-c-etched.step / efr32bg22c222f352gm40-c-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); efr32bg22c222f352gm40-c.step / efr32bg22c222f352gm40-c.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: SILICON LABS datasheet (103 pp, sha256 a6edd21c47bb5245, retrieved 2026-10-30, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF