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EFR32BG22C222F352GM32-C

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by adom

SILICON LABS RF Transceiver ICs, QFN-32-EP(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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EFR32BG22C222F352GM32-C

SILICON LABS · RF Transceiver ICs · QFN-32-EP(4x4)

EFR32BG22C222F352GM32-C from SILICON LABS, in a QFN-32-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PC00 bidirectional GPIO; alternate functions GPIO.EM4WU6 and GPIO.THMSW_EN.
2 PC01 bidirectional General-purpose I/O.
3 PC02 bidirectional General-purpose I/O.
4 PC03 bidirectional General-purpose I/O.
5 PC04 bidirectional General-purpose I/O.
6 PC05 bidirectional GPIO; alternate function GPIO.EM4WU7.
7 HFXTAL_I input High frequency crystal input.
8 HFXTAL_O output High frequency crystal output.
9 RESETn input Reset pin, internally pulled up to DVDD.
10 RFVDD power_in Radio power supply.
11 RFVSS power_in Radio ground.
12 RF2G4_IO bidirectional 2.4 GHz single-ended RF input/output.
13 PAVDD power_in Power amplifier (PA) power supply.
14 PB02 bidirectional General-purpose I/O.
15 PB01 bidirectional GPIO; alternate function GPIO.EM4WU3.
16 PB00 bidirectional GPIO; alternate function IADC0.VREFN.
17 PA00 bidirectional GPIO; alternate function IADC0.VREFP.
18 PA01 bidirectional GPIO; alternate function GPIO.SWCLK (debug clock).
19 PA02 bidirectional GPIO; alternate function GPIO.SWDIO (debug data).
20 PA03 bidirectional GPIO; alternate functions GPIO.SWV, GPIO.TDO and GPIO.TRACEDATA0.
21 PA04 bidirectional GPIO; alternate functions GPIO.TDI and GPIO.TRACECLK.
22 PA05 bidirectional GPIO; alternate function GPIO.EM4WU0.
23 PA06 bidirectional General-purpose I/O.
24 DECOUPLE passive Decouple output for on-chip voltage regulator; an external decoupling capacitor is required at this pin.
25 VREGSW passive DCDC regulator switching node.
26 VREGVDD power_in DCDC regulator input supply.
27 VREGVSS power_in DCDC ground.
28 DVDD power_in Digital power supply.
29 AVDD power_in Analog power supply.
30 IOVDD power_in I/O power supply.
31 PD01 bidirectional GPIO; alternate functions LFXO.LFXTAL_I and LFXO.LF_EXTCLK.
32 PD00 bidirectional GPIO; alternate function LFXO.LFXTAL_O.
33 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer SILICON LABS
Package QFN-32-EP(4x4)
Category RF & Radio
Pins 33

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Storage temperature range TSTG -50 150 °C 18
Voltage on any supply pin VDDMAX -0.3 3.8 V 18
Junction temperature TJMAX 105 °C -G grade 18
Voltage ramp rate on any supply pin VDDRAMPMAX 1 V / µs 18
Voltage on HFXO pins VHFXOPIN -0.3 1.4 V 18
DC voltage on any GPIO pin VDIGPIN -0.3 V max VIOVDD + 0.3 18
DC voltage on RESETn pin VRESETn -0.3 3.8 V 18
Input RF level on RF2G4_IO PRFMAX2G4 10 dBm 18
Absolute voltage on RF pin RF2G4_IO VMAX2G4 -0.3 V max VPAVDD + 0.3 18
Total current into VDD power lines IVDDMAX 200 mA Source 18
Total current into VSS ground lines IVSSMAX 200 mA Sink 18
Current per I/O pin (sink) IIOMAX 50 mA Sink 18
Current per I/O pin (source) IIOMAX 50 mA Source 18
Current for all I/O pins (sink) IIOALLMAX 200 mA Sink 18
Current for all I/O pins (source) IIOALLMAX 200 mA Source 18
Operating ambient temperature range TA -40 85 °C -G temperature grade 19
DVDD supply voltage VDVDD 1.71 3 3.8 V EM0/1 19
AVDD supply voltage VAVDD 1.71 3 3.8 V 19
IOVDDx operating supply voltage VIOVDDx 1.71 3 3.8 V All IOVDD pins 19
PAVDD operating supply voltage VPAVDD 1.71 3 3.8 V 19
VREGVDD operating supply voltage VVREGVDD 2.2 3 3.8 V DC-DC in regulation 19
VREGVDD operating supply voltage, DC-DC bypass VVREGVDD 1.8 3 3.8 V DC-DC in bypass 60 mA load 19
VREGVDD operating supply voltage, DC-DC not in use VVREGVDD 1.71 3 3.8 V DC-DC not in use. DVDD externally shorted to VREGVDD 19
DECOUPLE output capacitor CDECOUPLE 1 2.75 µF 1.0 µF ± 10% X8L capacitor used for performance characterization. 19
HCLK and SYSCLK frequency fHCLK 76.8 MHz VSCALE2, MODE = WS1 19
DC-DC regulated output accuracy ACCDC -2.5 3.3 % VVREGVDD ≥ 2.2 V, Steady state in EM0/EM1 mode or EM2/EM3 mode 21
DC-DC regulation total accuracy ACCTOT -5 7 % With mode transitions between EM0/EM1 and EM2/EM3 modes 21
DC-DC output load current ILOAD 60 mA EM0/EM1 mode, DCDC in regulation 21
DC-DC output capacitor CDCDC 4.7 10 µF 4.7 µF ± 10% X7R capacitor used for performance characterization 21
DC-DC nominal inductor LDCDC 2.2 µH ± 20% tolerance 21
Resistance in bypass mode RBYP 1.75 3 Ω Bypass switch from VREGVDD to DVDD, VVREGVDD = 1.8 V 21
Supply monitor threshold accuracy VCMP_ACC -5 5 % Supply falling edge trip point 21
Thermal resistance junction to ambient QFN32 4x4 THETAJA_QFN32_4X4 35.4 °C/W 4-Layer PCB, Natural Convection 24
Flash supply voltage during write or erase VFLASH 1.71 3.8 V 33
Flash erase cycles before failure ECFLASH 10000 cycles TA ≤ 125 °C 33
Flash data retention RETFLASH 10 years TA ≤ 125 °C 33
Program time, one word tPROG 42.1 44 45.6 uSec one word (32-bits) 33
Page erase time tPERASE 11.4 12.9 14.4 ms 33
Mass erase time tMERASE 11.7 13 14.3 ms Erases all of User Code area 33
HFXO supported crystal ESR ESRHFXO_38M4 40 60 Ω 38.4 MHz, CL = 10 pF 49
HFRCO frequency accuracy FHFRCO_ACC -3 3 % For all production calibrated frequencies 51
FSRCO frequency FFSRCO 17.2 20 21.2 MHz 52
LFRCO frequency accuracy, normal mode FLFRCO_ACC -3 3 % Normal mode 53
LFRCO frequency accuracy, precision mode FLFRCO_ACC -500 500 ppm Precision mode, across operating temperature range 53
ULFRCO oscillation frequency FULFRCO 0.944 1 1.095 kHz 53
GPIO leakage current, 3.8 V 85 °C ILEAK_IO 150 nA MODEx = DISABLED, IOVDD = 3.8 V TA = 85 °C 54
Input low voltage, GPIO VIL 0.3 V Any GPIO pin; max 0.3*IOVDD 54
Input high voltage, GPIO VIH 0.7 V Any GPIO pin; min 0.7*IOVDD 54
Output high voltage VOH 0.8 V Sourcing 20mA, IOVDD = 3.0 V; min 0.8*IOVDD 54
Output low voltage VOL 0.2 V Sinking 20mA, IOVDD = 3.0 V; max 0.2*IOVDD 54
RF tuning frequency range FRANGE 2400 2483.5 MHz 36

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
housing PC 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. 86

CAD (KiCad official)

  • Symbol: EFR32BG22C222F352GM32-C
  • Footprint: Package_DFN_QFN:QFN-32-1EP_4x4mm_P0.4mm_EP2.9x2.9mm
  • 3D model: QFN-32-EP(4x4) (KiCad packages3D, STEP)
  • 3D model files: efr32bg22c222f352gm32-c-etched.step / efr32bg22c222f352gm32-c-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); efr32bg22c222f352gm32-c.step / efr32bg22c222f352gm32-c.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: SILICON LABS datasheet (101 pp, sha256 9dc49fc97500e829, retrieved 2026-10-27, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF