component

EFM8UB11F16G-C-QSOP24

Public Made by Adom

by adom

SILICON LABS Pre-ordered MCUs, QSOP-24-150mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentembedded processors & controllersefm8ub11f16g-c-qsop24factory-2.0.0extractor-text

Verified EFM8UB11F16G-C-QSOP24

by Ray · last 31 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

31 Oct 2026RayPublished by the parts factory: tier lcsc, 24 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: EFM8UB11F16G-C-QSOP24 · QSOP-24-150mil · 24 pins
  • ✓copper: 24 copper pads, none touching another net
  • ✓datasheet: all 24 pin names found in the 64-page datasheet
  • ✓distributor: lcsc C1341711, digikey 336-3411-5-ND, mouser 634-8UB11F16GCQSOP24
  • ✓family: QSOP-24_3.9x8.7mm_P0.635mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-8mfgkpim/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height and body within the datasheet's package drawing (datasheet p.54)
  • ✓pads: 24 pins = 24 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 24 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ efm8ub11f16g-c-qsop24.kicad_sym✓ efm8ub11f16g-c-qsop24.kicad_mod✓ efm8ub11f16g-c-qsop24.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray
viewers efm8ub11f16g-c-qsop24: viewers · Ray
efm8ub11f16g-c-qsop24-etched.glb Publish 0.1.0 · Ray
efm8ub11f16g-c-qsop24-etched.step efm8ub11f16g-c-qsop24: factory component page (tier=lcsc) · Ray
efm8ub11f16g-c-qsop24-hero.glb efm8ub11f16g-c-qsop24: hero GLB from the etched model (keeps the MPN mark) · Ray
efm8ub11f16g-c-qsop24-hero.overlay.json Publish 0.1.0 · Ray
efm8ub11f16g-c-qsop24.glb Publish 0.1.0 · Ray
efm8ub11f16g-c-qsop24.kicad_mod Publish 0.1.0 · Ray
efm8ub11f16g-c-qsop24.kicad_sym Publish 0.1.0 · Ray
efm8ub11f16g-c-qsop24.lbr Publish 0.1.0 · Ray
efm8ub11f16g-c-qsop24.step Publish 0.1.0 · Ray
package.json Publish 0.1.0 · Ray
page.json Set visibility: public · Ray
README.md Publish 0.1.0 · Ray
verification.json Verified: Published by the parts factory: tier lcsc, 24 pins · Ray

EFM8UB11F16G-C-QSOP24

SILICON LABS · Pre-ordered MCUs · QSOP-24-150mil

EFM8UB11F16G-C-QSOP24 from SILICON LABS, in a QSOP-24-150mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 P0.2 bidirectional Multifunction I/O with crossbar capability, also providing P0MAT.2, INT0.2/INT1.2, ADC0.2 and CMP0P.2/CMP0N.2 functions; all pins are 5 V tolerant under bias.
2 P0.1 bidirectional Multifunction I/O with crossbar capability, also providing P0MAT.1, INT0.1/INT1.1, ADC0.1 and CMP0P.1/CMP0N.1 functions; the datasheet also lists AGND against this pin's analog functions.
3 P0.0 bidirectional Multifunction I/O with crossbar capability, also providing P0MAT.0, INT0.0/INT1.0, ADC0.0 and CMP0P.0/CMP0N.0 functions; the datasheet also lists VREF against this pin's analog functions.
4 GND power_in Ground pin.
5 D+ bidirectional USB Data Positive, also available as ADC0.28; the USB transceiver is low-power full/low-speed.
6 D- bidirectional USB Data Negative, also available as ADC0.29; the USB transceiver is low-power full/low-speed.
7 VIO power_in I/O Power Input that supplies the external I/O pins.
8 VDD power_in Supply Power Input / 5V Regulator Output; all internal circuitry draws power from VDD.
9 VREGIN power_in 5V Regulator Input for the on-chip 5 V-to-3.3 V LDO regulator, allowing direct connection to a USB supply.
10 P3.1 / VBUS bidirectional Multifunction I/O (GPIO) with VBUS function; P3.1 is not available on the crossbar in this package.
11 RSTb / C2CK input Active-low Reset input that doubles as the C2 Debug Clock.
12 P2.0 / C2D bidirectional Multifunction I/O with C2 Debug Data function; the C2D pin is not available on the crossbar in this package.
13 P1.6 bidirectional Multifunction I/O with crossbar capability, also providing P1MAT.6, I2C0_SCL, ADC0.14, CMP1P.9 and CMP1N.9 functions.
14 P1.5 bidirectional Multifunction I/O with crossbar capability, also providing P1MAT.5, I2C0_SDA, ADC0.13, CMP1P.7 and CMP1N.7 functions.
15 P1.4 bidirectional Multifunction I/O with crossbar capability, also providing P1MAT.4, ADC0.12, CMP1P.6 and CMP1N.6 functions.
16 P1.3 bidirectional Multifunction I/O with crossbar capability, also providing P1MAT.3, ADC0.11, CMP1P.5 and CMP1N.5 functions.
17 P1.2 bidirectional Multifunction I/O with crossbar capability, also providing P1MAT.2, I2C0_SCL, ADC0.10, CMP1P.4 and CMP1N.4 functions.
18 P1.1 bidirectional Multifunction I/O with crossbar capability, also providing P1MAT.1, I2C0_SDA, ADC0.9, CMP1P.3 and CMP1N.3 functions.
19 P1.0 bidirectional Multifunction I/O with crossbar capability, also providing P1MAT.0, ADC0.8, CMP1P.2 and CMP1N.2 functions.
20 P0.7 bidirectional Multifunction I/O with crossbar capability, also providing P0MAT.7, INT0.7/INT1.7, ADC0.7, CMP1P.1, CMP1N.1, CMP0P.7 and CMP0N.7 functions.
21 P0.6 bidirectional Multifunction I/O with crossbar capability, also providing P0MAT.6, CNVSTR, INT0.6/INT1.6, ADC0.6, CMP1P.0, CMP1N.0, CMP0P.6 and CMP0N.6 functions.
22 P0.5 bidirectional Multifunction I/O with crossbar capability, also providing P0MAT.5, INT0.5/INT1.5, UART0_RX, ADC0.5, CMP0P.5 and CMP0N.5 functions.
23 P0.4 bidirectional Multifunction I/O with crossbar capability, also providing P0MAT.4, INT0.4/INT1.4, UART0_TX, ADC0.4, CMP0P.4 and CMP0N.4 functions.
24 P0.3 bidirectional Multifunction I/O with crossbar capability, also providing P0MAT.3, EXTCLK, INT0.3/INT1.3, ADC0.3, CMP0P.3 and CMP0N.3 functions.

Key specifications

Parameter Value
Manufacturer SILICON LABS
Package QSOP-24-150mil
Category Embedded Processors & Controllers
Pins 24

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Operating Supply Voltage on VDD VDD 2.2 3.6 V 16
Operating Supply Voltage on VIO VIO 1.71 V Max printed as VDD 16
Operating Supply Voltage on VREGIN VREGIN 3 5.25 V 16
System Clock Frequency fSYSCLK 0 50 MHz 16
Operating Ambient Temperature TA -40 85 °C 16
Digital Core Supply Current, Normal Mode IDD 9.4 10.1 mA Full speed, code executing from flash; FSYSCLK = 48 MHz (HFOSC1) 17
Digital Core Supply Current, Normal Mode IDD 4.5 5.2 mA Full speed, code executing from flash; FSYSCLK = 24.5 MHz (HFOSC0) 17
Digital Core Supply Current, Idle Mode IDD 6.3 6.8 mA Core halted with peripherals running; FSYSCLK = 48 MHz (HFOSC1) 17
Digital Core Supply Current, Idle Mode IDD 2.9 3.3 mA Core halted with peripherals running; FSYSCLK = 24.5 MHz (HFOSC0) 17
Oscillator Frequency, High Frequency Oscillator 0 (24.5 MHz) fHFOSC0 24 24.5 25 MHz Full Temperature and Supply Range 21
Oscillator Frequency, High Frequency Oscillator 1 (48 MHz) fHFOSC1 47.3 48 48.7 MHz Full Temperature and Supply Range 21
Oscillator Frequency, Low Frequency Oscillator (80 kHz) fLFOSC 75 80 85 kHz Full Temperature and Supply Range 21
External Input CMOS Clock Frequency (at EXTCLK pin) fCMOS 0 50 MHz 21
External Input CMOS Clock High Time tCMOSH 9 ns 21
External Input CMOS Clock Low Time tCMOSL 9 ns 21
Throughput Rate (High Speed Mode) fS 200 ksps 12 Bit Mode 22
Throughput Rate (High Speed Mode) fS 800 ksps 10 Bit Mode 22
Throughput Rate (Low Power Mode) fS 62.5 ksps 12 Bit Mode 22
Throughput Rate (Low Power Mode) fS 250 ksps 10 Bit Mode 22
Tracking Time tTRK 230 ns High Speed Mode 22
Tracking Time tTRK 450 ns Low Power Mode 22
Power-On Time tPWR 1.2 μs 22
SAR Clock Frequency fSAR 6.25 MHz High Speed Mode, Reference is 2.4 V internal 22
SAR Clock Frequency fSAR 12.5 MHz High Speed Mode, Reference is not 2.4 V internal 22
SAR Clock Frequency fSAR 4 MHz Low Power Mode 22
Input Voltage Range VIN 0 V Gain = 1; max printed as VREF 22
Voltage Reference Range VREF 1 V Max printed as VDD 22
Integral Nonlinearity INL -2.3 1 2.3 LSB 12 Bit Mode; printed ±1 typ, ±2.3 max 22
Integral Nonlinearity INL -0.6 0.2 0.6 LSB 10 Bit Mode; printed ±0.2 typ, ±0.6 max 22
Differential Nonlinearity (Guaranteed Monotonic) DNL -1 0.7 1.9 LSB 12 Bit Mode 22
Differential Nonlinearity (Guaranteed Monotonic) DNL -0.6 0.2 0.6 LSB 10 Bit Mode; printed ±0.2 typ, ±0.6 max 22
Offset Error EOFF -3 0 3 LSB 12 Bit Mode, VREF = 1.65 V 22
Offset Error EOFF -2 0 2 LSB 10 Bit Mode, VREF = 1.65 V 22
Slope Error EM -0.1 0.02 0.1 % 12 Bit Mode; printed ±0.02 typ, ±0.1 max 23
Slope Error EM -0.24 0.06 0.24 % 10 Bit Mode; printed ±0.06 typ, ±0.24 max 23
Signal-to-Noise SNR 61 66 dB 12 Bit Mode; 10 kHz sine wave input, 1 dB below full scale, max throughput, AGND pin 23
Signal-to-Noise SNR 53 60 dB 10 Bit Mode; 10 kHz sine wave input, 1 dB below full scale, max throughput, AGND pin 23
Internal Fast Settling Reference Output Voltage (1.65 V Setting) VREFFS 1.62 1.65 1.68 V Full Temperature and Supply Range 23
Internal Fast Settling Reference Output Voltage (2.4 V Setting) VREFFS 2.35 2.4 2.45 V 2.4 V Setting, VDD > 2.6 V 23
Internal Fast Settling Reference Turn-on Time tREFFS 1.5 μs 23
1.8 V Internal LDO Output Voltage VOUT_1.8V 1.78 1.85 1.92 V 24
5 V Regulator Input Voltage Range VREGIN 3 5.25 V Input range to meet Output Voltage on VDD specification 24
5 V Regulator Output Voltage on VDD, Regulation Range VREGOUT 3.1 3.3 3.6 V Output Current = 1 to 100 mA; regulation range (VREGIN ≥ 4.1 V) 24
5 V Regulator Output Current IREGOUT 100 mA 24
5 V Regulator Dropout Voltage VDROPOUT 0.8 V Output Current = 100 mA 24
Ambient Temperature Under Bias TBIAS -55 125 °C 30
Storage Temperature TSTG -65 150 °C 30
Voltage on VDD VDD -0.3 4.2 V Min printed as GND-0.3 (referenced to GND) 30
Voltage on VIO VIO -0.3 4.2 V Min printed as GND-0.3 (referenced to GND) 30
Voltage on VREGIN VREGIN -0.3 5.8 V Min printed as GND-0.3 (referenced to GND) 30
Voltage on D+ or D- VUSBD -0.3 V Max printed as VDD+0.3 V; min printed as GND-0.3 30
Voltage on I/O pins (including VBUS / P3.1) or RSTb VIN -0.3 5.8 V VIO > 3.3 V; min printed as GND-0.3 30
Voltage on I/O pins (including VBUS / P3.1) or RSTb VIN -0.3 V VIO < 3.3 V; max printed as VIO+2.5 V; min printed as GND-0.3 30
Total Current Sunk into Supply Pin IVDD 400 mA 30
Total Current Sourced out of Ground Pin IGND 400 mA 30
Current Sourced or Sunk by any I/O Pin or RSTb IIO -100 100 mA 30
Operating Junction Temperature TJ -40 105 °C 30
Thermal Resistance (Junction to Ambient), QSOP-24 Package θJA 65 °C/W 30

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
housing PC 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. 51

CAD (KiCad official)

  • Symbol: EFM8UB11F16G-C-QSOP24
  • Footprint: Package_SO:QSOP-24_3.9x8.7mm_P0.635mm
  • 3D model: QSOP-24-150mil (KiCad packages3D, STEP)
  • 3D model files: efm8ub11f16g-c-qsop24-etched.step / efm8ub11f16g-c-qsop24-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); efm8ub11f16g-c-qsop24.step / efm8ub11f16g-c-qsop24.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: SILICON LABS datasheet (64 pp, sha256 3e758157389e7851, retrieved 2026-10-31, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF