component
EFM8SB20F32G-B-QFP32
Public Made by Adomby adom
SILICON LABS Pre-ordered MCUs, QFP-32(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
PCB Footprint
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
Datasheet
Open in new tab ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
Contents
README
markdownEFM8SB20F32G-B-QFP32
SILICON LABS · Pre-ordered MCUs · QFP-32(7x7)
EFM8SB20F32G-B-QFP32 from SILICON LABS, in a QFP-32(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model). Symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | N/C | unconnected | No connection; the pin definitions table lists this pin as no connection. |
| 2 | GND | power_in | Ground pin for the device. |
| 3 | VDD | power_in | Supply power input; the device is specified for a single supply of 1.8 to 3.6 V. |
| 4 | N/C | unconnected | No connection; the pin definitions table lists this pin as no connection. |
| 5 | N/C | unconnected | No connection; the pin definitions table lists this pin as no connection. |
| 6 | RSTb / C2CK | input | Active-low reset input that is also the C2 debug clock (C2CK). |
| 7 | P2.7 / C2D | bidirectional | Multifunction I/O that is also the C2 debug data line (C2D); the table lists no crossbar capability for this pin. |
| 8 | P2.6 | bidirectional | Multifunction I/O with crossbar capability, also available as EMIF_WRb, ADC0.22, CMP0P.11 and CMP1P.11. |
| 9 | XTAL4 | passive | RTC crystal connection XTAL4 for the external 32 kHz RTC crystal. |
| 10 | XTAL3 | passive | RTC crystal connection XTAL3 for the external 32 kHz RTC crystal. |
| 11 | P2.5 | bidirectional | Multifunction I/O with crossbar capability, also available as EMIF_RDb, ADC0.21, CMP0N.10 and CMP1N.10. |
| 12 | P2.4 | bidirectional | Multifunction I/O with crossbar capability, also available as EMIF_ALE, ADC0.20, CMP0P.10 and CMP1P.10. |
| 13 | P2.3 | bidirectional | Multifunction I/O with crossbar capability, also available as EMIF_A11, ADC0.19, CMP0N.9 and CMP1N.9. |
| 14 | P2.2 | bidirectional | Multifunction I/O with crossbar capability, also available as EMIF_A10, ADC0.18, CMP0P.9 and CMP1P.9. |
| 15 | P2.1 | bidirectional | Multifunction I/O with crossbar capability, also available as EMIF_A9, ADC0.17, CMP0N.8 and CMP1N.8. |
| 16 | P2.0 | bidirectional | Multifunction I/O with crossbar capability, also available as EMIF_A8, ADC0.16, CMP0P.8 and CMP1P.8. |
| 17 | P1.7 | bidirectional | Multifunction I/O with crossbar capability, also available as P1MAT.7, EMIF_AD7, ADC0.15, CMP0N.7 and CMP1N.7. |
| 18 | P1.6 | bidirectional | Multifunction I/O with crossbar capability, also available as P1MAT.6, EMIF_AD6, ADC0.14, CMP0P.7 and CMP1P.7. |
| 19 | P1.5 | bidirectional | Multifunction I/O with crossbar capability, also available as P1MAT.5, EMIF_AD5, ADC0.13, CMP0N.6 and CMP1N.6. |
| 20 | P1.4 | bidirectional | Multifunction I/O with crossbar capability, also available as P1MAT.4, EMIF_AD4, ADC0.12, CMP0P.6 and CMP1P.6. |
| 21 | P1.3 | bidirectional | Multifunction I/O with crossbar capability, also available as P1MAT.3, SPI1_NSS, EMIF_AD3, ADC0.11, CMP0N.5 and CMP1N.5. |
| 22 | P1.2 | bidirectional | Multifunction I/O with crossbar capability, also available as P1MAT.2, SPI1_MOSI, EMIF_AD2, ADC0.10, CMP0P.5 and CMP1P.5. |
| 23 | P1.1 | bidirectional | Multifunction I/O with crossbar capability, also available as P1MAT.1, SPI1_MISO, EMIF_AD1, ADC0.9, CMP0N.4 and CMP1N.4. |
| 24 | P1.0 | bidirectional | Multifunction I/O with crossbar capability, also available as P1MAT.0, SPI1_SCK, EMIF_AD0, ADC0.8, CMP0P.4 and CMP1P.4. |
| 25 | P0.7 | bidirectional | Multifunction I/O with crossbar capability, also available as P0MAT.7, INT0.7, INT1.7, ADC0.7, IREF0, CMP0N.3 and CMP1N.3. |
| 26 | P0.6 | bidirectional | Multifunction I/O with crossbar capability, also available as P0MAT.6, CNVSTR, INT0.6, INT1.6, ADC0.6, CMP0P.3 and CMP1P.3. |
| 27 | P0.5 | bidirectional | Multifunction I/O with crossbar capability, also available as P0MAT.5, INT0.5, INT1.5, ADC0.5, CMP0N.2 and CMP1N.2. |
| 28 | P0.4 | bidirectional | Multifunction I/O with crossbar capability, also available as P0MAT.4, INT0.4, INT1.4, ADC0.4, CMP0P.2 and CMP1P.2. |
| 29 | P0.3 | bidirectional | Multifunction I/O with crossbar capability, also available as P0MAT.3, EXTCLK, INT0.3, INT1.3, ADC0.3, XTAL2, CMP0N.1 and CMP1N.1. |
| 30 | P0.2 | bidirectional | Multifunction I/O with crossbar capability, also available as P0MAT.2, INT0.2, INT1.2, ADC0.2, XTAL1, CMP0P.1 and CMP1P.1. |
| 31 | P0.1 | bidirectional | Multifunction I/O with crossbar capability, also available as P0MAT.1, INT0.1, INT1.1, ADC0.1, AGND, CMP0N.0 and CMP1N.0. |
| 32 | P0.0 | bidirectional | Multifunction I/O with crossbar capability, also available as P0MAT.0, INT0.0, INT1.0, ADC0.0, VREF, CMP0P.0 and CMP1P.0. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | SILICON LABS |
| Package | QFP-32(7x7) |
| Category | Embedded Processors & Controllers |
| Pins | 32 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Operating Supply Voltage on VDD | VDD | 1.8 | 2.4 | 3.6 | V | 13 | |
| Minimum RAM Data Retention Voltage on VDD (Sleep Mode) | VRAM | 0.3 | 0.5 | V | Sleep Mode | 13 | |
| System Clock Frequency | fSYSCLK | 0 | 25 | MHz | 13 | ||
| Operating Ambient Temperature | TA | -40 | 85 | °C | 13 | ||
| Normal Mode supply current (full speed, code executing from flash) | IDD | 4.1 | 5 | mA | VDD = 1.8-3.6 V, fSYSCLK = 24.5 MHz | 14 | |
| Idle Mode supply current (core halted, peripherals running) | IDD | 2.5 | 3 | mA | VDD = 1.8-3.6 V, fSYSCLK = 24.5 MHz | 14 | |
| External Input CMOS Clock Frequency (at EXTCLK pin) | fCMOS | 0 | 25 | MHz | 18 | ||
| External Input CMOS Clock High Time | tCMOSH | 18 | ns | 18 | |||
| External Input CMOS Clock Low Time | tCMOSL | 18 | ns | 18 | |||
| ADC Throughput Rate | fS | 300 | ksps | 19 | |||
| ADC Tracking Time | tTRK | 1.5 | µs | 19 | |||
| ADC Power-On Time | tPWR | 1.5 | µs | 19 | |||
| ADC SAR Clock Frequency | fSAR | 8.33 | MHz | High Speed Mode | 19 | ||
| ADC Conversion Time | TCNV | 13 | Clocks | 19 | |||
| ADC Voltage Reference Range | VREF | 1 | V | 19 | |||
| ADC Input Voltage Range (Gain = 1) | VIN | 0 | V | Gain = 1 | 19 | ||
| ADC Input Voltage Range (Gain = 0.5) | VIN | 0 | V | Gain = 0.5 | 19 | ||
| ADC Integral Nonlinearity | INL | -1 | 0.5 | 1 | LSB | 19 | |
| ADC Differential Nonlinearity (Guaranteed Monotonic) | DNL | -1 | 0.5 | 1 | LSB | 19 | |
| ADC Offset Error | EOFF | -2 | 0 | 2 | LSB | VREF = 1.65 V | 19 |
| ADC Slope Error | EM | -0.24 | 0.06 | 0.24 | % | 19 | |
| ADC Signal-to-Noise Ratio | SNR | 54 | 58 | dB | 10 kHz sine wave input, 1 dB below full scale, max throughput | 19 | |
| ADC Signal-to-Noise Plus Distortion | SNDR | 54 | 58 | dB | 10 kHz sine wave input, 1 dB below full scale, max throughput | 19 | |
| Internal Fast Settling Reference Output Voltage | VREFFS | 1.6 | 1.65 | 1.7 | V | 20 | |
| Internal Fast Settling Reference Turn-on Time | tVREFFS | 1.5 | µs | 20 | |||
| On-chip Precision Reference Output Voltage | VREFP | 1.645 | 1.68 | 1.715 | V | 20 | |
| External Reference Input Voltage | VEXTREF | 1 | V | 20 | |||
| Output Low Voltage (High Drive) | VOL | 0.6 | V | IOL = 8.5 mA | 23 | ||
| Output Low Voltage (Low Drive) | VOL | 0.6 | V | IOL = 1.4 mA | 23 | ||
| Input Low Voltage | VIL | 0.6 | V | VDD = 2.0 to 3.6 V | 23 | ||
| Weak Pull-Up Current | IPU | -35 | -20 | µA | VDD = 3.6 V, VIN = 0 V | 23 | |
| Input Leakage Current | ILK | -1 | 1 | µA | Weak pullup disabled or pin in analog mode | 23 | |
| Thermal Resistance, junction to ambient (QFP-32 package) | θJA | 80 | °C/W | QFP-32 Packages | 23 | ||
| Ambient Temperature Under Bias | TBIAS | -55 | 125 | °C | 24 | ||
| Storage Temperature | TSTG | -65 | 150 | °C | 24 | ||
| Voltage on VDD | VDD | 4 | V | 24 | |||
| Voltage on I/O pins or RSTb | VIN | 5.8 | V | VDD > 2.2 V | 24 | ||
| Total Current Sunk into Supply Pin | IVDD | 400 | mA | 24 | |||
| Total Current Sourced out of Ground Pin | IGND | 400 | mA | 24 | |||
| Current Sourced or Sunk by Any I/O Pin or RSTb | IIO | -100 | 100 | mA | 24 | ||
| Maximum Total Current through all Port Pins | IIOTOT | 200 | mA | 24 | |||
| Operating Junction Temperature | TJ | -40 | 105 | °C | 24 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | PC | 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components. | 41 |
CAD (KiCad official)
- Symbol:
EFM8SB20F32G-B-QFP32 - Footprint:
Package_QFP:LQFP-32_7x7mm_P0.8mm - 3D model: QFP-32(7x7) (KiCad packages3D, STEP)
- 3D model files:
efm8sb20f32g-b-qfp32-etched.step/efm8sb20f32g-b-qfp32-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);efm8sb20f32g-b-qfp32.step/efm8sb20f32g-b-qfp32.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: SILICON LABS datasheet (55 pp, sha256
bd12812dfeaa3893, retrieved 2026-11-13, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).