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EFM8SB20F32G-B-QFN32R

Public Made by Adom

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SILICON LABS Microcontroller Units (MCUs/MPUs/SOCs), QFN-32-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentsingle chip microcomputer-microcontrollerefm8sb20f32g-b-qfn32rfactory-2.0.0extractor-text

Verified EFM8SB20F32G-B-QFN32R

by Ray · last 9 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

9 Nov 2026RayPublished by the parts factory: tier lcsc, 33 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: EFM8SB20F32G-B-QFN32R · QFN-32-EP(5x5) · 33 pins
  • ✓copper: 33 copper pads, none touching another net
  • ✓datasheet: all 33 pin names found in the 55-page datasheet
  • ✓distributor: lcsc C2054012, digikey 2832-EFM8SB20F32G-B-QFN32RTR-ND, mouser 634-EFM8SB32GBQFN32R
  • ✓family: QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-v15kukb5/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 33 pins = 33 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 33 pins agree
  • ✓symbol_text: no pin names collide
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ efm8sb20f32g-b-qfn32r.kicad_sym✓ efm8sb20f32g-b-qfn32r.kicad_mod✓ efm8sb20f32g-b-qfn32r.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray
viewers efm8sb20f32g-b-qfn32r: viewers · Ray
efm8sb20f32g-b-qfn32r-etched.glb Publish 0.1.0 · Ray
efm8sb20f32g-b-qfn32r-etched.step efm8sb20f32g-b-qfn32r: factory component page (tier=lcsc) · Ray
efm8sb20f32g-b-qfn32r-hero.glb efm8sb20f32g-b-qfn32r: hero GLB from the etched model (keeps the MPN mark) · Ray
efm8sb20f32g-b-qfn32r-hero.overlay.json Publish 0.1.0 · Ray
efm8sb20f32g-b-qfn32r.glb Publish 0.1.0 · Ray
efm8sb20f32g-b-qfn32r.kicad_mod Publish 0.1.0 · Ray
efm8sb20f32g-b-qfn32r.kicad_sym Publish 0.1.0 · Ray
efm8sb20f32g-b-qfn32r.lbr Publish 0.1.0 · Ray
efm8sb20f32g-b-qfn32r.step Publish 0.1.0 · Ray
package.json Publish 0.1.0 · Ray
page.json Set visibility: public · Ray
README.md Publish 0.1.0 · Ray
verification.json Verified: Published by the parts factory: tier lcsc, 33 pins · Ray

EFM8SB20F32G-B-QFN32R

SILICON LABS · Microcontroller Units (MCUs/MPUs/SOCs) · QFN-32-EP(5x5)

EFM8SB20F32G-B-QFN32R from SILICON LABS, in a QFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 N/C unconnected No connection.
2 GND power_in Ground.
3 VDD power_in Supply power input; the device is specified for a single 1.8 to 3.6 V supply.
4 N/C unconnected No connection.
5 N/C unconnected No connection.
6 RSTb / C2CK bidirectional Active-low reset input that doubles as the C2 debug clock.
7 P2.7 / C2D bidirectional Multifunction I/O that doubles as the C2 debug data line.
8 P2.6 bidirectional Multifunction crossbar I/O with EMIF_WRb, ADC0.22, CMP0P.11 and CMP1P.11 functions.
9 XTAL4 passive RTC crystal connection (XTAL4).
10 XTAL3 passive RTC crystal connection (XTAL3).
11 P2.5 bidirectional Multifunction crossbar I/O with EMIF_RDb, ADC0.21, CMP0N.10 and CMP1N.10 functions.
12 P2.4 bidirectional Multifunction crossbar I/O with EMIF_ALE, ADC0.20, CMP0P.10 and CMP1P.10 functions.
13 P2.3 bidirectional Multifunction crossbar I/O with EMIF_A11, ADC0.19, CMP0N.9 and CMP1N.9 functions.
14 P2.2 bidirectional Multifunction crossbar I/O with EMIF_A10, ADC0.18, CMP0P.9 and CMP1P.9 functions.
15 P2.1 bidirectional Multifunction crossbar I/O with EMIF_A9, ADC0.17, CMP0N.8 and CMP1N.8 functions.
16 P2.0 bidirectional Multifunction crossbar I/O with EMIF_A8, ADC0.16, CMP0P.8 and CMP1P.8 functions.
17 P1.7 bidirectional Multifunction crossbar I/O with P1MAT.7, EMIF_AD7, ADC0.15, CMP0N.7 and CMP1N.7 functions.
18 P1.6 bidirectional Multifunction crossbar I/O with P1MAT.6, EMIF_AD6, ADC0.14, CMP0P.7 and CMP1P.7 functions.
19 P1.5 bidirectional Multifunction crossbar I/O with P1MAT.5, EMIF_AD5, ADC0.13, CMP0N.6 and CMP1N.6 functions.
20 P1.4 bidirectional Multifunction crossbar I/O with P1MAT.4, EMIF_AD4, ADC0.12, CMP0P.6 and CMP1P.6 functions.
21 P1.3 bidirectional Multifunction crossbar I/O with P1MAT.3, SPI1_NSS, EMIF_AD3, ADC0.11, CMP0N.5 and CMP1N.5 functions.
22 P1.2 bidirectional Multifunction crossbar I/O with P1MAT.2, SPI1_MOSI, EMIF_AD2, ADC0.10, CMP0P.5 and CMP1P.5 functions.
23 P1.1 bidirectional Multifunction crossbar I/O with P1MAT.1, SPI1_MISO, EMIF_AD1, ADC0.9, CMP0N.4 and CMP1N.4 functions.
24 P1.0 bidirectional Multifunction crossbar I/O with P1MAT.0, SPI1_SCK, EMIF_AD0, ADC0.8, CMP0P.4 and CMP1P.4 functions.
25 P0.7 bidirectional Multifunction crossbar I/O with P0MAT.7, INT0.7, INT1.7, ADC0.7, IREF0, CMP0N.3 and CMP1N.3 functions.
26 P0.6 bidirectional Multifunction crossbar I/O with P0MAT.6, CNVSTR, INT0.6, INT1.6, ADC0.6, CMP0P.3 and CMP1P.3 functions.
27 P0.5 bidirectional Multifunction crossbar I/O with P0MAT.5, INT0.5, INT1.5, ADC0.5, CMP0N.2 and CMP1N.2 functions.
28 P0.4 bidirectional Multifunction crossbar I/O with P0MAT.4, INT0.4, INT1.4, ADC0.4, CMP0P.2 and CMP1P.2 functions.
29 P0.3 bidirectional Multifunction crossbar I/O with P0MAT.3, EXTCLK, INT0.3, INT1.3, ADC0.3, XTAL2, CMP0N.1 and CMP1N.1 functions.
30 P0.2 bidirectional Multifunction crossbar I/O with P0MAT.2, INT0.2, INT1.2, ADC0.2, CMP0P.1, CMP1P.1 and XTAL1 functions.
31 P0.1 bidirectional Multifunction crossbar I/O with P0MAT.1, INT0.1, INT1.1, ADC0.1, AGND, CMP0N.0 and CMP1N.0 functions.
32 P0.0 bidirectional Multifunction crossbar I/O with P0MAT.0, INT0.0, INT1.0, ADC0.0, CMP0P.0, CMP1P.0 and VREF functions.
33 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer SILICON LABS
Package QFN-32-EP(5x5)
Category Single Chip Microcomputer/Microcontroller
Pins 33

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
housing PC 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components. 41

CAD (KiCad official)

  • Symbol: EFM8SB20F32G-B-QFN32R
  • Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
  • 3D model: QFN-32-EP(5x5) (KiCad packages3D, STEP)
  • 3D model files: efm8sb20f32g-b-qfn32r-etched.step / efm8sb20f32g-b-qfn32r-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); efm8sb20f32g-b-qfn32r.step / efm8sb20f32g-b-qfn32r.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: SILICON LABS datasheet (55 pp, sha256 bd12812dfeaa3893, retrieved 2026-11-09, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF