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EFM8SB10F8G-A-QFN20

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SILICON LABS Microcontroller Units (MCUs/MPUs/SOCs), QFN-20-EP(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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EFM8SB10F8G-A-QFN20

SILICON LABS · Microcontroller Units (MCUs/MPUs/SOCs) · QFN-20-EP(3x3)

EFM8SB10F8G-A-QFN20 from SILICON LABS, in a QFN-20-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 P0.1 bidirectional Multifunction I/O with crossbar capability, also P0MAT.1, INT0.1, INT1.1, ADC0.1, CS0.1 and AGND functions.
2 P0.0 bidirectional Multifunction I/O with crossbar capability, also P0MAT.0, INT0.0, INT1.0, CS0.0 and VREF functions.
3 GND power_in Ground.
4 VDD power_in Supply power input (device specified for 1.8 to 3.6 V operation).
5 RSTb/C2CK bidirectional Active-low reset and C2 debug clock.
6 P2.7/C2D bidirectional Multifunction I/O and C2 debug data.
7 P1.7 bidirectional Multifunction I/O with crossbar capability, also P1MAT.7 and XTAL4.
8 P1.6 bidirectional Multifunction I/O with crossbar capability, also P1MAT.6 and XTAL3.
9 P1.5 bidirectional Multifunction I/O with crossbar capability, also P1MAT.5 and CS0.13.
10 P1.3 bidirectional Multifunction I/O with crossbar capability, also P1MAT.3, ADC0.11 and CS0.11.
11 P1.2 bidirectional Multifunction I/O with crossbar capability, also P1MAT.2, ADC0.10 and CS0.10.
12 GND power_in Ground.
13 P1.1 bidirectional Multifunction I/O with crossbar capability, also P1MAT.1, CMP0N.4 and CS0.9.
14 P1.0 bidirectional Multifunction I/O with crossbar capability, also P1MAT.0, CMP0P.4 and CS0.8.
15 P0.7 bidirectional Multifunction I/O with crossbar capability, also P0MAT.7, INT0.7, INT1.7, ADC0.7, CS0.7 and IREF0.
16 P0.6 bidirectional Multifunction I/O with crossbar capability, also P0MAT.6, CNVSTR, INT0.6, INT1.6, ADC0.6 and CS0.6.
17 P0.5 bidirectional Multifunction I/O with crossbar capability, also P0MAT.5, INT0.5, INT1.5, ADC0.5 and CS0.5.
18 P0.4 bidirectional Multifunction I/O with crossbar capability, also P0MAT.4, INT0.4, INT1.4, ADC0.4 and CS0.4.
19 P0.3 bidirectional Multifunction I/O with crossbar capability, also P0MAT.3, EXTCLK, WAKEOUT, INT0.3, INT1.3, ADC0.3, CS0.3 and XTAL2.
20 P0.2 bidirectional Multifunction I/O with crossbar capability, also P0MAT.2, RTCOUT, INT0.2, INT1.2, ADC0.2, CS0.2 and XTAL1.
21 GND power_in Center exposed pad, ground.

Key specifications

Parameter Value
Manufacturer SILICON LABS
Package QFN-20-EP(3x3)
Category Single Chip Microcomputer/Microcontroller
Pins 21

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Operating Supply Voltage on VDD VDD 1.8 2.4 3.6 V 14
Minimum RAM Data Retention Voltage on VDD (Sleep Mode) VRAM 0.3 0.5 V Sleep Mode 14
System Clock Frequency fSYSCLK 0 25 MHz 14
Operating Ambient Temperature TA -40 85 °C 14
Normal Mode supply current, full speed, code executing from flash IDD 3.6 4.5 mA VDD = 1.8-3.6 V, fSYSCLK = 24.5 MHz 15
Idle Mode supply current, core halted with peripherals running IDD 1.8 3 mA VDD = 1.8-3.6 V, fSYSCLK = 24.5 MHz 15
External Input CMOS Clock Frequency (at EXTCLK pin) fCMOS 0 25 MHz 19
External Input CMOS Clock High Time tCMOSH 18 ns 19
External Input CMOS Clock Low Time tCMOSL 18 ns 19
Throughput Rate fS 75 ksps 12 Bit Mode 20
Throughput Rate fS 300 ksps 10 Bit Mode 20
Tracking Time, initial acquisition tTRK 1.5 us Initial Acquisition 20
Tracking Time, subsequent acquisitions tTRK 1.1 us Subsequent Acquisitions (DC input, burst mode) 20
Power-On Time tPWR 1.5 µs 20
SAR Clock Frequency fSAR 8.33 MHz High Speed Mode 20
SAR Clock Frequency fSAR 4.4 MHz Low Power Mode 20
Conversion Time TCNV 13 Clocks 10-Bit Conversion 20
Integral Nonlinearity INL -1.5 1 1.5 LSB 12 Bit Mode 20
Integral Nonlinearity INL -1 0.5 1 LSB 10 Bit Mode 20
Differential Nonlinearity (Guaranteed Monotonic) DNL -1 0.8 1 LSB 12 Bit Mode 20
Differential Nonlinearity (Guaranteed Monotonic) DNL -1 0.5 1 LSB 10 Bit Mode 20
Offset Error EOFF -3 0 3 LSB 12 Bit Mode, VREF = 1.65 V 20
Offset Error EOFF -2 0 2 LSB 10 Bit Mode, VREF = 1.65 V 20
Slope Error EM -0.1 0.02 0.1 % 12 Bit Mode 20
Slope Error EM -0.24 0.06 0.24 % 10 Bit Mode 20
Signal-to-Noise SNR 62 65 dB 10 kHz Sine Wave Input 1dB below full scale, Max throughput; 12 Bit Mode 20
Signal-to-Noise SNR 54 58 dB 10 kHz Sine Wave Input 1dB below full scale, Max throughput; 10 Bit Mode 20
Signal-to-Noise Plus Distortion SNDR 62 65 dB 10 kHz Sine Wave Input 1dB below full scale, Max throughput; 12 Bit Mode 21
Signal-to-Noise Plus Distortion SNDR 54 58 dB 10 kHz Sine Wave Input 1dB below full scale, Max throughput; 10 Bit Mode 21
Internal Fast Settling Reference Output Voltage VREFFS 1.62 1.65 1.68 V 21
Internal Fast Settling Reference Turn-on Time tREFFS 1.5 µs 21
External Reference Input Voltage VEXTREF 1 V 21
Voltage Reference Range VREF 1 V 20
Input Voltage Range, Gain = 1 VIN 0 V Gain = 1 20
Input Voltage Range, Gain = 0.5 VIN 0 V Gain = 0.5 20
Thermal Resistance, QFN-20 Packages θJA 60 °C/W 29
Ambient Temperature Under Bias TBIAS -55 125 °C 29
Storage Temperature TSTG -65 150 °C 29
Voltage on VDD VDD 4 V 29
Total Current Sunk into Supply Pin IVDD 400 mA 29
Total Current Sourced out of Ground Pin IGND 400 mA 29
Current Sourced or Sunk by Any I/O Pin or RSTb IIO -100 100 mA 29
Maximum Total Current through all Port Pins IIOTOT 200 mA 29
Operating Junction Temperature TJ -40 105 °C 29

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
housing PC 5. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components. 47

CAD (KiCad official)

  • Symbol: EFM8SB10F8G-A-QFN20
  • Footprint: Package_DFN_QFN:UQFN-20-1EP_3x3mm_P0.4mm_EP1.85x1.85mm
  • 3D model: QFN-20-EP(3x3) (KiCad packages3D, STEP)
  • 3D model files: efm8sb10f8g-a-qfn20-etched.step / efm8sb10f8g-a-qfn20-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); efm8sb10f8g-a-qfn20.step / efm8sb10f8g-a-qfn20.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: SILICON LABS datasheet (71 pp, sha256 d01fe393424cb582, retrieved 2026-10-20, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF