component
EFM8LB12F32ES0-C-QFN24R
Public Made by Adomby adom
SILICON LABS Microcontroller Units (MCUs/MPUs/SOCs), QFN-24-EP(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownEFM8LB12F32ES0-C-QFN24R
SILICON LABS · Microcontroller Units (MCUs/MPUs/SOCs) · QFN-24-EP(3x3)
EFM8LB12F32ES0-C-QFN24R from SILICON LABS, in a QFN-24-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model). Symbol and footprint from KiCad-official CAD; the 3D model is generated from the datasheet's package dimensions.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | P0.1 | bidirectional | Multifunction I/O with crossbar, port match P0MAT.1, INT0.1/INT1.1, CLU0B.8, CLU2A.9, CLU3B.9, ADC0.0, CMP0P.0/CMP0N.0 and AGND analog functions. |
| 2 | P0.0 | bidirectional | Multifunction I/O with crossbar, port match P0MAT.0, INT0.0/INT1.0, CLU0A.8, CLU2A.8, CLU3B.8 and VREF analog function. |
| 3 | GND | power_in | Ground. |
| 4 | VDD / VIO | power_in | Supply power input; VDD and VIO are bonded to the same pin, with VDD operating range 2.2 V to 3.6 V. |
| 5 | RSTb / C2CK | bidirectional | Active-low reset input and C2 debug clock. |
| 6 | P3.0 / C2D | bidirectional | Multifunction I/O shared with C2 debug data; also the bootloader mode entry pin on QFN24. |
| 7 | P2.3 | bidirectional | Multifunction I/O with crossbar, port match P2MAT.3, CLU1B.15, CLU2B.15, CLU3A.15 and DAC3 output. |
| 8 | P2.2 | bidirectional | Multifunction I/O with crossbar, port match P2MAT.2, CLU1A.15, CLU2B.14, CLU3A.14 and DAC2 output. |
| 9 | P2.1 | bidirectional | Multifunction I/O with crossbar, port match P2MAT.1, CLU1B.14, CLU2A.15, CLU3B.15 and DAC1 output. |
| 10 | P2.0 | bidirectional | Multifunction I/O with crossbar, port match P2MAT.0, CLU1A.14, CLU2A.14, CLU3B.14 and DAC0 output. |
| 11 | P1.6 | bidirectional | Multifunction I/O with crossbar, P1MAT.6, CLU3OUT, CLU0A.15, CLU1B.12, CLU2A.12, ADC0.11 and CMP1P.5/CMP1N.5. |
| 12 | P1.5 | bidirectional | Multifunction I/O with crossbar, P1MAT.5, CLU2OUT, CLU0B.14, CLU1A.13, CLU2B.13, ADC0.10 and CMP1P.4/CMP1N.4. |
| 13 | P1.4 | bidirectional | Multifunction I/O with crossbar, P1MAT.4, I2C0_SCL, CLU0A.14, CLU1A.12, CLU2B.12, ADC0.9 and CMP1P.3/CMP1N.3. |
| 14 | P1.3 | bidirectional | Multifunction I/O with crossbar, P1MAT.3, I2C0_SDA, CLU0B.13, CLU1B.11, CLU2B.11, CLU3A.13 and CMP1P.2/CMP1N.2. |
| 15 | GND | power_in | Ground. |
| 16 | P1.2 | bidirectional | Multifunction I/O with crossbar, P1MAT.2, CLU0A.13, CLU1A.11, CLU2B.10, CLU3A.12 and ADC0.8. |
| 17 | P1.1 | bidirectional | Multifunction I/O with crossbar, P1MAT.1, CLU0B.12, CLU1B.10, CLU2A.11, CLU3B.13 and ADC0.7. |
| 18 | P1.0 | bidirectional | Multifunction I/O with crossbar, P1MAT.0, CLU0A.12, CLU1A.10, CLU2A.10, CLU3B.12 and ADC0.6. |
| 19 | P0.7 | bidirectional | Multifunction I/O with crossbar, P0MAT.7, INT0.7/INT1.7, CLU1OUT, CLU0B.11, CLU1B.9, CLU3A.11, ADC0.5, CMP0P.5/CMP0N.5 and CMP1P.1/CMP1N.1. |
| 20 | P0.6 | bidirectional | Multifunction I/O with crossbar, P0MAT.6, CNVSTR, INT0.6/INT1.6, CLU0A.11, CLU1B.8, CLU3A.10, ADC0.4, CMP0P.4/CMP0N.4 and CMP1P.0/CMP1N.0. |
| 21 | P0.5 | bidirectional | Multifunction I/O with crossbar, P0MAT.5, INT0.5/INT1.5, UART0_RX, CLU0B.10, CLU1A.9, CLU3B.11, ADC0.3 and CMP0P.3/CMP0N.3. |
| 22 | P0.4 | bidirectional | Multifunction I/O with crossbar, P0MAT.4, INT0.4/INT1.4, UART0_TX, CLU0A.10, CLU1A.8, CLU3B.10, ADC0.2 and CMP0P.2/CMP0N.2. |
| 23 | P0.3 | bidirectional | Multifunction I/O with crossbar, P0MAT.3, EXTCLK, INT0.3/INT1.3, CLU0B.9, CLU2B.9, CLU3A.9 and EXTOSC analog function. |
| 24 | P0.2 | bidirectional | Multifunction I/O with crossbar, P0MAT.2, INT0.2/INT1.2, CLU0OUT, CLU0A.9, CLU2B.8, CLU3A.8, ADC0.1 and CMP0P.1/CMP0N.1. |
| 25 | GND | power_in | Center exposed pad, Ground. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | SILICON LABS |
| Package | QFN-24-EP(3x3) |
| Category | Single Chip Microcomputer/Microcontroller |
| Pins | 25 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Operating Supply Voltage on VDD | VDD | 2.2 | 3.6 | V | 18 | ||
| Operating Supply Voltage on VIO | VIO | 2.2 | V | 18 | |||
| Operating Supply Voltage on VIO (second row, no symbol printed) | VIO | 1.713 | V | 18 | |||
| System Clock Frequency | fSYSCLK | 0 | 73.5 | MHz | 18 | ||
| Operating Ambient Temperature | TA | -40 | 105 | °C | 18 | ||
| Ambient Temperature Under Bias | TBIAS | -55 | 125 | °C | 36 | ||
| Storage Temperature | TSTG | -65 | 150 | °C | 36 | ||
| Voltage on VDD | VDD | 4.2 | V | 36 | |||
| Voltage on I/O pins or RSTb (VIO > 3.3 V) | VIN | 5.8 | V | VIO > 3.3 V | 36 | ||
| Total Current Sunk into Supply Pin | IVDD | 400 | mA | 36 | |||
| Total Current Sourced out of Ground Pin | IGND | 400 | mA | 36 | |||
| Current Sourced or Sunk by any I/O Pin or RSTb | IIO | -100 | 100 | mA | 36 | ||
| Operating Junction Temperature | TJ | -40 | 130 | °C | TA = -40 °C to 105 °C | 36 | |
| Digital Core Supply Current, Normal Mode full speed from flash | IDD | 12.9 | 15 | mA | FSYSCLK = 72 MHz (HFOSC1) | 19 | |
| Digital Core Supply Current, Normal Mode full speed from flash | IDD | 4.2 | 5 | mA | FSYSCLK = 24.5 MHz (HFOSC0) | 19 | |
| Digital Core Supply Current, Normal Mode full speed from flash | IDD | 625 | 1050 | μA | FSYSCLK = 1.53 MHz (HFOSC0) | 19 | |
| Digital Core Supply Current, Normal Mode full speed from flash | IDD | 155 | 575 | μA | FSYSCLK = 80 kHz | 19 | |
| Digital Core Supply Current, Idle Mode | IDD | 9.6 | 11.1 | mA | FSYSCLK = 72 MHz (HFOSC1) | 19 | |
| Digital Core Supply Current, Idle Mode | IDD | 3.14 | 3.8 | mA | FSYSCLK = 24.5 MHz (HFOSC0) | 19 | |
| Digital Core Supply Current, Idle Mode | IDD | 520 | 950 | μA | FSYSCLK = 1.53 MHz (HFOSC0) | 19 | |
| Digital Core Supply Current, Idle Mode | IDD | 135 | 550 | μA | FSYSCLK = 80 kHz | 19 | |
| Digital Core Supply Current, Suspend Mode | IDD | 125 | 545 | μA | LFO Running | 19 | |
| Digital Core Supply Current, Snooze Mode | IDD | 23 | 430 | μA | LFO Running | 19 | |
| Digital Core Supply Current, Stop Mode | IDD | 120 | 535 | μA | Internal LDO On, Supply monitor off | 19 | |
| Digital Core Supply Current, Shutdown Mode | IDD | 0.2 | 2.1 | μA | Internal LDO Off, Supply monitor off | 19 | |
| High-Frequency Oscillator 0 Supply Current | IHFOSC0 | 120 | 135 | μA | Operating at 24.5 MHz, TA = 25 °C | 19 | |
| High-Frequency Oscillator 1 Supply Current | IHFOSC1 | 1285 | 1340 | μA | Operating at 72 MHz, TA = 25 °C | 19 | |
| Low-Frequency Oscillator Supply Current | ILFOSC | 3.7 | 6 | μA | Operating at 80 kHz, TA = 25 °C | 19 | |
| ADC0 Supply Current, High Speed Mode | IADC | 1275 | 1700 | μA | 1 Msps, 12-bit conversions; Normal bias settings; VDD = 3.0 V | 20 | |
| ADC0 Supply Current, Low Power Mode | IADC | 390 | 530 | μA | 350 ksps, 12-bit conversions; Low power bias settings; VDD = 3.0 V | 20 | |
| Voltage Supply Monitor Supply Current | IVMON | 15 | 20 | μA | 20 | ||
| VDD Supply Monitor Threshold | VVDDM | 1.95 | 2.05 | 2.15 | V | 21 | |
| Power-On Reset (POR) Threshold, falling voltage on VDD | VPOR | 0.75 | 1.36 | V | Falling Voltage on VDD | 21 | |
| VDD Ramp Time | tRMP | 10 | μs | Time to VDD > 2.2 V | 21 | ||
| Reset Delay from POR | tPOR | 3 | 10 | 31 | ms | Relative to VDD > VPOR | 21 |
| RST Low Time to Generate Reset | tRSTL | 15 | μs | 21 | |||
| Missing Clock Detector Response Time (final rising edge to reset) | tMCD | 0.625 | 1.2 | ms | FSYSCLK > 1 MHz | 21 | |
| Missing Clock Detector Trigger Frequency | FMCD | 7.5 | 13.5 | kHz | 21 | ||
| Write Time (one byte) | tWRITE | 19 | 20 | 21 | μs | One Byte, FSYSCLK = 24.5 MHz | 21 |
| Erase Time (one page) | tERASE | 5.2 | 5.35 | 5.5 | ms | One Page, FSYSCLK = 24.5 MHz | 21 |
| VDD Voltage During Programming | VPROG | 2.2 | 3.6 | V | 21 | ||
| High Frequency Oscillator 0 Frequency (24.5 MHz) | fHFOSC0 | 24 | 24.5 | 25 | MHz | Full Temperature and Supply Range | 22 |
| High Frequency Oscillator 1 Frequency (72 MHz) | fHFOSC1 | 70.5 | 72 | 73.5 | MHz | Full Temperature and Supply Range | 22 |
| Low Frequency Oscillator Frequency (80 kHz) | fLFOSC | 75 | 80 | 85 | kHz | Full Temperature and Supply Range | 22 |
| External Input CMOS Clock Frequency (at EXTCLK pin) | fCMOS | 0 | 50 | MHz | 23 | ||
| External Input CMOS Clock High Time | tCMOSH | 9 | ns | 23 | |||
| External Input CMOS Clock Low Time | tCMOSL | 9 | ns | 23 | |||
| 1.8 V Internal LDO Output Voltage | VOUT_1.8V | 1.79 | 1.84 | 1.88 | V | 28 | |
| Internal Fast Settling Reference Output Voltage | VREFFS | 1.62 | 1.65 | 1.68 | V | Full Temperature and Supply Range | 27 |
| Internal Fast Settling Reference Turn-on Time | tREFFS | 1.5 | μs | 27 | |||
| On-chip Precision Reference Output Voltage (1.2 V output) | VREFP | 1.18 | 1.2 | 1.22 | V | 1.2 V Output | 27 |
| On-chip Precision Reference Output Voltage (2.4 V output) | VREFP | 2.36 | 2.4 | 2.44 | V | 2.4 V Output | 27 |
| DAC Output Current | IOUT | -2 | 2 | mA | 29 | ||
| DAC Offset Error | EOFF | -8 | 0 | 8 | LSB | VREF = 2.4 V | 29 |
| Comparator Input Offset Voltage | VOFF | -10 | 0 | 10 | mV | TA = 25 °C | 31 |
| Port I/O Weak Pull-Up Current | IPU | -30 | -20 | -10 | μA | VIN = 0 V, VDD = 3.6 | 32 |
| Thermal Resistance (Junction to Ambient), QFN24 Packages | θJA | 30 | °C/W | 35 | |||
| Thermal Resistance (Junction to Case), QFN24 Packages | θJC | 32.8 | °C/W | 35 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | PC | 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components. | 60 |
CAD (land: KiCad; 3D: generated from the datasheet)
- Symbol:
EFM8LB12F32ES0-C-QFN24R - Footprint:
Package_DFN_QFN:QFN-24-1EP_3x3mm_P0.4mm_EP1.75x1.6mm - 3D model: QFN-24-EP(3x3), generated on the KiCad land (body 3 x 3 mm, terminals on the pads, 0.85 mm tall, datasheet A, nominal). KiCad's stock model for this land is taller than the datasheet allows, so the model is generated from the datasheet drawing; the dimensions come from the datasheet drawing where it was read and are defaults otherwise (see provenance.model_3d_generated), not the manufacturer's CAD (STEP)
- 3D model files:
efm8lb12f32es0-c-qfn24r-etched.step/efm8lb12f32es0-c-qfn24r-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);efm8lb12f32es0-c-qfn24r.step/efm8lb12f32es0-c-qfn24r.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: SILICON LABS datasheet (77 pp, sha256
4bb882f3cda45564, retrieved 2026-11-13, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: land: KiCad official libraries (CC-BY-SA 4.0); 3D: generated from the datasheet's package dimensions (provenance.model_3d_generated).