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EFM8LB11F16E-C-QFN24
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SILICON LABS Pre-ordered MCUs, QFN-24-EP(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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EFM8LB11F16E-C-QFN24
SILICON LABS · Pre-ordered MCUs · QFN-24-EP(3x3)
EFM8LB11F16E-C-QFN24 from SILICON LABS, in a QFN-24-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model). Symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | P0.1 | bidirectional | Multifunction I/O with crossbar capability; additional digital functions P0MAT.1, INT0.1, INT1.1, CLU0B.8, CLU2A.9, CLU3B.9; analog functions ADC0.0, CMP0P.0, CMP0N.0 and AGND as listed in the datasheet. |
| 2 | P0.0 | bidirectional | Multifunction I/O with crossbar capability; additional digital functions P0MAT.0, INT0.0, INT1.0, CLU0A.8, CLU2A.8, CLU3B.8; analog function VREF. |
| 3 | GND | power_in | Ground pin. |
| 4 | VDD / VIO | power_in | Shared supply power input for VDD and VIO; device operation is specified from 2.2 V up to a 3.6 V supply. |
| 5 | RSTb / C2CK | input | Active-low reset input that is also the C2 debug clock (C2CK). |
| 6 | P3.0 / C2D | bidirectional | Multifunction I/O that is shared with the C2 debug data signal (C2D) on this package option. |
| 7 | P2.3 | bidirectional | Multifunction I/O with crossbar capability; additional digital functions P2MAT.3, CLU1B.15, CLU2B.15, CLU3A.15; analog function DAC3 as listed in the pin table. |
| 8 | P2.2 | bidirectional | Multifunction I/O with crossbar capability; additional digital functions P2MAT.2, CLU1A.15, CLU2B.14, CLU3A.14; analog function DAC2 as listed in the pin table. |
| 9 | P2.1 | bidirectional | Multifunction I/O with crossbar capability; additional digital functions P2MAT.1, CLU1B.14, CLU2A.15, CLU3B.15; analog function DAC1 as listed in the pin table. |
| 10 | P2.0 | bidirectional | Multifunction I/O with crossbar capability; additional digital functions P2MAT.0, CLU1A.14, CLU2A.14, CLU3B.14; analog function DAC0 as listed in the pin table. |
| 11 | P1.6 | bidirectional | Multifunction I/O with crossbar capability; additional digital functions P1MAT.6, CLU3OUT, CLU0A.15, CLU1B.12, CLU2A.12; analog functions ADC0.11, CMP1P.5, CMP1N.5. |
| 12 | P1.5 | bidirectional | Multifunction I/O with crossbar capability; additional digital functions P1MAT.5, CLU2OUT, CLU0B.14, CLU1A.13, CLU2B.13; analog functions ADC0.10, CMP1P.4, CMP1N.4. |
| 13 | P1.4 | bidirectional | Multifunction I/O with crossbar capability; additional digital functions P1MAT.4, I2C0_SCL, CLU0A.14, CLU1A.12, CLU2B.12; analog functions ADC0.9, CMP1P.3, CMP1N.3. |
| 14 | P1.3 | bidirectional | Multifunction I/O with crossbar capability; additional digital functions P1MAT.3, I2C0_SDA, CLU0B.13, CLU1B.11, CLU2B.11, CLU3A.13; analog functions CMP1P.2, CMP1N.2. |
| 15 | GND | power_in | Ground pin. |
| 16 | P1.2 | bidirectional | Multifunction I/O with crossbar capability; additional digital functions P1MAT.2, CLU0A.13, CLU1A.11, CLU2B.10, CLU3A.12; analog function ADC0.8. |
| 17 | P1.1 | bidirectional | Multifunction I/O with crossbar capability; additional digital functions P1MAT.1, CLU0B.12, CLU1B.10, CLU2A.11, CLU3B.13; analog function ADC0.7. |
| 18 | P1.0 | bidirectional | Multifunction I/O with crossbar capability; additional digital functions P1MAT.0, CLU0A.12, CLU1A.10, CLU2A.10, CLU3B.12; analog function ADC0.6. |
| 19 | P0.7 | bidirectional | Multifunction I/O with crossbar capability; additional digital functions P0MAT.7, INT0.7, INT1.7, CLU1OUT, CLU0B.11, CLU1B.9, CLU3A.11; analog functions ADC0.5, CMP0P.5, CMP0N.5, CMP1P.1, CMP1N.1. |
| 20 | P0.6 | bidirectional | Multifunction I/O with crossbar capability; additional digital functions P0MAT.6, CNVSTR, INT0.6, INT1.6, CLU0A.11, CLU1B.8, CLU3A.10; analog functions ADC0.4, CMP0P.4, CMP0N.4, CMP1P.0, CMP1N.0. |
| 21 | P0.5 | bidirectional | Multifunction I/O with crossbar capability; additional digital functions P0MAT.5, INT0.5, INT1.5, UART0_RX, CLU0B.10, CLU1A.9, CLU3B.11; analog functions ADC0.3, CMP0P.3, CMP0N.3. |
| 22 | P0.4 | bidirectional | Multifunction I/O with crossbar capability; additional digital functions P0MAT.4, INT0.4, INT1.4, UART0_TX, CLU0A.10, CLU1A.8, CLU3B.10; analog functions ADC0.2, CMP0P.2, CMP0N.2. |
| 23 | P0.3 | bidirectional | Multifunction I/O with crossbar capability; additional digital functions P0MAT.3, EXTCLK, INT0.3, INT1.3, CLU0B.9, CLU2B.9, CLU3A.9; analog function EXTOSC. |
| 24 | P0.2 | bidirectional | Multifunction I/O with crossbar capability; additional digital functions P0MAT.2, INT0.2, INT1.2, CLU0OUT, CLU0A.9, CLU2B.8, CLU3A.8; analog functions ADC0.1, CMP0P.1, CMP0N.1. |
| 25 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | SILICON LABS |
| Package | QFN-24-EP(3x3) |
| Category | Embedded Processors & Controllers |
| Pins | 25 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Operating Supply Voltage on VDD | VDD | 2.2 | 3.6 | V | 18 | ||
| Operating Supply Voltage on VIO | VIO | 2.2 | V | max printed as VDD | 18 | ||
| Operating Supply Voltage on VIO (second row) | VIO | 1.713 | V | max printed as VDD; no condition printed on this row | 18 | ||
| System Clock Frequency | fSYSCLK | 0 | 73.5 | MHz | 18 | ||
| Operating Ambient Temperature | TA | -40 | 105 | °C | 18 | ||
| Digital core supply current, Normal mode full speed | IDD | 12.9 | 15 | mA | Normal mode, code executing from flash, FSYSCLK = 72 MHz (HFOSC1) | 19 | |
| Digital core supply current, Normal mode | IDD | 4.2 | 5 | mA | Normal mode, code executing from flash, FSYSCLK = 24.5 MHz (HFOSC0) | 19 | |
| Digital core supply current, Normal mode | IDD | 625 | 1050 | μA | Normal mode, code executing from flash, FSYSCLK = 1.53 MHz (HFOSC0) | 19 | |
| Digital core supply current, Normal mode | IDD | 155 | 575 | μA | Normal mode, code executing from flash, FSYSCLK = 80 kHz | 19 | |
| Digital core supply current, Idle mode | IDD | 9.6 | 11.1 | mA | Idle mode, core halted, peripherals running, FSYSCLK = 72 MHz (HFOSC1) | 19 | |
| Digital core supply current, Idle mode | IDD | 3.14 | 3.8 | mA | Idle mode, core halted, peripherals running, FSYSCLK = 24.5 MHz (HFOSC0) | 19 | |
| Digital core supply current, Idle mode | IDD | 520 | 950 | μA | Idle mode, core halted, peripherals running, FSYSCLK = 1.53 MHz (HFOSC0) | 19 | |
| Digital core supply current, Idle mode | IDD | 135 | 550 | μA | Idle mode, core halted, peripherals running, FSYSCLK = 80 kHz | 19 | |
| Digital core supply current, Suspend mode | IDD | 125 | 545 | μA | Suspend mode, supply monitor off, LFO running | 19 | |
| Digital core supply current, Suspend mode | IDD | 120 | 535 | μA | Suspend mode, supply monitor off, LFO stopped | 19 | |
| Digital core supply current, Snooze mode | IDD | 23 | 430 | μA | Snooze mode, supply monitor off, LFO running | 19 | |
| Digital core supply current, Snooze mode | IDD | 19 | 425 | μA | Snooze mode, supply monitor off, LFO stopped | 19 | |
| Digital core supply current, Stop mode | IDD | 120 | 535 | μA | Stop mode, internal LDO on, supply monitor off | 19 | |
| Digital core supply current, Shutdown mode | IDD | 0.2 | 2.1 | μA | Shutdown mode, internal LDO off, supply monitor off | 19 | |
| High-Frequency Oscillator 0 supply current | IHFOSC0 | 120 | 135 | μA | Operating at 24.5 MHz, TA = 25 °C | 19 | |
| High-Frequency Oscillator 1 supply current | IHFOSC1 | 1285 | 1340 | μA | Operating at 72 MHz, TA = 25 °C | 19 | |
| Low-Frequency Oscillator supply current | ILFOSC | 3.7 | 6 | μA | Operating at 80 kHz, TA = 25 °C | 19 | |
| Throughput rate, High Speed Mode, 14-bit | fS | 900 | ksps | 14 Bit Mode, High Speed Mode | 24 | ||
| Throughput rate, High Speed Mode, 12-bit | fS | 1 | Msps | 12 Bit Mode, High Speed Mode | 24 | ||
| Throughput rate, High Speed Mode, 10-bit | fS | 1.125 | Msps | 10 Bit Mode, High Speed Mode | 24 | ||
| Power-On Time | tPWR | 1.2 | μs | 24 | |||
| Integral Nonlinearity, 14-bit | INL | -3.54 | 8.54 | LSB | 14 Bit Mode | 25 | |
| Integral Nonlinearity, 12-bit | INL | -1.9 | 1.9 | LSB | 12 Bit Mode | 25 | |
| Differential Nonlinearity, 14-bit (guaranteed monotonic) | DNL | -14 | 2.54 | LSB | 14 Bit Mode | 25 | |
| Differential Nonlinearity, 12-bit (guaranteed monotonic) | DNL | -0.9 | 0.9 | LSB | 12 Bit Mode | 25 | |
| Offset Error, 14-bit | EOFF | -84 | -2.5 | 8 | LSB | 14 Bit Mode | 25 |
| Offset Error, 12-bit | EOFF | -2 | 0 | 2 | LSB | 12 Bit Mode | 25 |
| Offset Error, 10-bit | EOFF | -1 | 0 | 1 | LSB | 10 Bit Mode | 25 |
| Slope Error, 14-bit | EM | -154 | 154 | LSB | 14 Bit Mode | 25 | |
| Slope Error, 12-bit | EM | -2.6 | 2.6 | LSB | 12 Bit Mode | 25 | |
| Slope Error, 10-bit | EM | -1.1 | 1.1 | LSB | 10 Bit Mode | 25 | |
| Signal-to-Noise Ratio, 14-bit | SNR | 664 | 72 | dB | 10 kHz sine wave input, 1 dB below full scale, max throughput, 14 Bit Mode | 25 | |
| Signal-to-Noise Ratio, 12-bit | SNR | 64 | 68 | dB | 10 kHz sine wave input, 1 dB below full scale, max throughput, 12 Bit Mode | 25 | |
| Internal Fast Settling Reference Output Voltage | VREFFS | 1.62 | 1.65 | 1.68 | V | Full temperature and supply range | 27 |
| On-chip precision reference valid supply range, 1.2 V output | VDD | 2.2 | 3.6 | V | 1.2 V Output | 27 | |
| On-chip precision reference valid supply range, 2.4 V output | VDD | 2.7 | 3.6 | V | 2.4 V Output | 27 | |
| On-chip precision reference output voltage, 1.2 V output | VREFP | 1.18 | 1.2 | 1.22 | V | 1.2 V Output | 27 |
| On-chip precision reference output voltage, 2.4 V output | VREFP | 2.36 | 2.4 | 2.44 | V | 2.4 V Output | 27 |
| Load capacitor for on-chip precision reference | CVREFP | 0.1 | µF | Load = 0 to 200 µA to GND | 27 | ||
| Temperature sensor error (typical slope, factory-calibrated offset) | ETOT | -2.6 | 1.8 | °C | T = 0 °C to 70 °C | 28 | |
| Temperature sensor error (typical slope, factory-calibrated offset) | ETOT | -2.9 | 2.7 | °C | T = -20 °C to 85 °C | 28 | |
| Temperature sensor error (typical slope, factory-calibrated offset) | ETOT | -3.2 | 4.2 | °C | T = -40 °C to 105 °C | 28 | |
| 1.8 V internal LDO output voltage | VOUT_1.8V | 1.79 | 1.84 | 1.88 | V | 28 | |
| Ambient temperature under bias | TBIAS | -55 | 125 | °C | 36 | ||
| Storage temperature | TSTG | -65 | 150 | °C | 36 | ||
| Voltage on VDD | VDD | -0.3 | 4.2 | V | min printed as GND-0.3 | 36 | |
| Voltage on VIO | VIO | -0.3 | V | min printed as GND-0.3; max printed as VDD+0.3 | 36 | ||
| Voltage on I/O pins or RSTb (VIO > 3.3 V) | VIN | -0.3 | 5.8 | V | VIO > 3.3 V; min printed as GND-0.3; excludes P2.0-P2.3 (QFN24) | 36 | |
| Voltage on I/O pins or RSTb (VIO < 3.3 V) | VIN | -0.3 | V | VIO < 3.3 V; min printed as GND-0.3; max printed as VIO+2.5 V | 36 | ||
| Voltage on P2.0-P2.3 (QFN24) | VIN | -0.3 | V | min printed as GND-0.3; max printed as VDD+0.3 | 36 | ||
| Total current sunk into supply pin | IVDD | 400 | mA | 36 | |||
| Total current sourced out of ground pin | IGND | 400 | mA | 36 | |||
| Current sourced or sunk by any I/O pin or RSTb | IIO | -100 | 100 | mA | 36 | ||
| Operating junction temperature | TJ | -40 | 130 | °C | TA = -40 °C to 105 °C | 36 | |
| Thermal resistance, junction to ambient, QFN24 packages | θJA | 30 | °C/W | 35 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | PC | 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components. | 60 |
CAD (KiCad official)
- Symbol:
EFM8LB11F16E-C-QFN24 - Footprint:
Package_DFN_QFN:QFN-24-1EP_3x3mm_P0.4mm_EP1.75x1.6mm - 3D model: QFN-24-EP(3x3), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.85 mm tall, datasheet A, nominal). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions come from the datasheet drawing where it was read and are defaults otherwise (see provenance.model_3d_generated), not the manufacturer's CAD (STEP)
- 3D model files:
efm8lb11f16e-c-qfn24-etched.step/efm8lb11f16e-c-qfn24-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);efm8lb11f16e-c-qfn24.step/efm8lb11f16e-c-qfn24.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: SILICON LABS datasheet (77 pp, sha256
4bb882f3cda45564, retrieved 2026-11-12, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# EFM8LB11F16E-C-QFN24
**SILICON LABS** · Pre-ordered MCUs · QFN-24-EP(3x3)
EFM8LB11F16E-C-QFN24 from SILICON LABS, in a QFN-24-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model). Symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | P0.1 | bidirectional | Multifunction I/O with crossbar capability; additional digital functions P0MAT.1, INT0.1, INT1.1, CLU0B.8, CLU2A.9, CLU3B.9; analog functions ADC0.0, CMP0P.0, CMP0N.0 and AGND as listed in the datasheet. |
| 2 | P0.0 | bidirectional | Multifunction I/O with crossbar capability; additional digital functions P0MAT.0, INT0.0, INT1.0, CLU0A.8, CLU2A.8, CLU3B.8; analog function VREF. |
| 3 | GND | power_in | Ground pin. |
| 4 | VDD / VIO | power_in | Shared supply power input for VDD and VIO; device operation is specified from 2.2 V up to a 3.6 V supply. |
| 5 | RSTb / C2CK | input | Active-low reset input that is also the C2 debug clock (C2CK). |
| 6 | P3.0 / C2D | bidirectional | Multifunction I/O that is shared with the C2 debug data signal (C2D) on this package option. |
| 7 | P2.3 | bidirectional | Multifunction I/O with crossbar capability; additional digital functions P2MAT.3, CLU1B.15, CLU2B.15, CLU3A.15; analog function DAC3 as listed in the pin table. |
| 8 | P2.2 | bidirectional | Multifunction I/O with crossbar capability; additional digital functions P2MAT.2, CLU1A.15, CLU2B.14, CLU3A.14; analog function DAC2 as listed in the pin table. |
| 9 | P2.1 | bidirectional | Multifunction I/O with crossbar capability; additional digital functions P2MAT.1, CLU1B.14, CLU2A.15, CLU3B.15; analog function DAC1 as listed in the pin table. |
| 10 | P2.0 | bidirectional | Multifunction I/O with crossbar capability; additional digital functions P2MAT.0, CLU1A.14, CLU2A.14, CLU3B.14; analog function DAC0 as listed in the pin table. |
| 11 | P1.6 | bidirectional | Multifunction I/O with crossbar capability; additional digital functions P1MAT.6, CLU3OUT, CLU0A.15, CLU1B.12, CLU2A.12; analog functions ADC0.11, CMP1P.5, CMP1N.5. |
| 12 | P1.5 | bidirectional | Multifunction I/O with crossbar capability; additional digital functions P1MAT.5, CLU2OUT, CLU0B.14, CLU1A.13, CLU2B.13; analog functions ADC0.10, CMP1P.4, CMP1N.4. |
| 13 | P1.4 | bidirectional | Multifunction I/O with crossbar capability; additional digital functions P1MAT.4, I2C0_SCL, CLU0A.14, CLU1A.12, CLU2B.12; analog functions ADC0.9, CMP1P.3, CMP1N.3. |
| 14 | P1.3 | bidirectional | Multifunction I/O with crossbar capability; additional digital functions P1MAT.3, I2C0_SDA, CLU0B.13, CLU1B.11, CLU2B.11, CLU3A.13; analog functions CMP1P.2, CMP1N.2. |
| 15 | GND | power_in | Ground pin. |
| 16 | P1.2 | bidirectional | Multifunction I/O with crossbar capability; additional digital functions P1MAT.2, CLU0A.13, CLU1A.11, CLU2B.10, CLU3A.12; analog function ADC0.8. |
| 17 | P1.1 | bidirectional | Multifunction I/O with crossbar capability; additional digital functions P1MAT.1, CLU0B.12, CLU1B.10, CLU2A.11, CLU3B.13; analog function ADC0.7. |
| 18 | P1.0 | bidirectional | Multifunction I/O with crossbar capability; additional digital functions P1MAT.0, CLU0A.12, CLU1A.10, CLU2A.10, CLU3B.12; analog function ADC0.6. |
| 19 | P0.7 | bidirectional | Multifunction I/O with crossbar capability; additional digital functions P0MAT.7, INT0.7, INT1.7, CLU1OUT, CLU0B.11, CLU1B.9, CLU3A.11; analog functions ADC0.5, CMP0P.5, CMP0N.5, CMP1P.1, CMP1N.1. |
| 20 | P0.6 | bidirectional | Multifunction I/O with crossbar capability; additional digital functions P0MAT.6, CNVSTR, INT0.6, INT1.6, CLU0A.11, CLU1B.8, CLU3A.10; analog functions ADC0.4, CMP0P.4, CMP0N.4, CMP1P.0, CMP1N.0. |
| 21 | P0.5 | bidirectional | Multifunction I/O with crossbar capability; additional digital functions P0MAT.5, INT0.5, INT1.5, UART0_RX, CLU0B.10, CLU1A.9, CLU3B.11; analog functions ADC0.3, CMP0P.3, CMP0N.3. |
| 22 | P0.4 | bidirectional | Multifunction I/O with crossbar capability; additional digital functions P0MAT.4, INT0.4, INT1.4, UART0_TX, CLU0A.10, CLU1A.8, CLU3B.10; analog functions ADC0.2, CMP0P.2, CMP0N.2. |
| 23 | P0.3 | bidirectional | Multifunction I/O with crossbar capability; additional digital functions P0MAT.3, EXTCLK, INT0.3, INT1.3, CLU0B.9, CLU2B.9, CLU3A.9; analog function EXTOSC. |
| 24 | P0.2 | bidirectional | Multifunction I/O with crossbar capability; additional digital functions P0MAT.2, INT0.2, INT1.2, CLU0OUT, CLU0A.9, CLU2B.8, CLU3A.8; analog functions ADC0.1, CMP0P.1, CMP0N.1. |
| 25 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | SILICON LABS |
| Package | QFN-24-EP(3x3) |
| Category | Embedded Processors & Controllers |
| Pins | 25 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Operating Supply Voltage on VDD | VDD | 2.2 | | 3.6 | V | | 18 |
| Operating Supply Voltage on VIO | VIO | 2.2 | | | V | max printed as VDD | 18 |
| Operating Supply Voltage on VIO (second row) | VIO | 1.713 | | | V | max printed as VDD; no condition printed on this row | 18 |
| System Clock Frequency | fSYSCLK | 0 | | 73.5 | MHz | | 18 |
| Operating Ambient Temperature | TA | -40 | | 105 | °C | | 18 |
| Digital core supply current, Normal mode full speed | IDD | | 12.9 | 15 | mA | Normal mode, code executing from flash, FSYSCLK = 72 MHz (HFOSC1) | 19 |
| Digital core supply current, Normal mode | IDD | | 4.2 | 5 | mA | Normal mode, code executing from flash, FSYSCLK = 24.5 MHz (HFOSC0) | 19 |
| Digital core supply current, Normal mode | IDD | | 625 | 1050 | μA | Normal mode, code executing from flash, FSYSCLK = 1.53 MHz (HFOSC0) | 19 |
| Digital core supply current, Normal mode | IDD | | 155 | 575 | μA | Normal mode, code executing from flash, FSYSCLK = 80 kHz | 19 |
| Digital core supply current, Idle mode | IDD | | 9.6 | 11.1 | mA | Idle mode, core halted, peripherals running, FSYSCLK = 72 MHz (HFOSC1) | 19 |
| Digital core supply current, Idle mode | IDD | | 3.14 | 3.8 | mA | Idle mode, core halted, peripherals running, FSYSCLK = 24.5 MHz (HFOSC0) | 19 |
| Digital core supply current, Idle mode | IDD | | 520 | 950 | μA | Idle mode, core halted, peripherals running, FSYSCLK = 1.53 MHz (HFOSC0) | 19 |
| Digital core supply current, Idle mode | IDD | | 135 | 550 | μA | Idle mode, core halted, peripherals running, FSYSCLK = 80 kHz | 19 |
| Digital core supply current, Suspend mode | IDD | | 125 | 545 | μA | Suspend mode, supply monitor off, LFO running | 19 |
| Digital core supply current, Suspend mode | IDD | | 120 | 535 | μA | Suspend mode, supply monitor off, LFO stopped | 19 |
| Digital core supply current, Snooze mode | IDD | | 23 | 430 | μA | Snooze mode, supply monitor off, LFO running | 19 |
| Digital core supply current, Snooze mode | IDD | | 19 | 425 | μA | Snooze mode, supply monitor off, LFO stopped | 19 |
| Digital core supply current, Stop mode | IDD | | 120 | 535 | μA | Stop mode, internal LDO on, supply monitor off | 19 |
| Digital core supply current, Shutdown mode | IDD | | 0.2 | 2.1 | μA | Shutdown mode, internal LDO off, supply monitor off | 19 |
| High-Frequency Oscillator 0 supply current | IHFOSC0 | | 120 | 135 | μA | Operating at 24.5 MHz, TA = 25 °C | 19 |
| High-Frequency Oscillator 1 supply current | IHFOSC1 | | 1285 | 1340 | μA | Operating at 72 MHz, TA = 25 °C | 19 |
| Low-Frequency Oscillator supply current | ILFOSC | | 3.7 | 6 | μA | Operating at 80 kHz, TA = 25 °C | 19 |
| Throughput rate, High Speed Mode, 14-bit | fS | | | 900 | ksps | 14 Bit Mode, High Speed Mode | 24 |
| Throughput rate, High Speed Mode, 12-bit | fS | | | 1 | Msps | 12 Bit Mode, High Speed Mode | 24 |
| Throughput rate, High Speed Mode, 10-bit | fS | | | 1.125 | Msps | 10 Bit Mode, High Speed Mode | 24 |
| Power-On Time | tPWR | 1.2 | | | μs | | 24 |
| Integral Nonlinearity, 14-bit | INL | -3.54 | | 8.54 | LSB | 14 Bit Mode | 25 |
| Integral Nonlinearity, 12-bit | INL | -1.9 | | 1.9 | LSB | 12 Bit Mode | 25 |
| Differential Nonlinearity, 14-bit (guaranteed monotonic) | DNL | -14 | | 2.54 | LSB | 14 Bit Mode | 25 |
| Differential Nonlinearity, 12-bit (guaranteed monotonic) | DNL | -0.9 | | 0.9 | LSB | 12 Bit Mode | 25 |
| Offset Error, 14-bit | EOFF | -84 | -2.5 | 8 | LSB | 14 Bit Mode | 25 |
| Offset Error, 12-bit | EOFF | -2 | 0 | 2 | LSB | 12 Bit Mode | 25 |
| Offset Error, 10-bit | EOFF | -1 | 0 | 1 | LSB | 10 Bit Mode | 25 |
| Slope Error, 14-bit | EM | -154 | | 154 | LSB | 14 Bit Mode | 25 |
| Slope Error, 12-bit | EM | -2.6 | | 2.6 | LSB | 12 Bit Mode | 25 |
| Slope Error, 10-bit | EM | -1.1 | | 1.1 | LSB | 10 Bit Mode | 25 |
| Signal-to-Noise Ratio, 14-bit | SNR | 664 | 72 | | dB | 10 kHz sine wave input, 1 dB below full scale, max throughput, 14 Bit Mode | 25 |
| Signal-to-Noise Ratio, 12-bit | SNR | 64 | 68 | | dB | 10 kHz sine wave input, 1 dB below full scale, max throughput, 12 Bit Mode | 25 |
| Internal Fast Settling Reference Output Voltage | VREFFS | 1.62 | 1.65 | 1.68 | V | Full temperature and supply range | 27 |
| On-chip precision reference valid supply range, 1.2 V output | VDD | 2.2 | | 3.6 | V | 1.2 V Output | 27 |
| On-chip precision reference valid supply range, 2.4 V output | VDD | 2.7 | | 3.6 | V | 2.4 V Output | 27 |
| On-chip precision reference output voltage, 1.2 V output | VREFP | 1.18 | 1.2 | 1.22 | V | 1.2 V Output | 27 |
| On-chip precision reference output voltage, 2.4 V output | VREFP | 2.36 | 2.4 | 2.44 | V | 2.4 V Output | 27 |
| Load capacitor for on-chip precision reference | CVREFP | 0.1 | | | µF | Load = 0 to 200 µA to GND | 27 |
| Temperature sensor error (typical slope, factory-calibrated offset) | ETOT | -2.6 | | 1.8 | °C | T = 0 °C to 70 °C | 28 |
| Temperature sensor error (typical slope, factory-calibrated offset) | ETOT | -2.9 | | 2.7 | °C | T = -20 °C to 85 °C | 28 |
| Temperature sensor error (typical slope, factory-calibrated offset) | ETOT | -3.2 | | 4.2 | °C | T = -40 °C to 105 °C | 28 |
| 1.8 V internal LDO output voltage | VOUT_1.8V | 1.79 | 1.84 | 1.88 | V | | 28 |
| Ambient temperature under bias | TBIAS | -55 | | 125 | °C | | 36 |
| Storage temperature | TSTG | -65 | | 150 | °C | | 36 |
| Voltage on VDD | VDD | -0.3 | | 4.2 | V | min printed as GND-0.3 | 36 |
| Voltage on VIO | VIO | -0.3 | | | V | min printed as GND-0.3; max printed as VDD+0.3 | 36 |
| Voltage on I/O pins or RSTb (VIO > 3.3 V) | VIN | -0.3 | | 5.8 | V | VIO > 3.3 V; min printed as GND-0.3; excludes P2.0-P2.3 (QFN24) | 36 |
| Voltage on I/O pins or RSTb (VIO < 3.3 V) | VIN | -0.3 | | | V | VIO < 3.3 V; min printed as GND-0.3; max printed as VIO+2.5 V | 36 |
| Voltage on P2.0-P2.3 (QFN24) | VIN | -0.3 | | | V | min printed as GND-0.3; max printed as VDD+0.3 | 36 |
| Total current sunk into supply pin | IVDD | | | 400 | mA | | 36 |
| Total current sourced out of ground pin | IGND | | | 400 | mA | | 36 |
| Current sourced or sunk by any I/O pin or RSTb | IIO | -100 | | 100 | mA | | 36 |
| Operating junction temperature | TJ | -40 | | 130 | °C | TA = -40 °C to 105 °C | 36 |
| Thermal resistance, junction to ambient, QFN24 packages | θJA | | 30 | | °C/W | | 35 |
## Materials and finish
As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | PC | | 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components. | 60 |
## CAD (KiCad official)
- Symbol: `EFM8LB11F16E-C-QFN24`
- Footprint: `Package_DFN_QFN:QFN-24-1EP_3x3mm_P0.4mm_EP1.75x1.6mm`
- 3D model: QFN-24-EP(3x3), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.85 mm tall, datasheet A, nominal). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions come from the datasheet drawing where it was read and are defaults otherwise (see provenance.model_3d_generated), not the manufacturer's CAD (STEP)
- 3D model files: `efm8lb11f16e-c-qfn24-etched.step` / `efm8lb11f16e-c-qfn24-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `efm8lb11f16e-c-qfn24.step` / `efm8lb11f16e-c-qfn24.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [SILICON LABS datasheet](docs/efm8lb11f16e-c-qfn24-datasheet.pdf) (77 pp, sha256 `4bb882f3cda45564`, retrieved 2026-11-12, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/efm8lb11f16e-c-qfn24-datasheet.pdf)