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EFM32ZG222F32-B-QFP48R

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SKYWORKS/SILICON LABS Microcontrollers (MCU/MPU/SOC), TQFP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentembedded processors & controllersefm32zg222f32-b-qfp48rfactory-2.0.0extractor-text

Verified EFM32ZG222F32-B-QFP48R

by Ray · last 2 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

2 Nov 2026RayPublished by the parts factory: tier lcsc, 48 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: EFM32ZG222F32-B-QFP48R · TQFP-48(7x7) · 48 pins
  • ✓copper: 48 copper pads, none touching another net
  • ✓datasheet: all 48 pin names found in the 104-page datasheet
  • ✓distributor: lcsc C3236149, digikey EFM32ZG222F32-B-QFP48R-ND, mouser 634-EFM32ZG22232B48R
  • ✓family: TQFP-48_7x7mm_P0.5mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-9fwsx7g7/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 48 pins = 48 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 48 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ efm32zg222f32-b-qfp48r.kicad_sym✓ efm32zg222f32-b-qfp48r.kicad_mod✓ efm32zg222f32-b-qfp48r.step
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Ray Publish 0.1.0 2906427

EFM32ZG222F32-B-QFP48R

SKYWORKS/SILICON LABS · Microcontrollers (MCU/MPU/SOC) · TQFP-48(7x7)

EFM32ZG222F32-B-QFP48R from SKYWORKS/SILICON LABS, in a TQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PA0 bidirectional GPIO PA0 with alternate functions TIM0_CC0, LEU0_RX (location 4), I2C0_SDA (location 0), PRS_CH0 (location 0) and GPIO_EM4WU0 wake-up from EM4.
2 PA1 bidirectional GPIO PA1 with alternate functions TIM0_CC1, I2C0_SCL (location 0), CMU_CLK1 (location 0) and PRS_CH1 (location 0).
3 PA2 bidirectional GPIO PA2 with alternate functions TIM0_CC2 (locations 0/1) and CMU_CLK0 (location 0).
4 IOVDD_0 power_in Digital IO power supply 0.
5 VSS power_in Ground.
6 PC0 bidirectional GPIO PC0 with analog input ACMP0_CH0 and alternate functions TIM0_CC1 (location 4), PCNT0_S0IN (location 2), US1_TX (location 0), I2C0_SDA (location 4) and PRS_CH2 (location 0).
7 PC1 bidirectional GPIO PC1 with analog input ACMP0_CH1 and alternate functions TIM0_CC2 (location 4), PCNT0_S1IN (location 2), US1_RX (location 0), I2C0_SCL (location 4) and PRS_CH3 (location 0).
8 PC2 bidirectional GPIO PC2 with analog input ACMP0_CH2.
9 PC3 bidirectional GPIO PC3 with analog input ACMP0_CH3.
10 PC4 bidirectional GPIO PC4 with analog input ACMP0_CH4.
11 PB7 bidirectional GPIO PB7 used as LFXTAL_P low frequency crystal positive pin, with alternate functions TIM1_CC0 (location 3) and US1_CLK (location 0).
12 PB8 bidirectional GPIO PB8 used as LFXTAL_N low frequency crystal negative pin (also an optional external clock input), with alternate functions TIM1_CC1 (location 3) and US1_CS (location 0).
13 PA8 bidirectional GPIO PA8 with no alternate functionality listed in the pinout table.
14 PA9 bidirectional GPIO PA9 with no alternate functionality listed in the pinout table.
15 PA10 bidirectional GPIO PA10 with no alternate functionality listed in the pinout table.
16 RESETn input Reset input, active low; to apply an external reset, drive this pin low only during reset and let the internal pull-up release reset.
17 PB11 bidirectional GPIO PB11 with IDAC0_OUT current DAC output and alternate function TIM1_CC2 (location 3).
18 VSS power_in Ground.
19 AVDD_1 power_in Analog power supply 1.
20 PB13 bidirectional GPIO PB13 used as HFXTAL_P high frequency crystal positive pin, with alternate function LEU0_TX (location 1).
21 PB14 bidirectional GPIO PB14 used as HFXTAL_N high frequency crystal negative pin (also an optional external clock input), with alternate function LEU0_RX (location 1).
22 IOVDD_3 power_in Digital IO power supply 3.
23 AVDD_0 power_in Analog power supply 0.
24 PD4 bidirectional GPIO PD4 with analog input ADC0_CH4 and alternate function LEU0_TX (location 0).
25 PD5 bidirectional GPIO PD5 with analog input ADC0_CH5 and alternate function LEU0_RX (location 0).
26 PD6 bidirectional GPIO PD6 with analog input ADC0_CH6 and alternate functions TIM1_CC0 (location 4), PCNT0_S0IN (location 3), US1_RX (locations 2/3), I2C0_SDA (location 1) and ACMP0_O (location 2).
27 PD7 bidirectional GPIO PD7 with analog input ADC0_CH7 and alternate functions TIM1_CC1 (location 4), PCNT0_S1IN (location 3), US1_TX (locations 2/3), I2C0_SCL (location 1) and CMU_CLK0 (location 2).
28 VDD_DREG power_in Power supply for on-chip voltage regulator.
29 DECOUPLE passive Decouple output for on-chip voltage regulator; an external capacitance of size CDECOUPLE is required at this pin.
30 PC8 bidirectional GPIO PC8 with no alternate functionality listed in the pinout table.
31 PC9 bidirectional GPIO PC9 with alternate function GPIO_EM4WU2 that can wake the system up from EM4.
32 PC10 bidirectional GPIO PC10 with no alternate functionality listed in the pinout table.
33 PC11 bidirectional GPIO PC11 with no alternate functionality listed in the pinout table.
34 PC13 bidirectional GPIO PC13 with alternate functions TIM1_CC0 (location 0), TIM1_CC2 (location 4) and PCNT0_S0IN (location 0).
35 PC14 bidirectional GPIO PC14 with alternate functions TIM1_CC1 (location 0), PCNT0_S1IN (location 0), US1_CS (location 3) and PRS_CH0 (location 2).
36 PC15 bidirectional GPIO PC15 with alternate functions TIM1_CC2 (location 0), US1_CLK (location 3) and PRS_CH1 (location 2).
37 PF0 bidirectional GPIO PF0 with alternate functions TIM0_CC0 (location 5), US1_CLK (location 2), LEU0_TX (location 3), I2C0_SDA (location 5), DBG_SWCLK (location 0, built-in pull down) and BOOT_TX.
38 PF1 bidirectional GPIO PF1 with alternate functions TIM0_CC1 (location 5), US1_CS (location 2), LEU0_RX (location 3), I2C0_SCL (location 5), DBG_SWDIO (location 0, built-in pull up), GPIO_EM4WU3 and BOOT_RX.
39 PF2 bidirectional GPIO PF2 with alternate functions TIM0_CC2 (location 5), LEU0_TX (location 4) and GPIO_EM4WU4 wake-up from EM4.
40 PF3 bidirectional GPIO PF3 with alternate function PRS_CH0 (location 1).
41 PF4 bidirectional GPIO PF4 with alternate function PRS_CH1 (location 1).
42 PF5 bidirectional GPIO PF5 with alternate function PRS_CH2 (location 1).
43 IOVDD_5 power_in Digital IO power supply 5.
44 VSS power_in Ground.
45 PE10 bidirectional GPIO PE10 with alternate functions TIM1_CC0 (location 1) and PRS_CH2 (location 2).
46 PE11 bidirectional GPIO PE11 with alternate functions TIM1_CC1 (location 1) and PRS_CH3 (location 2).
47 PE12 bidirectional GPIO PE12 with alternate functions TIM1_CC2 (location 1), I2C0_SDA (location 6) and CMU_CLK1 (location 2).
48 PE13 bidirectional GPIO PE13 with alternate functions I2C0_SCL (location 6), ACMP0_O (location 0) and GPIO_EM4WU5 wake-up from EM4.

Key specifications

Parameter Value
Manufacturer SKYWORKS/SILICON LABS
Package TQFP-48(7x7)
Category Embedded Processors & Controllers
Pins 48

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Storage temperature range TSTG -40 150 °C 17
Maximum soldering temperature TS 260 °C Latest IPC/JEDEC J-STD-020 Standard 17
External main supply voltage VDDMAX 0 3.8 V 17
Voltage on any I/O pin VIOPIN -0.3 V Maximum printed as VDD+0.3 17
Current per I/O pin (sink) IIOMAX_SINK 100 mA 17
Current per I/O pin (source) IIOMAX_SOURCE -100 mA 17
Ambient temperature range TAMB -40 85 °C 17
Operating supply voltage VDDOP 1.98 3.8 V 17
Internal APB clock frequency fAPB 24 MHz 17
Internal AHB clock frequency fAHB 24 MHz 17
BOD threshold on falling external supply voltage VBODextthr- 1.74 1.96 V 27
Flash erase cycles before failure ECFLASH 20000 cycles 28
Flash word write cycles between erase WWCFLASH 2 cycles Maximum of two writes to the same word between erases (Note 1) 28
Flash data retention RETFLASH 10000 h TAMB<150 °C 28
Flash data retention RETFLASH 10 years TAMB<85 °C 28
Flash data retention RETFLASH 20 years TAMB<70 °C 28
Word (32-bit) programming time tW_PROG 20 µs 28
Page erase time tPERASE 20 20.4 20.8 ms 28
Device erase time tDERASE 40 40.8 41.6 ms 28
Erase current IERASE 7 mA Measured at 25 °C 28
Write current IWRITE 7 mA Measured at 25 °C 28
Supply voltage during flash erase and write VFLASH 1.98 3.8 V 28
Input leakage current IIOLEAK -100 0.1 100 nA High impedance IO connected to GROUND or VDD 30
Pulse width of pulses to be removed by the glitch suppression filter tIO-GLITCH 10 50 ns 30
Supported crystal equivalent series resistance (ESR) ESRLFXO 30 120 kΩ LFXO 37
Supported crystal external load range CLFXOL 5 25 pF LFXO 37
Supported nominal crystal frequency fHFXO 4 24 MHz HFXO 37
Supported crystal equivalent series resistance (ESR) ESRHFXO 30 100 Ω Crystal frequency 24 MHz 37
Supported crystal equivalent series resistance (ESR) ESRHFXO 400 1500 Ω Crystal frequency 4 MHz 37
Transconductance of the HFXO input transistor at crystal startup gmHFXO 20 mS HFXOBOOST in CMU_CTRL equals 0b11 37
Oscillation frequency fLFRCO 31.29 32.768 34.28 kHz VDD=3.0 V, TAMB=25°C 38
Oscillation frequency, 21 MHz band fHFRCO 20.37 21 21.63 MHz VDD=3.0 V, TAMB=25°C; 21 MHz frequency band 39
Oscillation frequency, 14 MHz band fHFRCO 13.58 14 14.42 MHz VDD=3.0 V, TAMB=25°C; 14 MHz frequency band 39
Oscillation frequency, 11 MHz band fHFRCO 10.67 11 11.33 MHz VDD=3.0 V, TAMB=25°C; 11 MHz frequency band 39
Oscillation frequency, 7 MHz band fHFRCO 6.4 6.6 6.8 MHz VDD=3.0 V, TAMB=25°C; 7 MHz frequency band 39
Oscillation frequency, 1 MHz band fHFRCO 1.15 1.2 1.25 MHz VDD=3.0 V, TAMB=25°C; 1 MHz frequency band 39
Current consumption, 21 MHz IHFRCO 93 175 µA fHFRCO = 21 MHz 39
Current consumption, 14 MHz IHFRCO 77 140 µA fHFRCO = 14 MHz 39
Current consumption, 11 MHz IHFRCO 72 125 µA fHFRCO = 11 MHz 39
Current consumption, 6.6 MHz IHFRCO 63 105 µA fHFRCO = 6.6 MHz 39
Current consumption, 1.2 MHz IHFRCO 22 40 µA fHFRCO = 1.2 MHz 39
Average active current, ADC IADC 351 500 µA 1 MSamples/s, 12-bit, external reference 43
Current consumption of internal voltage reference IADCREF 65 127 µA Internal voltage reference 43
Input ON resistance RADCIN 300 800 Ω 43
ADC clock frequency fADCCLK 13 MHz 43
Conversion time 12-bit tADCCONV 13 ADCCLK cycles 12-bit 43
Acquisition time tADCACQ 1 256 ADCCLK cycles Programmable 44
Required acquisition time for VDD/3 reference tADCACQVDD3 2 µs 44
Offset voltage VADCOFFSET -4 0.3 4 mV After calibration, single-ended 46
Differential non-linearity (DNL) DNLADC -1 0.7 4 LSB VDD=3.0 V, external 2.5V reference 46
Current consumption, EM0 24 MHz HFXO 25°C IEM0 115 132 µA/MHz 24 MHz HFXO, all peripheral clocks disabled, VDD=3.0 V, TAMB=25°C 18
Current consumption, EM4 85°C IEM4 0.29 0.7 µA VDD=3.0 V, TAMB=85°C 19
Current consumption, EM3 85°C IEM3 1.3 2 µA EM3 current (ULFRCO enabled, LFRCO/LFXO disabled), VDD=3.0 V, TAMB=85°C 19
SCL clock frequency, Standard-mode fSCL 0 100 kHz I2C Standard-mode (Sm) 63
SDA hold time, Standard-mode tHD,DAT 8 3450 ns I2C Standard-mode (Sm); maximum applies only when SCL low time is not stretched 63
SDA hold time, Fast-mode tHD,DAT 8 900 ns I2C Fast-mode (Fm); maximum applies only when SCL low time is not stretched 63

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts gold The TQFP48 package is 7 by 7 mm in size and has a 0.5 mm pin pitch. The TQFP48 package uses Nickel-Palladium-Gold preplated leadframe. 95

CAD (KiCad official)

  • Symbol: EFM32ZG222F32-B-QFP48R
  • Footprint: Package_QFP:TQFP-48_7x7mm_P0.5mm
  • 3D model: TQFP-48(7x7) (KiCad packages3D, STEP)
  • 3D model files: efm32zg222f32-b-qfp48r-etched.step / efm32zg222f32-b-qfp48r-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); efm32zg222f32-b-qfp48r.step / efm32zg222f32-b-qfp48r.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: SKYWORKS/SILICON LABS datasheet (104 pp, sha256 6d1c4d21c94b4036, retrieved 2026-11-02, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF