component

EFM32TG222F32-D-QFP48R

Public Made by Adom

by adom

SILICON LABS Microcontroller Units (MCUs/MPUs/SOCs), TQFP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentsingle chip microcomputer-microcontrollerefm32tg222f32-d-qfp48rfactory-2.0.0extractor-text

Verified EFM32TG222F32-D-QFP48R

by Ray · last 13 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

13 Nov 2026RayPublished by the parts factory: tier lcsc, 48 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • •array (skip): not an array of element pairs
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: EFM32TG222F32-D-QFP48R · TQFP-48(7x7) · 48 pins
  • ✓copper: 48 copper pads, none touching another net
  • ✓datasheet: all 48 pin names found in the 202-page datasheet
  • ✓distributor: lcsc C1852042, digikey 336-EFM32TG222F32-D-QFP48RTR-ND, mouser 634-EFM32TG222F32-DR
  • ✓family: TQFP-48_7x7mm_P0.5mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-2u2ei6a6/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height and body within the datasheet's package drawing (datasheet p.184)
  • ✓pads: 48 pins = 48 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 48 pins agree
  • ✓symbol_text: no pin names collide
  • ✓viewers: viewers/footprint.html 59 kB, viewers/symbol.html 32 kB
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ efm32tg222f32-d-qfp48r.kicad_sym✓ efm32tg222f32-d-qfp48r.kicad_mod✓ efm32tg222f32-d-qfp48r.step
Spot something wrong? Report it as an issue Propose a fix Records are signed by members of adom.
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Ray Publish 0.1.0 8343da7

EFM32TG222F32-D-QFP48R

SILICON LABS · Microcontroller Units (MCUs/MPUs/SOCs) · TQFP-48(7x7)

EFM32TG222F32-D-QFP48R from SILICON LABS, in a TQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model). Symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PA0 bidirectional GPIO PA0 with TIM0_CC0 #0/1/4, LEU0_RX #4, I2C0_SDA #0, PRS_CH0 #0 and EM4 wake-up GPIO_EM4WU0.
2 PA1 bidirectional GPIO PA1 with TIM0_CC1 #0/1, I2C0_SCL #0, CMU_CLK1 #0 and PRS_CH1 #0.
3 PA2 bidirectional GPIO PA2 with TIM0_CC2 #0/1 and CMU_CLK0 #0.
4 IOVDD_0 power_in Digital IO power supply 0.
5 VSS power_in Ground.
6 PC0 bidirectional GPIO PC0 with ACMP0_CH0, DAC0_OUT0ALT/OPAMP_OUT0ALT #0, TIM0_CC1 #4, PCNT0_S0IN #2, US0_TX #5, US1_TX #0, I2C0_SDA #4, LES_CH0 and PRS_CH2 #0.
7 PC1 bidirectional GPIO PC1 with ACMP0_CH1, DAC0_OUT0ALT/OPAMP_OUT0ALT #1, TIM0_CC2 #4, PCNT0_S1IN #2, US0_RX #5, US1_RX #0, I2C0_SCL #4, LES_CH1 and PRS_CH3 #0.
8 PC2 bidirectional GPIO PC2 with ACMP0_CH2, DAC0_OUT0ALT/OPAMP_OUT0ALT #2 and LES_CH2 #0.
9 PC3 bidirectional GPIO PC3 with ACMP0_CH3, DAC0_OUT0ALT/OPAMP_OUT0ALT #3 and LES_CH3 #0.
10 PC4 bidirectional GPIO PC4 with ACMP0_CH4, DAC0_P0/OPAMP_P0, LETIM0_OUT0 #3 and LES_CH4 #0.
11 PB7 bidirectional GPIO PB7 / LFXTAL_P low frequency crystal positive pin, with TIM1_CC0 #3, US0_TX #4 and US1_CLK #0.
12 PB8 bidirectional GPIO PB8 / LFXTAL_N low frequency crystal negative pin (or external clock input), with TIM1_CC1 #3, US0_RX #4 and US1_CS #0.
13 PA8 bidirectional GPIO PA8; no alternate functions listed.
14 PA9 bidirectional GPIO PA9; no alternate functions listed.
15 PA10 bidirectional GPIO PA10; no alternate functions listed.
16 RESETn input Reset input, active low; external reset source should only drive it low during reset and let the internal pull-up release reset.
17 PB11 bidirectional GPIO PB11 with DAC0_OUT0/OPAMP_OUT0, TIM1_CC2 #3 and LETIM0_OUT0 #1.
18 VSS power_in Ground.
19 AVDD_1 power_in Analog power supply 1.
20 PB13 bidirectional GPIO PB13 / HFXTAL_P high frequency crystal positive pin, with US0_CLK #4/5 and LEU0_TX #1.
21 PB14 bidirectional GPIO PB14 / HFXTAL_N high frequency crystal negative pin (or external clock input), with US0_CS #4/5 and LEU0_RX #1.
22 IOVDD_3 power_in Digital IO power supply 3.
23 AVDD_0 power_in Analog power supply 0.
24 PD4 bidirectional GPIO PD4 with ADC0_CH4, OPAMP_P2 and LEU0_TX #0.
25 PD5 bidirectional GPIO PD5 with ADC0_CH5, OPAMP_OUT2 #0 and LEU0_RX #0.
26 PD6 bidirectional GPIO PD6 with ADC0_CH6, DAC0_P1/OPAMP_P1, TIM1_CC0 #4, LETIM0_OUT0 #0, PCNT0_S0IN #3, US1_RX #2, I2C0_SDA #1, LES_ALTEX0 and ACMP0_O #2.
27 PD7 bidirectional GPIO PD7 with ADC0_CH7, DAC0_N1/OPAMP_N1, TIM1_CC1 #4, LETIM0_OUT1 #0, PCNT0_S1IN #3, US1_TX #2, I2C0_SCL #1, CMU_CLK0 #2, LES_ALTEX1 and ACMP1_O #2.
28 VDD_DREG power_in Power supply for on-chip voltage regulator.
29 DECOUPLE passive Decouple output for on-chip voltage regulator; an external capacitance of size CDECOUPLE is required at this pin.
30 PC8 bidirectional GPIO PC8 with ACMP1_CH0, US0_CS #2 and LES_CH8 #0.
31 PC9 bidirectional GPIO PC9 with ACMP1_CH1, US0_CLK #2, LES_CH9 #0 and EM4 wake-up GPIO_EM4WU2.
32 PC10 bidirectional GPIO PC10 with ACMP1_CH2, US0_RX #2 and LES_CH10 #0.
33 PC11 bidirectional GPIO PC11 with ACMP1_CH3, US0_TX #2 and LES_CH11 #0.
34 PC13 bidirectional GPIO PC13 with ACMP1_CH5, DAC0_OUT1ALT/OPAMP_OUT1ALT #1, TIM1_CC0 #0, TIM1_CC2 #4, PCNT0_S0IN #0 and LES_CH13 #0.
35 PC14 bidirectional GPIO PC14 with ACMP1_CH6, DAC0_OUT1ALT/OPAMP_OUT1ALT #2, TIM1_CC1 #0, PCNT0_S1IN #0, US0_CS #3 and LES_CH14 #0.
36 PC15 bidirectional GPIO PC15 with ACMP1_CH7, DAC0_OUT1ALT/OPAMP_OUT1ALT #3, TIM1_CC2 #0, US0_CLK #3, LES_CH15 #0 and DBG_SWO #1.
37 PF0 bidirectional GPIO PF0 with DBG_SWCLK #0/1 (enabled out of reset, built-in pull-down), TIM0_CC0 #5, LETIM0_OUT0 #2, US1_CLK #2, LEU0_TX #3 and I2C0_SDA #5.
38 PF1 bidirectional GPIO PF1 with DBG_SWDIO #0/1 (enabled out of reset, built-in pull-up), TIM0_CC1 #5, LETIM0_OUT1 #2, US1_CS #2, LEU0_RX #3, I2C0_SCL #5 and EM4 wake-up GPIO_EM4WU3.
39 PF2 bidirectional GPIO PF2 with TIM0_CC2 #5, LEU0_TX #4, ACMP1_O #0, DBG_SWO #0 (not enabled after reset) and EM4 wake-up GPIO_EM4WU4.
40 PF3 bidirectional GPIO PF3 with PRS_CH0 #1.
41 PF4 bidirectional GPIO PF4 with PRS_CH1 #1.
42 PF5 bidirectional GPIO PF5 with PRS_CH2 #1.
43 IOVDD_5 power_in Digital IO power supply 5.
44 VSS power_in Ground.
45 PE10 bidirectional GPIO PE10 with TIM1_CC0 #1, US0_TX #0 and BOOT_TX bootloader transmit.
46 PE11 bidirectional GPIO PE11 with TIM1_CC1 #1, US0_RX #0, LES_ALTEX5 #0 and BOOT_RX bootloader receive.
47 PE12 bidirectional GPIO PE12 with TIM1_CC2 #1, US0_RX #3, US0_CLK #0, I2C0_SDA #6, CMU_CLK1 #2 and LES_ALTEX6 #0.
48 PE13 bidirectional GPIO PE13 with US0_TX #3, US0_CS #0, I2C0_SCL #6, LES_ALTEX7 #0, ACMP0_O #0 and EM4 wake-up GPIO_EM4WU5.

Key specifications

Parameter Value
Manufacturer SILICON LABS
Package TQFP-48(7x7)
Category Single Chip Microcomputer/Microcontroller
Pins 48

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Storage temperature range TSTG -40 150 °C 27
Maximum soldering temperature TS 260 °C Latest IPC/JEDEC J-STD-020 Standard 27
External main supply voltage VDDMAX 0 3.8 V 27
Voltage on any I/O pin VIOPIN -0.3 V max printed as VDD+0.3 27
Current per I/O pin (sink) IIOMAX_SINK 100 mA 27
Current per I/O pin (source) IIOMAX_SOURCE -100 mA 27
Ambient temperature range TAMB -40 85 °C 27
Operating supply voltage VDDOP 1.98 3.8 V 27
Internal APB clock frequency fAPB 32 MHz 27
Internal AHB clock frequency fAHB 32 MHz 27
EM0 current IEM0 150 170 µA/MHz 28 MHz HFRCO, all peripheral clocks disabled, VDD= 3.0 V 28
EM0 current IEM0 155 175 µA/MHz 14 MHz HFRCO, all peripheral clocks disabled, VDD= 3.0 V 28
EM0 current IEM0 200 240 µA/MHz 1.2 MHz HFRCO, all peripheral clocks disabled, VDD= 3.0 V 28
EM1 current IEM1 51 57 µA/MHz 28 MHz HFRCO, all peripheral clocks disabled, VDD= 3.0 V 28
EM1 current IEM1 56 61 µA/MHz 14 MHz HFRCO, all peripheral clocks disabled, VDD= 3.0 V 28
EM1 current IEM1 100 122 µA/MHz 1.2 MHz HFRCO, all peripheral clocks disabled, VDD= 3.0 V 28
EM2 current IEM2 1 1.2 µA RTC prescaled to 1 Hz, 32.768 kHz LFRCO, VDD= 3.0 V, TAMB=25ºC 28
EM2 current IEM2 2.4 5 µA RTC prescaled to 1 Hz, 32.768 kHz LFRCO, VDD= 3.0 V, TAMB=85ºC 28
EM3 current IEM3 0.59 1 µA VDD= 3.0 V, TAMB=25ºC 28
EM3 current IEM3 2 4.5 µA VDD= 3.0 V, TAMB=85ºC 28
EM4 current IEM4 0.02 0.055 µA VDD= 3.0 V, TAMB=25ºC 28
EM4 current IEM4 0.25 0.7 µA VDD= 3.0 V, TAMB=85ºC 28
BOD threshold on falling external supply voltage VBODextthr- 1.74 1.96 V 31
BOD threshold on rising external supply voltage VBODextthr+ 1.85 1.98 V 31
Power-on Reset threshold on rising external supply voltage VPORthr+ 1.98 V 31
Flash erase cycles before failure ECFLASH 20000 cycles 31
Flash word write cycles between erase WWCFLASH 2 cycles 31
Flash data retention RETFLASH 10000 h TAMB<150ºC 31
Flash data retention RETFLASH 10 years TAMB<85ºC 31
Flash data retention RETFLASH 20 years TAMB<70ºC 31
Word (32-bit) programming time tW_PROG 20 µs 31
Page erase time tP_ERASE 20 20.4 20.8 ms 31
Device erase time tD_ERASE 40 40.8 41.6 ms 31
Erase current IERASE 7 mA Measured at 25°C 31
Write current IWRITE 7 mA Measured at 25°C 31
Supply voltage during flash erase and write VFLASH 1.98 3.8 V 31
Input low voltage VIOIL 0.3 ×VDD 32
Input high voltage VIOIH 0.7 ×VDD 32
Output high voltage VIOOH 0.75 ×VDD Sourcing 6 mA, VDD=1.98 V, DRIVEMODE = STANDARD 32
Output high voltage VIOOH 0.85 ×VDD Sourcing 6 mA, VDD=3.0 V, DRIVEMODE = STANDARD 32
Output low voltage VIOOL 0.3 ×VDD Sinking 6 mA, VDD=1.98 V, DRIVEMODE = STANDARD 32
Output low voltage VIOOL 0.2 ×VDD Sinking 6 mA, VDD=3.0 V, DRIVEMODE = STANDARD 32
Input leakage current IIOLEAK -100 100 nA High Impedance IO connected to GROUND or VDD 33
Glitch suppression filter pulse width tIOGLITCH 10 50 ns 33
Output fall time tIOOF 250 ns DRIVEMODE = LOWEST and CL=12.5-25pF 33
I/O pin hysteresis VIOHYST 0.1 ×VDD VDD = 1.98 - 3.8 V 33
LFRCO oscillation frequency fLFRCO 31.29 32.768 34.24 kHz VDD=3.0 V, TAMB=25°C 41
LFRCO current consumption ILFRCO 210 380 nA 41
HFRCO oscillation frequency fHFRCO 27.16 28 28.84 MHz 28 MHz frequency band, VDD=3.0 V, TAMB=25ºC 42
HFRCO oscillation frequency fHFRCO 20.37 21 21.63 MHz 21 MHz frequency band, VDD=3.0 V, TAMB=25ºC 42
HFRCO oscillation frequency fHFRCO 13.58 14 14.42 MHz 14 MHz frequency band, VDD=3.0 V, TAMB=25ºC 42
HFRCO oscillation frequency fHFRCO 10.67 11 11.33 MHz 11 MHz frequency band, VDD=3.0 V, TAMB=25ºC 42
HFRCO oscillation frequency fHFRCO 6.401 6.601 6.801 MHz 7 MHz frequency band, VDD=3.0 V, TAMB=25ºC 42
HFRCO oscillation frequency fHFRCO 1.162 1.202 1.242 MHz 1 MHz frequency band, VDD=3.0 V, TAMB=25ºC 42
HFRCO current consumption IHFRCO 104 120 µA fHFRCO = 14 MHz 42
ULFRCO oscillation frequency fULFRCO 0.7 1.75 kHz 25°C, 3V 46
ADC offset voltage VADCOFFSET -4 0.3 4 mV After calibration, single ended 50
ADC differential non-linearity DNLADC -1 0.7 4 LSB VDD= 3.0 V, external 2.5V reference 50
ADC integral non-linearity INLADC 1.2 3 LSB VDD= 3.0 V, external 2.5V reference 50
ACMP offset voltage VACMPOFFSET -12 0 12 mV BIASPROG= 0b1010, FULLBIAS=0 and HALFBIAS=0 in ACMPn_CTRL register 64

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts gold The TQFP48 package is 7 by 7 mm in size and has a 0.5 mm pin pitch. The TQFP48 package uses Nickel-Palladium-Gold preplated leadframe. 184

CAD (KiCad official)

  • Symbol: EFM32TG222F32-D-QFP48R
  • Footprint: Package_QFP:TQFP-48_7x7mm_P0.5mm
  • 3D model: TQFP-48(7x7) (KiCad packages3D, STEP)
  • 3D model files: efm32tg222f32-d-qfp48r-etched.step / efm32tg222f32-d-qfp48r-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); efm32tg222f32-d-qfp48r.step / efm32tg222f32-d-qfp48r.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: SILICON LABS datasheet (202 pp, sha256 d84cadd4d3d5f69c, retrieved 2026-11-13, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF