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EFM32TG11B140F64GQ48-B

Public Made by Adom

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SILICON LABS Pre-ordered MCUs, TQFP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentembedded processors & controllersefm32tg11b140f64gq48-bfactory-2.0.0extractor-text

Verified EFM32TG11B140F64GQ48-B

by Ray · last 13 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

13 Nov 2026RayPublished by the parts factory: tier lcsc, 48 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • •array (skip): not an array of element pairs
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: EFM32TG11B140F64GQ48-B · TQFP-48(7x7) · 48 pins
  • ✓copper: 48 copper pads, none touching another net
  • ✓datasheet: all 48 pin names found in the 153-page datasheet
  • ✓distributor: lcsc C1341099, digikey EFM32TG11B140F64GQ48-B-ND, mouser 634-EFM32TG64GQ48-B
  • ✓family: TQFP-48_7x7mm_P0.5mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-_iogg09d/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height and body within the datasheet's package drawing (datasheet p.144)
  • ✓pads: 48 pins = 48 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 48 pins agree
  • ✓symbol_text: no pin names collide
  • ✓viewers: viewers/footprint.html 59 kB, viewers/symbol.html 32 kB
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ efm32tg11b140f64gq48-b.kicad_sym✓ efm32tg11b140f64gq48-b.kicad_mod✓ efm32tg11b140f64gq48-b.step
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Ray Publish 0.1.0 54311fd

EFM32TG11B140F64GQ48-B

SILICON LABS · Pre-ordered MCUs · TQFP-48(7x7)

EFM32TG11B140F64GQ48-B from SILICON LABS, in a TQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model). Symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PA0 bidirectional General purpose I/O (no 5 V tolerance); DC voltage limited to -0.3 V to IOVDD + 0.3 V per Table 4.1, alternate functions per Table 5.14.
2 PA1 bidirectional General purpose I/O (no 5 V tolerance); DC voltage limited to -0.3 V to IOVDD + 0.3 V per Table 4.1, alternate functions per Table 5.14.
3 PA2 bidirectional General purpose I/O (no 5 V tolerance); DC voltage limited to -0.3 V to IOVDD + 0.3 V per Table 4.1, alternate functions per Table 5.14.
4 IOVDD0 power_in Digital IO power supply 0; the standard GPIO voltage limits in Table 4.1 are referenced to IOVDD. This package has three IOVDD0 pins (4, 22, 43).
5 VSS power_in Ground; this package has three VSS pins (5, 18, 44).
6 PC0 bidirectional General purpose I/O with 5 V tolerance; DC voltage limited to the minimum of 5.25 V and IOVDD + 2 V per Table 4.1.
7 PC1 bidirectional General purpose I/O with 5 V tolerance; DC voltage limited to the minimum of 5.25 V and IOVDD + 2 V per Table 4.1.
8 PC2 bidirectional General purpose I/O with 5 V tolerance; DC voltage limited to the minimum of 5.25 V and IOVDD + 2 V per Table 4.1.
9 PC3 bidirectional General purpose I/O with 5 V tolerance; DC voltage limited to the minimum of 5.25 V and IOVDD + 2 V per Table 4.1.
10 PC4 bidirectional General purpose I/O (no 5 V tolerance); DC voltage limited to -0.3 V to IOVDD + 0.3 V per Table 4.1, alternate functions per Table 5.14.
11 PB7 bidirectional General purpose I/O (no 5 V tolerance); DC voltage limited to -0.3 V to IOVDD + 0.3 V per Table 4.1, alternate functions per Table 5.14.
12 PB8 bidirectional General purpose I/O (no 5 V tolerance); DC voltage limited to -0.3 V to IOVDD + 0.3 V per Table 4.1, alternate functions per Table 5.14.
13 PA8 bidirectional General purpose I/O (no 5 V tolerance); DC voltage limited to -0.3 V to IOVDD + 0.3 V per Table 4.1, alternate functions per Table 5.14.
14 PA9 bidirectional General purpose I/O (no 5 V tolerance); DC voltage limited to -0.3 V to IOVDD + 0.3 V per Table 4.1, alternate functions per Table 5.14.
15 PA10 bidirectional General purpose I/O (no 5 V tolerance); DC voltage limited to -0.3 V to IOVDD + 0.3 V per Table 4.1, alternate functions per Table 5.14.
16 RESETn input Reset input, active low; drive this pin low only during reset and let the internal pull-up ensure that reset is released.
17 PB11 bidirectional General purpose I/O (no 5 V tolerance); DC voltage limited to -0.3 V to IOVDD + 0.3 V per Table 4.1, alternate functions per Table 5.14.
18 VSS power_in Ground; this package has three VSS pins (5, 18, 44).
19 AVDD power_in Analog power supply; the absolute maximum voltage on any supply pin is 3.8 V per Table 4.1. This package has two AVDD pins (19, 23).
20 PB13 bidirectional General purpose I/O (no 5 V tolerance); DC voltage limited to -0.3 V to IOVDD + 0.3 V per Table 4.1, alternate functions per Table 5.14.
21 PB14 bidirectional General purpose I/O (no 5 V tolerance); DC voltage limited to -0.3 V to IOVDD + 0.3 V per Table 4.1, alternate functions per Table 5.14.
22 IOVDD0 power_in Digital IO power supply 0; the standard GPIO voltage limits in Table 4.1 are referenced to IOVDD. This package has three IOVDD0 pins (4, 22, 43).
23 AVDD power_in Analog power supply; the absolute maximum voltage on any supply pin is 3.8 V per Table 4.1. This package has two AVDD pins (19, 23).
24 PD4 bidirectional General purpose I/O (no 5 V tolerance); DC voltage limited to -0.3 V to IOVDD + 0.3 V per Table 4.1, alternate functions per Table 5.14.
25 PD5 bidirectional General purpose I/O (no 5 V tolerance); DC voltage limited to -0.3 V to IOVDD + 0.3 V per Table 4.1, alternate functions per Table 5.14.
26 PD6 bidirectional General purpose I/O (no 5 V tolerance); DC voltage limited to -0.3 V to IOVDD + 0.3 V per Table 4.1, alternate functions per Table 5.14.
27 PD7 bidirectional General purpose I/O (no 5 V tolerance); DC voltage limited to -0.3 V to IOVDD + 0.3 V per Table 4.1, alternate functions per Table 5.14.
28 DVDD power_in Digital power supply; the absolute maximum voltage on any supply pin is 3.8 V per Table 4.1.
29 DECOUPLE power_out Decouple output for the on-chip voltage regulator; an external decoupling capacitor is required at this pin.
30 PC8 bidirectional General purpose I/O (no 5 V tolerance); DC voltage limited to -0.3 V to IOVDD + 0.3 V per Table 4.1, alternate functions per Table 5.14.
31 PC9 bidirectional General purpose I/O (no 5 V tolerance); DC voltage limited to -0.3 V to IOVDD + 0.3 V per Table 4.1, alternate functions per Table 5.14.
32 PC10 bidirectional General purpose I/O with 5 V tolerance; DC voltage limited to the minimum of 5.25 V and IOVDD + 2 V per Table 4.1.
33 PC11 bidirectional General purpose I/O with 5 V tolerance; DC voltage limited to the minimum of 5.25 V and IOVDD + 2 V per Table 4.1.
34 PC13 bidirectional General purpose I/O with 5 V tolerance; DC voltage limited to the minimum of 5.25 V and IOVDD + 2 V per Table 4.1.
35 PC14 bidirectional General purpose I/O with 5 V tolerance; DC voltage limited to the minimum of 5.25 V and IOVDD + 2 V per Table 4.1.
36 PC15 bidirectional General purpose I/O with 5 V tolerance; DC voltage limited to the minimum of 5.25 V and IOVDD + 2 V per Table 4.1.
37 PF0 bidirectional General purpose I/O with 5 V tolerance; DC voltage limited to the minimum of 5.25 V and IOVDD + 2 V per Table 4.1.
38 PF1 bidirectional General purpose I/O with 5 V tolerance; DC voltage limited to the minimum of 5.25 V and IOVDD + 2 V per Table 4.1.
39 PF2 bidirectional General purpose I/O (no 5 V tolerance); DC voltage limited to -0.3 V to IOVDD + 0.3 V per Table 4.1, alternate functions per Table 5.14.
40 PF3 bidirectional General purpose I/O (no 5 V tolerance); DC voltage limited to -0.3 V to IOVDD + 0.3 V per Table 4.1, alternate functions per Table 5.14.
41 PF4 bidirectional General purpose I/O (no 5 V tolerance); DC voltage limited to -0.3 V to IOVDD + 0.3 V per Table 4.1, alternate functions per Table 5.14.
42 PF5 bidirectional General purpose I/O (no 5 V tolerance); DC voltage limited to -0.3 V to IOVDD + 0.3 V per Table 4.1, alternate functions per Table 5.14.
43 IOVDD0 power_in Digital IO power supply 0; the standard GPIO voltage limits in Table 4.1 are referenced to IOVDD. This package has three IOVDD0 pins (4, 22, 43).
44 VSS power_in Ground; this package has three VSS pins (5, 18, 44).
45 PE10 bidirectional General purpose I/O (no 5 V tolerance); DC voltage limited to -0.3 V to IOVDD + 0.3 V per Table 4.1, alternate functions per Table 5.14.
46 PE11 bidirectional General purpose I/O (no 5 V tolerance); DC voltage limited to -0.3 V to IOVDD + 0.3 V per Table 4.1, alternate functions per Table 5.14.
47 PE12 bidirectional General purpose I/O (no 5 V tolerance); DC voltage limited to -0.3 V to IOVDD + 0.3 V per Table 4.1, alternate functions per Table 5.14.
48 PE13 bidirectional General purpose I/O (no 5 V tolerance); DC voltage limited to -0.3 V to IOVDD + 0.3 V per Table 4.1, alternate functions per Table 5.14.

Key specifications

Parameter Value
Manufacturer SILICON LABS
Package TQFP-48(7x7)
Category Embedded Processors & Controllers
Pins 48

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Operating ambient temperature range TA -40 25 85 °C -G temperature grade 21
AVDD supply voltage VAVDD 1.8 3.3 3.8 V 21
VREGVDD operating supply voltage VVREGVDD 1.8 3.3 3.8 V DCDC not in use. DVDD externally shorted to VREGVDD 21
DVDD operating supply voltage VDVDD 1.62 V 21
IOVDD operating supply voltage VIOVDD 1.62 V All IOVDD pins 21
DECOUPLE output capacitor CDECOUPLE 0.75 1 2.75 µF 21
HFCORECLK frequency fCORE 48 MHz VSCALE2, MODE = WS1 21
HFCORECLK frequency fCORE 25 MHz VSCALE2, MODE = WS0 21
HFCORECLK frequency fCORE 20 MHz VSCALE0, MODE = WS1 21
HFCORECLK frequency fCORE 10 MHz VSCALE0, MODE = WS0 21
HFCLK frequency fHFCLK 48 MHz VSCALE2 21
HFCLK frequency fHFCLK 20 MHz VSCALE0 21
HFSRCCLK frequency fHFSRCCLK 48 MHz VSCALE2 21
HFSRCCLK frequency fHFSRCCLK 20 MHz VSCALE0 21
HFBUSCLK frequency fHFBUSCLK 48 MHz VSCALE2 21
HFBUSCLK frequency fHFBUSCLK 20 MHz VSCALE0 21
HFPERCLK frequency fHFPERCLK 48 MHz VSCALE2 21
HFPERCLK frequency fHFPERCLK 20 MHz VSCALE0 21
HFPERBCLK frequency fHFPERBCLK 48 MHz VSCALE2 21
HFPERBCLK frequency fHFPERBCLK 20 MHz VSCALE0 21
HFPERCCLK frequency fHFPERCCLK 48 MHz VSCALE2 21
HFPERCCLK frequency fHFPERCCLK 20 MHz VSCALE0 21
Storage temperature range TSTG -50 150 °C 19
Voltage on any supply pin VDDMAX -0.3 3.8 V 19
Voltage ramp rate on any supply pin VDDRAMPMAX 1 V / µs 19
DC voltage on any GPIO pin VDIGPIN -0.3 V 5V tolerant GPIO pins 19
Total current into VDD power lines IVDDMAX 200 mA Source 19
Total current into VSS ground lines IVSSMAX 200 mA Sink 19
Current per I/O pin IIOMAX 50 mA Sink 19
Current for all I/O pins IIOALLMAX 200 mA Sink 19
Junction temperature TJ -40 105 °C -G grade devices 19
AUXHFRCO frequency accuracy fAUXHFRCO_ACC -3 3 % At production calibrated frequencies, across supply voltage and temperature 40
Oscillation frequency (ULFRCO) fULFRCO 0.88 1 1.12 kHz 40
Flash erase cycles before failure ECFLASH 10000 cycles 41
Flash data retention RETFLASH 10 years T ≤ 85 °C 41
Word (32-bit) programming time tW_PROG 20 26 32 µs Burst write, 128 words, average time per word 41
Word (32-bit) programming time tW_PROG 59 68 83 µs Single word 41
Page erase time tPERASE 20 27 35 ms 41
Mass erase time tMERASE 20 27 35 ms 41
Device erase time tDERASE 54 70 ms T ≤ 85 °C 41
Erase current IERASE 1.7 mA Page Erase 41
Erase current IERASE 2 mA Mass or Device Erase 41
Write current IWRITE 3.5 mA 41
Supply voltage during flash erase and write VFLASH 1.62 3.6 V 41
Input leakage current IIOLEAK 0.1 40 nA All GPIO except LFXO pins, GPIO ≤ IOVDD, T ≤ 85 °C 42
Input leakage current IIOLEAK 0.1 60 nA LFXO Pins, GPIO ≤ IOVDD, T ≤ 85 °C 42
Input leakage current IIOLEAK 150 nA All GPIO except LFXO pins, GPIO ≤ IOVDD, T > 85 °C 42
Input leakage current IIOLEAK 300 nA LFXO Pins, GPIO ≤ IOVDD, T > 85 °C 42
Input leakage current on 5VTOL pads above IOVDD I5VTOLLEAK 3.3 15 µA IOVDD < GPIO ≤ IOVDD + 2 V 42
I/O pin pull-up/pull-down resistor RPUD 30 40 65 kΩ 42
Pulse width of pulses removed by the glitch suppression filter tIOGLITCH 15 25 45 ns 42
Thermal resistance, TQFP48 Package THETAJA_TQFP48 44.1 °C/W 4-Layer PCB, Air velocity = 0 m/s 22
Thermal resistance, TQFP48 Package THETAJA_TQFP48 43.5 °C/W 4-Layer PCB, Air velocity = 1 m/s 22
Thermal resistance, TQFP48 Package THETAJA_TQFP48 42.3 °C/W 4-Layer PCB, Air velocity = 2 m/s 22

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
housing PC 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components. 126

CAD (KiCad official)

  • Symbol: EFM32TG11B140F64GQ48-B
  • Footprint: Package_QFP:TQFP-48_7x7mm_P0.5mm
  • 3D model: TQFP-48(7x7) (KiCad packages3D, STEP)
  • 3D model files: efm32tg11b140f64gq48-b-etched.step / efm32tg11b140f64gq48-b-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); efm32tg11b140f64gq48-b.step / efm32tg11b140f64gq48-b.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: SILICON LABS datasheet (153 pp, sha256 24bd24b451bb61c6, retrieved 2026-11-13, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF