component
EFM32PG23B210F128IM48-C
Public Made by Adomby adom
SKYWORKS/SILICON LABS Microcontroller Units (MCUs/MPUs/SOCs), QFN-48(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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EFM32PG23B210F128IM48-C
SKYWORKS/SILICON LABS · Microcontroller Units (MCUs/MPUs/SOCs) · QFN-48(6x6)
EFM32PG23B210F128IM48-C from SKYWORKS/SILICON LABS, in a QFN-48(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PC00 | bidirectional | GPIO port C pin 0, with alternate functions GPIO.EM4WU6 and LCD.SEG0. |
| 2 | PC01 | bidirectional | GPIO port C pin 1, with alternate function LCD.SEG1. |
| 3 | PC02 | bidirectional | GPIO port C pin 2, with alternate function LCD.SEG2. |
| 4 | PC03 | bidirectional | GPIO port C pin 3, with alternate function LCD.SEG3. |
| 5 | PC04 | bidirectional | GPIO port C pin 4, with alternate function LCD.SEG4. |
| 6 | PC05 | bidirectional | GPIO port C pin 5, with alternate functions GPIO.EM4WU7 and LCD.SEG5. |
| 7 | PC06 | bidirectional | GPIO port C pin 6, with alternate function LCD.SEG6. |
| 8 | PC07 | bidirectional | GPIO port C pin 7, with alternate functions GPIO.EM4WU8 and LCD.SEG7. |
| 9 | PC08 | bidirectional | GPIO port C pin 8, with alternate function LCD.SEG18. |
| 10 | PC09 | bidirectional | GPIO port C pin 9, with alternate function LCD.SEG19. |
| 11 | HFXTAL_I | input | High frequency crystal oscillator input pin. |
| 12 | HFXTAL_O | output | High frequency crystal oscillator output pin. |
| 13 | RESETn | input | Active-low reset pin with internal pull-up to DVDD (33-55 kΩ); must be held low at least 100 ns to ensure a pin reset. |
| 14 | DVDD | power_in | Digital VDD supply pin, 1.71 V to 3.8 V; must be shorted to VREGVDD when the DCDC is not used. |
| 15 | NC | unconnected | No connection. |
| 16 | PB06 | bidirectional | GPIO port B pin 6. |
| 17 | PB05 | bidirectional | GPIO port B pin 5. |
| 18 | PB04 | bidirectional | GPIO port B pin 4. |
| 19 | PB03 | bidirectional | GPIO port B pin 3, with alternate functions GPIO.EM4WU4 and LCD.SEG17. |
| 20 | PB02 | bidirectional | GPIO port B pin 2, with alternate function LCD.SEG16. |
| 21 | PB01 | bidirectional | GPIO port B pin 1, with alternate functions GPIO.EM4WU3, LCD.SEG15 and VDAC0.CH1_MAIN_OUT. |
| 22 | PB00 | bidirectional | GPIO port B pin 0, with alternate functions LCD.SEG14 and VDAC0.CH0_MAIN_OUT. |
| 23 | AIN1 | input | Dedicated ADC input 1. |
| 24 | AIN0 | input | Dedicated ADC input 0. |
| 25 | PA00 | bidirectional | GPIO port A pin 0, with alternate functions IADC0.VREFP and LCD.SEG8. |
| 26 | PA01 | bidirectional | GPIO port A pin 1, with alternate functions GPIO.SWCLK and LCD.SEG9. |
| 27 | PA02 | bidirectional | GPIO port A pin 2, with alternate function GPIO.SWDIO. |
| 28 | PA03 | bidirectional | GPIO port A pin 3, with alternate functions GPIO.SWV, GPIO.TDO, GPIO.TRACEDATA0 and LESENSE.EN_0. |
| 29 | PA04 | bidirectional | GPIO port A pin 4, with alternate functions GPIO.TDI, GPIO.TRACECLK, LCD.SEG10 and LESENSE.EN_1. |
| 30 | PA05 | bidirectional | GPIO port A pin 5, with alternate functions GPIO.TRACEDATA1, GPIO.EM4WU0, LCD.SEG11 and LESENSE.EN_2. |
| 31 | PA06 | bidirectional | GPIO port A pin 6, with alternate functions GPIO.TRACEDATA2 and LCD.LCD_CP. |
| 32 | PA07 | bidirectional | GPIO port A pin 7, with alternate functions GPIO.TRACEDATA3 and LCD.SEG12. |
| 33 | PA08 | bidirectional | GPIO port A pin 8, with alternate function LCD.SEG13. |
| 34 | PA09 | bidirectional | GPIO port A pin 9. |
| 35 | PA10 | bidirectional | GPIO port A pin 10. |
| 36 | DECOUPLE | passive | Decoupling capacitor pin; a 1.0 µF capacitor (0.75 to 2.75 µF allowed) is connected here and DVDD must be at or above DECOUPLE. |
| 37 | VREGSW | power_out | DCDC converter output (inductor) pin. |
| 38 | VREGVDD | power_in | DCDC input supply pin, 2.2 V to 3.8 V with DCDC in regulation, and must be at or above DVDD. |
| 39 | VREGVSS | power_in | DCDC ground pin. |
| 40 | DVDD | power_in | Digital VDD supply pin, 1.71 V to 3.8 V; DCDC buck converter output when the DCDC is used and then not driven externally. |
| 41 | AVDD | power_in | Analog VDD supply pin, 1.71 V to 3.8 V. |
| 42 | IOVDD | power_in | I/O VDD supply pin, 1.71 V to 3.8 V. |
| 43 | PD05 | bidirectional | GPIO port D pin 5, with alternate functions GPIO.EM4WU10 and LCD.COM3. |
| 44 | PD04 | bidirectional | GPIO port D pin 4, with alternate function LCD.COM2. |
| 45 | PD03 | bidirectional | GPIO port D pin 3, with alternate function LCD.COM1. |
| 46 | PD02 | bidirectional | GPIO port D pin 2, with alternate functions GPIO.EM4WU9 and LCD.COM0. |
| 47 | PD01 | bidirectional | GPIO port D pin 1, with alternate functions LFXO.LFXTAL_I and LFXO.LF_EXTCLK. |
| 48 | PD00 | bidirectional | GPIO port D pin 0, with alternate function LFXO.LFXTAL_O. |
| 49 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | SKYWORKS/SILICON LABS |
| Package | QFN-48(6x6) |
| Category | Single Chip Microcomputer/Microcontroller |
| Pins | 49 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Storage temperature range | TSTG | -50 | 150 | °C | 21 | ||
| Voltage on any supply pin | VDDMAX | -0.3 | 3.8 | V | 21 | ||
| Junction temperature | TJMAX | 125 | °C | -I grade | 21 | ||
| Voltage ramp rate on any supply pin | VDDRAMPMAX | 1 | V / µs | 21 | |||
| Voltage on HFXO pins | VHFXOPIN | -0.3 | 1.2 | V | 21 | ||
| DC voltage on RESETn pin | VRESETn | -0.3 | 3.8 | V | 21 | ||
| Total current into VDD power lines | IVDDMAX | 200 | mA | Source | 21 | ||
| Total current into VSS ground lines | IVSSMAX | 200 | mA | Sink | 21 | ||
| Current per I/O pin (sink) | IIOMAX | 50 | mA | Sink | 21 | ||
| Current per I/O pin (source) | IIOMAX | 50 | mA | Source | 21 | ||
| Current for all I/O pins (sink) | IIOALLMAX | 200 | mA | Sink | 21 | ||
| Current for all I/O pins (source) | IIOALLMAX | 200 | mA | Source | 21 | ||
| DC voltage on any GPIO pin | VDIGPIN | -0.3 | V | max is VIOVDD + 0.3 V | 21 | ||
| Operating ambient temperature range | TA | -40 | 125 | °C | -I temperature grade | 22 | |
| DVDD supply voltage | VDVDD | 1.71 | 3.3 | 3.8 | V | EM0/1 | 22 |
| AVDD supply voltage | VAVDD | 1.71 | 3.3 | 3.8 | V | 22 | |
| IOVDD operating supply voltage | VIOVDD | 1.71 | 3.3 | 3.8 | V | 22 | |
| VREGVDD operating supply voltage | VVREGVDD | 2.2 | 3.3 | 3.8 | V | DCDC in regulation | 22 |
| VREGVDD operating supply voltage | VVREGVDD | 1.8 | 3.3 | 3.8 | V | DCDC in bypass 60 mA load | 22 |
| VREGVDD operating supply voltage | VVREGVDD | 1.71 | 3.3 | 3.8 | V | DCDC not in use. DVDD externally shorted to VREGVDD | 22 |
| DECOUPLE output capacitor | CDECOUPLE | 0.75 | 1 | 2.75 | µF | 1.0 µF ± 10% X8L capacitor used for performance characterization. | 22 |
| HCLK and SYSCLK frequency | fHCLK | 80 | MHz | VSCALE2, MODE = WS1 | 22 | ||
| HCLK and SYSCLK frequency | fHCLK | 40 | MHz | VSCALE2, MODE = WS0 | 22 | ||
| HCLK and SYSCLK frequency | fHCLK | 20 | MHz | VSCALE1, MODE = WS0 | 22 | ||
| PCLK frequency | fPCLK | 40 | MHz | VSCALE2 or VSCALE1 | 22 | ||
| External Clock Input | fCLKIN | 40 | MHz | VSCALE2 or VSCALE1, IOVDD ≥ 2.7 V | 22 | ||
| DCDC regulation DC accuracy | ACCDC | -2.5 | 4 | % | VVREGVDD ≥ 2.2 V, Steady state in EM0/EM1 mode or EM2/EM3 mode | 23 | |
| DCDC regulation total accuracy | ACCTOT | -5 | 7 | % | All error sources (including DC errors, overshoot, undershoot) | 23 | |
| DCDC input voltage range at VREGVDD | VVREGVDD | 2.2 | 3.8 | V | DCDC in regulation, ILOAD = 60 mA, EM0/EM1 mode | 23 | |
| DCDC input voltage range at VREGVDD | VVREGVDD | 1.8 | 3.8 | V | DCDC in regulation, ILOAD = 5 mA, EM0/EM1 or EM2/EM3 mode | 23 | |
| DCDC output load current | ILOAD | 60 | mA | EM0/EM1 mode, DCDC in regulation | 23 | ||
| DCDC output load current | ILOAD | 5 | mA | EM2/EM3 mode, DCDC in regulation | 23 | ||
| DCDC output capacitor | CDCDC | 4.7 | 10 | µF | 4.7 µF ± 10% X7R capacitor used for performance characterization | 23 | |
| DCDC bypass switch resistance | RBYP | 0.45 | 0.8 | Ω | Bypass switch from VREGVDD to DVDD, VVREGVDD = 1.8 V | 23 | |
| DCDC powertrain PFET resistance | RBYP | 0.6 | 0.9 | Ω | Powertrain PFET switch from VREGVDD to VREGSW, VVREGVDD = 1.8 V | 23 | |
| Supply monitor threshold programming range | VCMP_RNG | 2 | 2.3 | V | Programmable in 0.1 V steps | 23 | |
| Supply monitor threshold accuracy | VCMP_ACC | -5 | 5 | % | Supply falling edge trip point | 23 | |
| Thermal resistance junction to ambient, 48QFN | ΘJA | 27.7 | °C/W | JEDEC 2s2p, Still Air | 24 | ||
| Thermal resistance junction to board, 48QFN | ΘJB | 14.6 | °C/W | JEDEC 2s2p | 24 | ||
| Thermal resistance junction to case, 48QFN | ΘJC | 23 | °C/W | No Board, temperature controlled heat sink on top of package, all other sides insulated | 24 | ||
| Flash supply voltage during write or erase | VFLASH | 1.71 | 3.8 | V | 32 | ||
| Flash data retention | RETFLASH | 10 | years | 32 | |||
| Flash erase cycles before failure | ECFLASH | 10000 | cycles | 32 | |||
| Program time | tPROG | 41 | 44.4 | 47.9 | µs | one word (32-bits) | 32 |
| Page erase time | tPERASE | 11.8 | 12.5 | 14.6 | ms | 32 | |
| Mass erase time | tMERASE | 47.2 | 50.1 | 58.3 | ms | 512 kB | 32 |
| Program current | IWRITE | 2.4 | mA | TA = 25 °C | 32 | ||
| Page erase current | IERASE | 1.9 | mA | TA = 25 °C | 32 | ||
| HFXO crystal frequency | FHFXO | 38 | 39 | 40 | MHz | 33 | |
| HFXO crystal max ESR | ESRHFXO | 60 | Ω | 39.0 MHz | 33 | ||
| HFRCO frequency accuracy | FHFRCO_ACC | -3 | 3 | % | For all production calibrated frequencies | 35 | |
| FSRCO frequency | FFSRCO | 17.2 | 20 | 21.2 | MHz | 36 | |
| LFRCO frequency accuracy | FLFRCO_ACC | -3 | 3 | % | 37 | ||
| ULFRCO oscillation frequency | FULFRCO | 0.944 | 1 | 1.095 | kHz | 37 | |
| EM2 current, 64 kB RAM retention, RTC from LFXO | IEM2_VS | 1.33 | µA | VSCALE0, 64 kB RAM retention, RTC running from LFXO | 25 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | PC | 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. | 90 |
CAD (KiCad official)
- Symbol:
EFM32PG23B210F128IM48-C - Footprint:
Package_DFN_QFN:QFN-48-1EP_6x6mm_P0.4mm_EP4.2x4.2mm - 3D model: QFN-48(6x6), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.9 mm nominal QFN height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files:
efm32pg23b210f128im48-c-etched.step/efm32pg23b210f128im48-c-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);efm32pg23b210f128im48-c.step/efm32pg23b210f128im48-c.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: SKYWORKS/SILICON LABS datasheet (99 pp, sha256
a4ad4405a1050471, retrieved 2026-10-31, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# EFM32PG23B210F128IM48-C
**SKYWORKS/SILICON LABS** · Microcontroller Units (MCUs/MPUs/SOCs) · QFN-48(6x6)
EFM32PG23B210F128IM48-C from SKYWORKS/SILICON LABS, in a QFN-48(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PC00 | bidirectional | GPIO port C pin 0, with alternate functions GPIO.EM4WU6 and LCD.SEG0. |
| 2 | PC01 | bidirectional | GPIO port C pin 1, with alternate function LCD.SEG1. |
| 3 | PC02 | bidirectional | GPIO port C pin 2, with alternate function LCD.SEG2. |
| 4 | PC03 | bidirectional | GPIO port C pin 3, with alternate function LCD.SEG3. |
| 5 | PC04 | bidirectional | GPIO port C pin 4, with alternate function LCD.SEG4. |
| 6 | PC05 | bidirectional | GPIO port C pin 5, with alternate functions GPIO.EM4WU7 and LCD.SEG5. |
| 7 | PC06 | bidirectional | GPIO port C pin 6, with alternate function LCD.SEG6. |
| 8 | PC07 | bidirectional | GPIO port C pin 7, with alternate functions GPIO.EM4WU8 and LCD.SEG7. |
| 9 | PC08 | bidirectional | GPIO port C pin 8, with alternate function LCD.SEG18. |
| 10 | PC09 | bidirectional | GPIO port C pin 9, with alternate function LCD.SEG19. |
| 11 | HFXTAL_I | input | High frequency crystal oscillator input pin. |
| 12 | HFXTAL_O | output | High frequency crystal oscillator output pin. |
| 13 | RESETn | input | Active-low reset pin with internal pull-up to DVDD (33-55 kΩ); must be held low at least 100 ns to ensure a pin reset. |
| 14 | DVDD | power_in | Digital VDD supply pin, 1.71 V to 3.8 V; must be shorted to VREGVDD when the DCDC is not used. |
| 15 | NC | unconnected | No connection. |
| 16 | PB06 | bidirectional | GPIO port B pin 6. |
| 17 | PB05 | bidirectional | GPIO port B pin 5. |
| 18 | PB04 | bidirectional | GPIO port B pin 4. |
| 19 | PB03 | bidirectional | GPIO port B pin 3, with alternate functions GPIO.EM4WU4 and LCD.SEG17. |
| 20 | PB02 | bidirectional | GPIO port B pin 2, with alternate function LCD.SEG16. |
| 21 | PB01 | bidirectional | GPIO port B pin 1, with alternate functions GPIO.EM4WU3, LCD.SEG15 and VDAC0.CH1_MAIN_OUT. |
| 22 | PB00 | bidirectional | GPIO port B pin 0, with alternate functions LCD.SEG14 and VDAC0.CH0_MAIN_OUT. |
| 23 | AIN1 | input | Dedicated ADC input 1. |
| 24 | AIN0 | input | Dedicated ADC input 0. |
| 25 | PA00 | bidirectional | GPIO port A pin 0, with alternate functions IADC0.VREFP and LCD.SEG8. |
| 26 | PA01 | bidirectional | GPIO port A pin 1, with alternate functions GPIO.SWCLK and LCD.SEG9. |
| 27 | PA02 | bidirectional | GPIO port A pin 2, with alternate function GPIO.SWDIO. |
| 28 | PA03 | bidirectional | GPIO port A pin 3, with alternate functions GPIO.SWV, GPIO.TDO, GPIO.TRACEDATA0 and LESENSE.EN_0. |
| 29 | PA04 | bidirectional | GPIO port A pin 4, with alternate functions GPIO.TDI, GPIO.TRACECLK, LCD.SEG10 and LESENSE.EN_1. |
| 30 | PA05 | bidirectional | GPIO port A pin 5, with alternate functions GPIO.TRACEDATA1, GPIO.EM4WU0, LCD.SEG11 and LESENSE.EN_2. |
| 31 | PA06 | bidirectional | GPIO port A pin 6, with alternate functions GPIO.TRACEDATA2 and LCD.LCD_CP. |
| 32 | PA07 | bidirectional | GPIO port A pin 7, with alternate functions GPIO.TRACEDATA3 and LCD.SEG12. |
| 33 | PA08 | bidirectional | GPIO port A pin 8, with alternate function LCD.SEG13. |
| 34 | PA09 | bidirectional | GPIO port A pin 9. |
| 35 | PA10 | bidirectional | GPIO port A pin 10. |
| 36 | DECOUPLE | passive | Decoupling capacitor pin; a 1.0 µF capacitor (0.75 to 2.75 µF allowed) is connected here and DVDD must be at or above DECOUPLE. |
| 37 | VREGSW | power_out | DCDC converter output (inductor) pin. |
| 38 | VREGVDD | power_in | DCDC input supply pin, 2.2 V to 3.8 V with DCDC in regulation, and must be at or above DVDD. |
| 39 | VREGVSS | power_in | DCDC ground pin. |
| 40 | DVDD | power_in | Digital VDD supply pin, 1.71 V to 3.8 V; DCDC buck converter output when the DCDC is used and then not driven externally. |
| 41 | AVDD | power_in | Analog VDD supply pin, 1.71 V to 3.8 V. |
| 42 | IOVDD | power_in | I/O VDD supply pin, 1.71 V to 3.8 V. |
| 43 | PD05 | bidirectional | GPIO port D pin 5, with alternate functions GPIO.EM4WU10 and LCD.COM3. |
| 44 | PD04 | bidirectional | GPIO port D pin 4, with alternate function LCD.COM2. |
| 45 | PD03 | bidirectional | GPIO port D pin 3, with alternate function LCD.COM1. |
| 46 | PD02 | bidirectional | GPIO port D pin 2, with alternate functions GPIO.EM4WU9 and LCD.COM0. |
| 47 | PD01 | bidirectional | GPIO port D pin 1, with alternate functions LFXO.LFXTAL_I and LFXO.LF_EXTCLK. |
| 48 | PD00 | bidirectional | GPIO port D pin 0, with alternate function LFXO.LFXTAL_O. |
| 49 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | SKYWORKS/SILICON LABS |
| Package | QFN-48(6x6) |
| Category | Single Chip Microcomputer/Microcontroller |
| Pins | 49 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Storage temperature range | TSTG | -50 | | 150 | °C | | 21 |
| Voltage on any supply pin | VDDMAX | -0.3 | | 3.8 | V | | 21 |
| Junction temperature | TJMAX | | | 125 | °C | -I grade | 21 |
| Voltage ramp rate on any supply pin | VDDRAMPMAX | | | 1 | V / µs | | 21 |
| Voltage on HFXO pins | VHFXOPIN | -0.3 | | 1.2 | V | | 21 |
| DC voltage on RESETn pin | VRESETn | -0.3 | | 3.8 | V | | 21 |
| Total current into VDD power lines | IVDDMAX | | | 200 | mA | Source | 21 |
| Total current into VSS ground lines | IVSSMAX | | | 200 | mA | Sink | 21 |
| Current per I/O pin (sink) | IIOMAX | | | 50 | mA | Sink | 21 |
| Current per I/O pin (source) | IIOMAX | | | 50 | mA | Source | 21 |
| Current for all I/O pins (sink) | IIOALLMAX | | | 200 | mA | Sink | 21 |
| Current for all I/O pins (source) | IIOALLMAX | | | 200 | mA | Source | 21 |
| DC voltage on any GPIO pin | VDIGPIN | -0.3 | | | V | max is VIOVDD + 0.3 V | 21 |
| Operating ambient temperature range | TA | -40 | | 125 | °C | -I temperature grade | 22 |
| DVDD supply voltage | VDVDD | 1.71 | 3.3 | 3.8 | V | EM0/1 | 22 |
| AVDD supply voltage | VAVDD | 1.71 | 3.3 | 3.8 | V | | 22 |
| IOVDD operating supply voltage | VIOVDD | 1.71 | 3.3 | 3.8 | V | | 22 |
| VREGVDD operating supply voltage | VVREGVDD | 2.2 | 3.3 | 3.8 | V | DCDC in regulation | 22 |
| VREGVDD operating supply voltage | VVREGVDD | 1.8 | 3.3 | 3.8 | V | DCDC in bypass 60 mA load | 22 |
| VREGVDD operating supply voltage | VVREGVDD | 1.71 | 3.3 | 3.8 | V | DCDC not in use. DVDD externally shorted to VREGVDD | 22 |
| DECOUPLE output capacitor | CDECOUPLE | 0.75 | 1 | 2.75 | µF | 1.0 µF ± 10% X8L capacitor used for performance characterization. | 22 |
| HCLK and SYSCLK frequency | fHCLK | | | 80 | MHz | VSCALE2, MODE = WS1 | 22 |
| HCLK and SYSCLK frequency | fHCLK | | | 40 | MHz | VSCALE2, MODE = WS0 | 22 |
| HCLK and SYSCLK frequency | fHCLK | | | 20 | MHz | VSCALE1, MODE = WS0 | 22 |
| PCLK frequency | fPCLK | | | 40 | MHz | VSCALE2 or VSCALE1 | 22 |
| External Clock Input | fCLKIN | | | 40 | MHz | VSCALE2 or VSCALE1, IOVDD ≥ 2.7 V | 22 |
| DCDC regulation DC accuracy | ACCDC | -2.5 | | 4 | % | VVREGVDD ≥ 2.2 V, Steady state in EM0/EM1 mode or EM2/EM3 mode | 23 |
| DCDC regulation total accuracy | ACCTOT | -5 | | 7 | % | All error sources (including DC errors, overshoot, undershoot) | 23 |
| DCDC input voltage range at VREGVDD | VVREGVDD | 2.2 | | 3.8 | V | DCDC in regulation, ILOAD = 60 mA, EM0/EM1 mode | 23 |
| DCDC input voltage range at VREGVDD | VVREGVDD | 1.8 | | 3.8 | V | DCDC in regulation, ILOAD = 5 mA, EM0/EM1 or EM2/EM3 mode | 23 |
| DCDC output load current | ILOAD | | | 60 | mA | EM0/EM1 mode, DCDC in regulation | 23 |
| DCDC output load current | ILOAD | | | 5 | mA | EM2/EM3 mode, DCDC in regulation | 23 |
| DCDC output capacitor | CDCDC | | 4.7 | 10 | µF | 4.7 µF ± 10% X7R capacitor used for performance characterization | 23 |
| DCDC bypass switch resistance | RBYP | | 0.45 | 0.8 | Ω | Bypass switch from VREGVDD to DVDD, VVREGVDD = 1.8 V | 23 |
| DCDC powertrain PFET resistance | RBYP | | 0.6 | 0.9 | Ω | Powertrain PFET switch from VREGVDD to VREGSW, VVREGVDD = 1.8 V | 23 |
| Supply monitor threshold programming range | VCMP_RNG | 2 | | 2.3 | V | Programmable in 0.1 V steps | 23 |
| Supply monitor threshold accuracy | VCMP_ACC | -5 | | 5 | % | Supply falling edge trip point | 23 |
| Thermal resistance junction to ambient, 48QFN | ΘJA | | 27.7 | | °C/W | JEDEC 2s2p, Still Air | 24 |
| Thermal resistance junction to board, 48QFN | ΘJB | | 14.6 | | °C/W | JEDEC 2s2p | 24 |
| Thermal resistance junction to case, 48QFN | ΘJC | | 23 | | °C/W | No Board, temperature controlled heat sink on top of package, all other sides insulated | 24 |
| Flash supply voltage during write or erase | VFLASH | 1.71 | | 3.8 | V | | 32 |
| Flash data retention | RETFLASH | 10 | | | years | | 32 |
| Flash erase cycles before failure | ECFLASH | 10000 | | | cycles | | 32 |
| Program time | tPROG | 41 | 44.4 | 47.9 | µs | one word (32-bits) | 32 |
| Page erase time | tPERASE | 11.8 | 12.5 | 14.6 | ms | | 32 |
| Mass erase time | tMERASE | 47.2 | 50.1 | 58.3 | ms | 512 kB | 32 |
| Program current | IWRITE | | | 2.4 | mA | TA = 25 °C | 32 |
| Page erase current | IERASE | | | 1.9 | mA | TA = 25 °C | 32 |
| HFXO crystal frequency | FHFXO | 38 | 39 | 40 | MHz | | 33 |
| HFXO crystal max ESR | ESRHFXO | | | 60 | Ω | 39.0 MHz | 33 |
| HFRCO frequency accuracy | FHFRCO_ACC | -3 | | 3 | % | For all production calibrated frequencies | 35 |
| FSRCO frequency | FFSRCO | 17.2 | 20 | 21.2 | MHz | | 36 |
| LFRCO frequency accuracy | FLFRCO_ACC | -3 | | 3 | % | | 37 |
| ULFRCO oscillation frequency | FULFRCO | 0.944 | 1 | 1.095 | kHz | | 37 |
| EM2 current, 64 kB RAM retention, RTC from LFXO | IEM2_VS | | 1.33 | | µA | VSCALE0, 64 kB RAM retention, RTC running from LFXO | 25 |
## Materials and finish
As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | PC | | 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. | 90 |
## CAD (KiCad official)
- Symbol: `EFM32PG23B210F128IM48-C`
- Footprint: `Package_DFN_QFN:QFN-48-1EP_6x6mm_P0.4mm_EP4.2x4.2mm`
- 3D model: QFN-48(6x6), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.9 mm nominal QFN height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files: `efm32pg23b210f128im48-c-etched.step` / `efm32pg23b210f128im48-c-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `efm32pg23b210f128im48-c.step` / `efm32pg23b210f128im48-c.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [SKYWORKS/SILICON LABS datasheet](docs/efm32pg23b210f128im48-c-datasheet.pdf) (99 pp, sha256 `a4ad4405a1050471`, retrieved 2026-10-31, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/efm32pg23b210f128im48-c-datasheet.pdf)