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EFM32GG380F1024G-E-QFP100

Public Made by Adom

by adom

SILICON LABS SILICON LABS, LQFP-100(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentembedded processors & controllersefm32gg380f1024g-e-qfp100factory-2.0.0extractor-text
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3D Model

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Symbol & Footprint

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Datasheet

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Contents

README

markdown

EFM32GG380F1024G-E-QFP100

SILICON LABS · SILICON LABS · LQFP-100(14x14)

EFM32GG380F1024G-E-QFP100 from SILICON LABS, in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PA0 bidirectional GPIO PA0 with EBI_AD09, TIM0_CC0, LEU0_RX, I2C0_SDA, PRS_CH0 and GPIO_EM4WU0 alternate functions.
2 PA1 bidirectional GPIO PA1 with EBI_AD10, TIM0_CC1, I2C0_SCL, CMU_CLK1 and PRS_CH1 alternate functions.
3 PA2 bidirectional GPIO PA2 with EBI_AD11, TIM0_CC2, CMU_CLK0 and ETM_TD0 alternate functions.
4 PA3 bidirectional GPIO PA3 with EBI_AD12, TIM0_CDTI0, U0_TX, LES_ALTEX2 and ETM_TD1 alternate functions.
5 PA4 bidirectional GPIO PA4 with EBI_AD13, TIM0_CDTI1, U0_RX, LES_ALTEX3 and ETM_TD2 alternate functions.
6 PA5 bidirectional GPIO PA5 with EBI_AD14, TIM0_CDTI2, LEU1_TX, LES_ALTEX4 and ETM_TD3 alternate functions.
7 PA6 bidirectional GPIO PA6 with EBI_AD15, LEU1_RX, ETM_TCLK and GPIO_EM4WU1 alternate functions.
8 IOVDD_0 power_in Digital IO power supply 0.
9 PB0 bidirectional GPIO PB0 with EBI_A16 and TIM1_CC0 alternate functions.
10 PB1 bidirectional GPIO PB1 with EBI_A17 and TIM1_CC1 alternate functions.
11 PB2 bidirectional GPIO PB2 with EBI_A18 and TIM1_CC2 alternate functions.
12 PB3 bidirectional GPIO PB3 with EBI_A19, PCNT1_S0IN and US2_TX alternate functions.
13 PB4 bidirectional GPIO PB4 with EBI_A20, PCNT1_S1IN and US2_RX alternate functions.
14 PB5 bidirectional GPIO PB5 with EBI_A21 and US2_CLK alternate functions.
15 PB6 bidirectional GPIO PB6 with EBI_A22 and US2_CS alternate functions.
16 VSS power_in Ground.
17 IOVDD_1 power_in Digital IO power supply 1.
18 PC0 bidirectional GPIO PC0 with ACMP0_CH0, DAC0_OUT0ALT/OPAMP_OUT0ALT, EBI_A23, TIM0_CC1, PCNT0_S0IN, US0_TX, US1_TX, I2C0_SDA, LES_CH0 and PRS_CH2 alternate functions.
19 PC1 bidirectional GPIO PC1 with ACMP0_CH1, DAC0_OUT0ALT/OPAMP_OUT0ALT, EBI_A24, TIM0_CC2, PCNT0_S1IN, US0_RX, US1_RX, I2C0_SCL, LES_CH1 and PRS_CH3 alternate functions.
20 PC2 bidirectional GPIO PC2 with ACMP0_CH2, DAC0_OUT0ALT/OPAMP_OUT0ALT, EBI_A25, TIM0_CDTI0, US2_TX and LES_CH2 alternate functions.
21 PC3 bidirectional GPIO PC3 with ACMP0_CH3, DAC0_OUT0ALT/OPAMP_OUT0ALT, EBI_NANDREn, TIM0_CDTI1, US2_RX and LES_CH3 alternate functions.
22 PC4 bidirectional GPIO PC4 with ACMP0_CH4, DAC0_P0/OPAMP_P0, EBI_A26, TIM0_CDTI2, LETIM0_OUT0, PCNT1_S0IN, US2_CLK, I2C1_SDA and LES_CH4 alternate functions.
23 PC5 bidirectional GPIO PC5 with ACMP0_CH5, DAC0_N0/OPAMP_N0, EBI_NANDWEn, LETIM0_OUT1, PCNT1_S1IN, US2_CS, I2C1_SCL and LES_CH5 alternate functions.
24 PB7 bidirectional GPIO PB7 that is also the LFXTAL_P low frequency crystal pin, with TIM1_CC0, US0_TX and US1_CLK alternates.
25 PB8 bidirectional GPIO PB8 that is also the LFXTAL_N low frequency crystal pin, with TIM1_CC1, US0_RX and US1_CS alternates.
26 PA7 bidirectional GPIO PA7 with EBI_CSTFT alternate function.
27 PA8 bidirectional GPIO PA8 with EBI_DCLK and TIM2_CC0 alternate functions.
28 PA9 bidirectional GPIO PA9 with EBI_DTEN and TIM2_CC1 alternate functions.
29 PA10 bidirectional GPIO PA10 with EBI_VSNC and TIM2_CC2 alternate functions.
30 PA11 bidirectional GPIO PA11 with EBI_HSNC alternate function.
31 IOVDD_2 power_in Digital IO power supply 2.
32 VSS power_in Ground.
33 PA12 bidirectional GPIO PA12 with EBI_A00 and TIM2_CC0 alternate functions.
34 PA13 bidirectional GPIO PA13 with EBI_A01 and TIM2_CC1 alternate functions.
35 PA14 bidirectional GPIO PA14 with EBI_A02 and TIM2_CC2 alternate functions.
36 RESETn input Reset input, active low; to apply an external reset source drive this pin low only during reset and let the internal pull-up release reset.
37 PB9 bidirectional GPIO PB9 with EBI_A03 and U1_TX alternate functions.
38 PB10 bidirectional GPIO PB10 with EBI_A04 and U1_RX alternate functions.
39 PB11 bidirectional GPIO PB11 with DAC0_OUT0/OPAMP_OUT0, TIM1_CC2, LETIM0_OUT0 and I2C1_SDA alternate functions.
40 PB12 bidirectional GPIO PB12 with DAC0_OUT1/OPAMP_OUT1, LETIM0_OUT1 and I2C1_SCL alternate functions.
41 AVDD_1 power_in Analog power supply 1.
42 PB13 bidirectional GPIO PB13 that is also the HFXTAL_P high frequency crystal pin, with US0_CLK and LEU0_TX alternates.
43 PB14 bidirectional GPIO PB14 that is also the HFXTAL_N high frequency crystal pin, with US0_CS and LEU0_RX alternates.
44 IOVDD_3 power_in Digital IO power supply 3.
45 AVDD_0 power_in Analog power supply 0.
46 PD0 bidirectional GPIO PD0 with ADC0_CH0, DAC0_OUT0ALT/OPAMP_OUT0ALT, OPAMP_OUT2, PCNT2_S0IN and US1_TX alternate functions.
47 PD1 bidirectional GPIO PD1 with ADC0_CH1, DAC0_OUT1ALT/OPAMP_OUT1ALT, TIM0_CC0, PCNT2_S1IN, US1_RX and DBG_SWO alternate functions.
48 PD2 bidirectional GPIO PD2 with ADC0_CH2, EBI_A27, TIM0_CC1, USB_DMPU, US1_CLK and DBG_SWO alternate functions.
49 PD3 bidirectional GPIO PD3 with ADC0_CH3, OPAMP_N2, TIM0_CC2, US1_CS and ETM_TD1 alternate functions.
50 PD4 bidirectional GPIO PD4 with ADC0_CH4, OPAMP_P2, LEU0_TX and ETM_TD2 alternate functions.
51 PD5 bidirectional GPIO PD5 with ADC0_CH5, OPAMP_OUT2, LEU0_RX and ETM_TD3 alternate functions.
52 PD6 bidirectional GPIO PD6 with ADC0_CH6, DAC0_P1/OPAMP_P1, TIM1_CC0, LETIM0_OUT0, PCNT0_S0IN, US1_RX, I2C0_SDA, LES_ALTEX0, ACMP0_O and ETM_TD0 alternates.
53 PD7 bidirectional GPIO PD7 with ADC0_CH7, DAC0_N1/OPAMP_N1, TIM1_CC1, LETIM0_OUT1, PCNT0_S1IN, US1_TX, I2C0_SCL, CMU_CLK0, LES_ALTEX1, ACMP1_O and ETM_TCLK alternates.
54 PD8 power_in GPIO PD8 that is also BU_VIN, the battery input for the Backup Power Domain, with CMU_CLK1 alternate.
55 PC6 bidirectional GPIO PC6 with ACMP0_CH6, EBI_A05, LEU1_TX, I2C0_SDA, LES_CH6 and ETM_TCLK alternate functions.
56 PC7 bidirectional GPIO PC7 with ACMP0_CH7, EBI_A06, LEU1_RX, I2C0_SCL, LES_CH7 and ETM_TD0 alternate functions.
57 VDD_DREG power_in Power supply for on-chip voltage regulator.
58 VSS power_in Ground.
59 DECOUPLE passive Decouple output for on-chip voltage regulator; an external capacitance of size CDECOUPLE is required at this pin.
60 PE0 bidirectional GPIO PE0 with EBI_A07, TIM3_CC0, PCNT0_S0IN, U0_TX and I2C1_SDA alternate functions.
61 PE1 bidirectional GPIO PE1 with EBI_A08, TIM3_CC1, PCNT0_S1IN, U0_RX and I2C1_SCL alternate functions.
62 PE2 bidirectional GPIO PE2 that is also BU_VOUT (backup power domain power output), with EBI_A09, TIM3_CC2, U1_TX and ACMP0_O alternates.
63 PE3 bidirectional GPIO PE3 that is also BU_STAT (backup mode status), with EBI_A10, U1_RX and ACMP1_O alternates.
64 PE4 bidirectional GPIO PE4 with EBI_A11 and US0_CS alternate functions.
65 PE5 bidirectional GPIO PE5 with EBI_A12 and US0_CLK alternate functions.
66 PE6 bidirectional GPIO PE6 with EBI_A13 and US0_RX alternate functions.
67 PE7 bidirectional GPIO PE7 with EBI_A14 and US0_TX alternate functions.
68 PC8 bidirectional GPIO PC8 with ACMP1_CH0, EBI_A15, TIM2_CC0, US0_CS and LES_CH8 alternate functions.
69 PC9 bidirectional GPIO PC9 with ACMP1_CH1, EBI_A09, TIM2_CC1, US0_CLK, LES_CH9 and GPIO_EM4WU2 alternate functions.
70 PC10 bidirectional GPIO PC10 with ACMP1_CH2, EBI_A10, TIM2_CC2, US0_RX and LES_CH10 alternate functions.
71 PC11 bidirectional GPIO PC11 with ACMP1_CH3, EBI_ALE, US0_TX and LES_CH11 alternate functions.
72 USB_VREGI power_in USB input to internal 3.3 V regulator.
73 USB_VREGO power_out USB decoupling for internal 3.3 V USB regulator and regulator output.
74 PF10 bidirectional GPIO PF10 that is also USB_DM (USB D- pin), with U1_TX alternate function.
75 PF11 bidirectional GPIO PF11 that is also USB_DP (USB D+ pin), with U1_RX alternate function.
76 PF0 bidirectional GPIO PF0 with TIM0_CC0, LETIM0_OUT0, US1_CLK, LEU0_TX, I2C0_SDA and DBG_SWCLK (enabled out of reset with pull-down) alternates.
77 PF1 bidirectional GPIO PF1 with TIM0_CC1, LETIM0_OUT1, US1_CS, LEU0_RX, I2C0_SCL, DBG_SWDIO and GPIO_EM4WU3 alternates.
78 PF2 bidirectional GPIO PF2 with EBI_ARDY, TIM0_CC2, LEU0_TX, ACMP1_O, DBG_SWO and GPIO_EM4WU4 alternate functions.
79 USB_VBUS power_in USB 5.0 V VBUS input.
80 PF12 bidirectional GPIO PF12 that is also USB_ID (USB ID pin).
81 PF5 bidirectional GPIO PF5 with EBI_REn, TIM0_CDTI2, USB_VBUSEN (USB 5 V VBUS enable) and PRS_CH2 alternate functions.
82 IOVDD_5 power_in Digital IO power supply 5.
83 VSS power_in Ground.
84 PF6 bidirectional GPIO PF6 with EBI_BL0, TIM0_CC0 and U0_TX alternate functions.
85 PF7 bidirectional GPIO PF7 with EBI_BL1, TIM0_CC1 and U0_RX alternate functions.
86 PF8 bidirectional GPIO PF8 with EBI_WEn, TIM0_CC2 and ETM_TCLK alternate functions.
87 PF9 bidirectional GPIO PF9 with EBI_REn and ETM_TD0 alternate functions.
88 PD9 bidirectional GPIO PD9 with EBI_CS0 alternate function.
89 PD10 bidirectional GPIO PD10 with EBI_CS1 alternate function.
90 PD11 bidirectional GPIO PD11 with EBI_CS2 alternate function.
91 PD12 bidirectional GPIO PD12 with EBI_CS3 alternate function.
92 PE8 bidirectional GPIO PE8 with EBI_AD00, PCNT2_S0IN and PRS_CH3 alternate functions.
93 PE9 bidirectional GPIO PE9 with EBI_AD01 and PCNT2_S1IN alternate functions.
94 PE10 bidirectional GPIO PE10 with EBI_AD02, TIM1_CC0, US0_TX and BOOT_TX alternate functions.
95 PE11 bidirectional GPIO PE11 with EBI_AD03, TIM1_CC1, US0_RX, LES_ALTEX5 and BOOT_RX alternate functions.
96 PE12 bidirectional GPIO PE12 with EBI_AD04, TIM1_CC2, US0_RX, US0_CLK, I2C0_SDA, CMU_CLK1 and LES_ALTEX6 alternate functions.
97 PE13 bidirectional GPIO PE13 with EBI_AD05, US0_TX, US0_CS, I2C0_SCL, LES_ALTEX7, ACMP0_O and GPIO_EM4WU5 alternate functions.
98 PE14 bidirectional GPIO PE14 with EBI_AD06, TIM3_CC0 and LEU0_TX alternate functions.
99 PE15 bidirectional GPIO PE15 with EBI_AD07, TIM3_CC1 and LEU0_RX alternate functions.
100 PA15 bidirectional GPIO PA15 with EBI_AD08 and TIM3_CC2 alternate functions.

Key specifications

Parameter Value
Manufacturer SILICON LABS
Package LQFP-100(14x14)
Category Embedded Processors & Controllers
Pins 100

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Storage temperature range TSTG -40 150 °C 61
Maximum soldering temperature TS 260 °C Latest IPC/JEDEC J-STD-020 Standard 61
External main supply voltage VDDMAX 0 3.8 V 61
Voltage on any I/O pin VIOPIN -0.3 3.8 V Printed as VDD+0.3 V maximum; 3.8 V is VDD maximum plus 0.3 V is not computed, see max as VDD+0.3 61
Current per I/O pin (sink) IIOMAX_SINK 100 mA 61
Current per I/O pin (source) IIOMAX_SOURCE -100 mA 61
Ambient temperature range TAMB -40 85 °C 61
Operating supply voltage VDDOP 1.98 3.8 V 61
Internal APB clock frequency fAPB 48 MHz 61
Internal AHB clock frequency fAHB 48 MHz 61
EM0 current IEM0 219 240 µA/MHz 48 MHz HFXO, all peripheral clocks disabled, VDD= 3.0 V 62
EM0 current IEM0 209 232 µA/MHz 14 MHz HFRCO, all peripheral clocks disabled, VDD= 3.0 V 62
EM1 current IEM1 80 90 µA/MHz 48 MHz HFXO, all peripheral clocks disabled, VDD= 3.0 V 62
EM1 current IEM1 83 99 µA/MHz 14 MHz HFRCO, all peripheral clocks disabled, VDD= 3.0 V 62
EM2 current IEM2 1.11 1.91 µA RTC prescaled to 1 Hz, 32.768 kHz LFRCO, VDD= 3.0 V, TAMB=25ºC 62
EM2 current IEM2 8.81 21.51 µA RTC prescaled to 1 Hz, 32.768 kHz LFRCO, VDD= 3.0 V, TAMB=85ºC 62
EM3 current IEM3 0.81 1.51 µA VDD= 3.0 V, TAMB=25ºC 62
EM3 current IEM3 8.21 20.31 µA VDD= 3.0 V, TAMB=85ºC 62
EM4 current IEM4 0.02 0.08 µA VDD= 3.0 V, TAMB=25ºC 62
EM4 current IEM4 0.5 2.5 µA VDD= 3.0 V, TAMB=85ºC 62
BOD threshold on falling external supply voltage VBODextthr- 1.74 1.96 V EM0 68
BOD threshold on falling external supply voltage VBODextthr- 1.74 1.98 V EM2 68
BOD threshold on falling internally regulated supply voltage VBODintthr- 1.57 1.7 V 68
BOD threshold on rising external supply voltage VBODextthr+ 1.85 1.98 V 68
POR threshold on rising external supply voltage VPORthr+ 1.98 V 68
Flash erase cycles before failure ECFLASH 20000 cycles 69
Flash data retention RETFLASH 10 years TAMB<85 °C 69
Page erase time tPERASE 20 20.4 20.8 ms LPERASE == 0 69
Device erase time tDERASE 161.6 ms 69
Erase current IERASE 142 mA LPERASE == 0 69
Supply voltage during flash erase and write VFLASH 1.98 3.8 V 69
Input low voltage VIOIL 0.3 V Printed as 0.30×VDD 70
Input high voltage VIOIH 0.7 V Printed as 0.70×VDD 70
Input leakage current IIOLEAK -40 0.1 40 nA High Impedance IO connected to GROUND or VDD 71
I/O pin hysteresis VIOHYST 0.1 V VDD = 1.98 - 3.8 V; printed as 0.10×VDD 71
LFRCO oscillation frequency fLFRCO 31.29 32.768 34.28 kHz VDD= 3.0 V, TAMB=25°C 79
HFRCO oscillation frequency 28 MHz band fHFRCO 27.5 28 28.5 MHz VDD= 3.0 V, TAMB=25ºC 80
HFRCO oscillation frequency 14 MHz band fHFRCO 13.7 14 14.3 MHz VDD= 3.0 V, TAMB=25ºC 80
HFXO supported crystal frequency fHFXO 4 48 MHz 78
ULFRCO oscillation frequency fULFRCO 0.7 1.75 kHz 25°C, 3V 84
ADC input voltage range VADCIN 0 V Single-ended; max printed as VREF 85
ADC clock frequency fADCCLK 13 MHz 85
ADC offset voltage VADCOFFSET -3 0.3 3 mV After calibration, differential 88
ADC differential non-linearity DNLADC -1 0.7 4 LSB VDD= 3.0 V, external 2.5 V reference 88
ADC integral non-linearity INLADC 1.2 3 LSB VDD= 3.0 V, external 2.5 V reference 88
DAC offset voltage VDACOFFSET 2 12 mV After calibration, single-ended 97
OPAMP active current IOPAMP 350 405 µA (OPA2)BIASPROG=0xF, (OPA2)HALFBIAS=0x0, Unity Gain 98
OPAMP input offset voltage VOFFSET -13 0 11 mV Unity Gain, VSS<Vin<VDD, OPAxHCMDIS=0 98
ACMP offset voltage VACMPOFFSET -12 0 12 mV BIASPROG= 0b1010, FULLBIAS=0 and HALFBIAS=0 in ACMPn_CTRL register 102
VCMP offset voltage VVCMPOFFSET -230 -40 190 mV Single-ended 104
Decoupling capacitor CDECOUPLE 1 µF X5R capacitor recommended. Apply between DECOUPLE pin and GROUND 68

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
housing abs exposed to light, it may be necessary to cover the top and sides with an opaque material. For additional Quality and Environmental information, please see: http://www.silabs.com/support/quality/pages/ 422
contacts gold The TQFP64 Package is 10 by 10 mm in size and has a 0.5 mm pin pitch. The TQFP64 Package uses Nickel-Palladium-Gold preplated leadframe. 413

CAD (KiCad official)

  • Symbol: EFM32GG380F1024G-E-QFP100
  • Footprint: Package_QFP:LQFP-100_14x14mm_P0.5mm
  • 3D model: LQFP-100(14x14) (KiCad packages3D, STEP)
  • 3D model files: efm32gg380f1024g-e-qfp100-etched.step / efm32gg380f1024g-e-qfp100-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); efm32gg380f1024g-e-qfp100.step / efm32gg380f1024g-e-qfp100.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: SILICON LABS datasheet (433 pp, sha256 ee792fa615a39cfe, retrieved 2026-10-23, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF